JP3604474B2 - Self-scanning light emitting device - Google Patents

Description

【００３１】
したがって、実際には、図１１（Ｂ）に示すように、負荷抵抗補償回路として、この等価抵抗Ｒ_Ｅ のみを付加すれば良い。
【００３２】
【実施例５】
本実施例は、本発明者らが特開平２−２６３６６８号公報にて開示した自己走査型発光装置であって、本発明を適用できる例の１つである。
【００３３】
本実施例の発光装置の原理を説明するための等価回路図を図１２に示す。
【００３４】
この発光装置は、スイッチ素子Ｔ（−１）〜Ｔ（２）、書き込み用発光素子Ｌ（−１）〜Ｌ（２）からなる。スイッチ素子部分の構成は、ダイオード接続を用いた例を示している。スイッチ素子のゲート電極Ｇ_−１〜Ｇ_１ は、書き込み用発光素子のゲートにも接続される。書き込み用発光素子のアノードには、書き込み信号Ｓ_ｉｎが加えられている。
【００３５】
以下に、この発光装置の動作を説明する。いま、スイッチ素子Ｔ（０）がオン状態にあるとすると、ゲート電極Ｇ_０ の電圧は、Ｖ_ＧＫ（ここでは５ボルトと想定する）より低下し、ほぼ零ボルトとなる。したがって、書き込み信号Ｓ_ｉｎの電圧が、ＰＮ接合の拡散電位（約１ボルト）以上であれば、発光素子Ｌ（０）を発光状態とすることができる。
【００３６】
これに対し、ゲート電極Ｇ_−１は約５ボルトであり、ゲート電極Ｇ_１ は約１ボルトとなる。したがって、発光素子Ｌ（−１）の書き込み電圧は約６ボルト、発光素子Ｌ（１）の書き込み電圧は約２ボルトとなる。これから、発光素子Ｌ（０）のみに書き込める書き込み信号Ｓ_ｉｎの電圧は、約１〜２ボルトの範囲となる。発光素子Ｌ（０）がオン、すなわち発光状態に入ると、書き込み信号Ｓ_ｉｎラインの電圧は約１ボルトに固定されてしまうので、他の発光素子が選択されてしまう、というエラーは防ぐことができる。
【００３７】
発光強度は書き込み信号Ｓ_ｉｎに流す電流量で決められ、任意の強度にて画像書き込みが可能となる。また、発光状態を次の素子に転送するためには、書き込み信号Ｓ_ｉｎラインの電圧を一度零ボルトまでおとし、発光している素子をいったんオフにしておく必要がある。
【００３８】
本実施例の自己走査型発光装置においては、最終段のスイッチ素子に、図５に示したラダー構造１０または図６に示したラダー構造２０を付加すれば良い。
【００３９】
【実施例６】
本実施例は、複数の発光素子を同時に発光できるようにした自己走査型発光装置である。この発光装置の等価回路図を、図１３に示す。
【００４０】
図１２の回路と異なるのは、発光素子を３つずつのブロックとし、１ブロック内の発光素子は１つのスイッチ素子によって制御し、かつ１ブロック内の発光素子にそれぞれ別々の書き込み信号ラインＳ_ｉｎ１，Ｓ_ｉｎ２，Ｓ_ｉｎ３を接続して、発光素子の発光を制御した点である。図中、発光素子Ｌ_１ （−１），Ｌ_２ （−１），Ｌ_３ （−１）、発光素子Ｌ_１（０），Ｌ_２ （０），Ｌ_３ （０）、発光素子Ｌ_１（１），Ｌ_２ （１），Ｌ_３ （１）等が、ブロック化された発光素子を示している。
【００４１】
動作は図９の回路と同じで、１素子ずつＳ_ｉｎによって発光が書き込まれていたものが、同時に複数書き込まれ発光し、それがブロックごとに転送するようになったものである。
【００４２】
いま、ＬＥＤプリンタ等の一般的に知られる光プリンタ用の光源として、この発光装置を用いることを考えると、Ａ４の短辺（約２１ｃｍ）相当のプリントを１６ドット／ｍｍの解像度で印字するためには約３４００ビットの発光素子が必要になる。
【００４３】
実施例４にて説明してきた発光装置では、発光しているポイントは常に一つで、上記の場合ではこの発光の強度を変化させて画像を書き込むことになる。これを用いて光プリンタを形成すると、通常使用されている光プリンタ用ＬＥＤアレイ（これは画像を書き込むポイントに位置するＬＥＤが、同時に発光するよう駆動ＩＣによって制御されている）に比べ、画像書き込み時に３４００倍の輝度が必要となり、発光効率が同じならば３４００倍の電流を流す必要がある。ただし発光時間は、逆に通常のＬＥＤアレイに比べ１／３４００となる。
【００４４】
しかし発光素子は、一般的に電流が増えると加速度的に寿命が短くなる傾向があり、いくらデューティが１／３４００とはいえ従来のＬＥＤプリンタに比べ、寿命が短くなってしまうという問題点を持っていた。
【００４５】
しかしながら本実施例によると、ビット総数が同じ条件で比較すると、この例では１ブロックに３素子が入っているため、実施例５の発光装置に比べて１素子の発光時間は３倍となる。したがって、オン状態の発光素子に流す電流は１／３でよく、実施例５に比べ長寿命化することが可能である。
【００４６】
本実施例では、１ブロックに３素子が含まれる場合を例示したが、この素子数が大きいほうが書き込み電流が小さくて済み、さらに長寿命化をはかることができる。
【００４７】
本実施例の自己走査型発光装置においては、最終段のスイッチ素子に、図５に示したラダー構造１０または図６に示したラダー構造２０を付加すれば良い。
【００４８】
【実施例７】
以下に、デューティをさらに向上することができる自己走査型発光装置の例を、図１４，図１５，図１６を用いて説明する。図１４は本実施例の発光装置のブロック構成図である。
【００４９】
本実施例の発光装置は、シフトレジスタ２００，書き込みスイッチアレイ２０１，リセットスイッチアレイ２０２，発光素子アレイ２０３から構成される。各々のアレイはＮ個の素子からなっており、その番号を（１）〜（Ｎ）とする。
【００５０】
シフトレジスタ２００は、電源Ｖ_１ 、複数の転送パルスφ、およびスタートパルスφ_Ｓ により駆動され、オン状態が転送（自己走査）される。転送方向は、ここでは左から右、すなわち（１）から（Ｎ）としてある。
【００５１】
書き込みスイッチアレイ２０１は、画像信号Ｖ_ＩＮを発光素子アレイ２０３に書き込むスイッチであり、シフトレジスタ２００に同期する。つまり、時刻ｔにオン状態であるシフトレジスタ２００に対応する発光素子アレイ２０３のビットに、画像信号Ｖ_ＩＮ（ｔ）を書き込む働きを有する。
【００５２】
この画像信号Ｖ_ＩＮの書き込みは、本実施例では各ビットとも同じ番号内で行われるようにされている。一度書き込まれた発光情報は、発光素子アレイ２０３に保持される。
【００５３】
一方、シフトレジスタ２００は、同時にリセットスイッチアレイ２０２もアドレスするよう構成されている。ただし、番号（１）のシフトレジスタ出力は番号（２）のリセットスイッチに、番号（２）のシフトレジスタ出力は番号（３）のリセットスイッチになど、１ビット転送方向へ進んだ素子に接続されている。
【００５４】
このリセットスイッチがアドレスされると、発光素子はリセットされる。すなわち、シフトレジスタがオンすると、このシフトレジスタより１ビット転送方向へ進んだ発光素子は、発光状態，非発光状態に関わらず、一旦非発光状態（オフ状態）に戻される。
【００５５】
このような構成になっていれば、画像信号の時間変化が発光素子の位置変化として書き込まれ、発光素子に画像情報が書き込まれて発光による画像パターンが構成される。そして次の画像信号を書き込む際、リセットスイッチにより書き込まれた画像情報は消去され、そのすぐ後に新たな画像情報が書き込まれる。このため、発光素子はほぼ常時点灯に近い状態となり、デューティはほぼ１となる。
【００５６】
ここではシフトレジスタ２００を１つのみ設け、この出力を画像信号書き込み、およびリセットの両方に用いるよう構成したが、シフトレジスタを２つ設け、それぞれ画像信号書き込み用およびリセット用として用いてもよい。
【００５７】
図１５に、図１４で説明した機能を発光サイリスタおよびトランジスタで構成した回路を示す。シフトレジスタ２００は、サイリスタＴ_Ｓ （１）〜Ｔ_Ｓ （４）により構成される。各サイリスタはトランジスタＴｒ_１ ，Ｔｒ_２ で構成され、そのゲートが負荷抵抗Ｒ_Ｌ ，結合用抵抗Ｒ_Ｉ を介して隣接するサイリスタおよび電源Ｖ_１ に接続される。このシフトレジスタの出力はゲートから取り出され、出力電圧Ｖ_Ｏ （１）〜Ｖ_Ｏ （３）と表示されている。（１）〜（３）は各ビットの番号である。図中、転送クロックラインの電流を制限する抵抗は、抵抗Ｒ_ｅ で表している。
【００５８】
書き込みスイッチとして、ＰＮＰトランジスタＴｒ_３ （１）〜Ｔｒ_３ （３）を用い、リセットスイッチとして、ＮＰＮトランジスタＴｒ_４ （１）〜Ｔｒ_４ （３）を用いている。抵抗Ｒ_ｅ は、発光素子に流れる電流を制限する抵抗である。また発光素子として、トランジスタＴｒ_５ ，Ｔｒ_６ の組合せで表示される発光サイリスタを用いている。この発光サイリスタの特性として、一度オンしてしまうと電源を落とすまでオンし続けるという特徴を持ち、これを発光のメモリ機能として利用する。
【００５９】
この回路の動作を、図１６に示すパルスタイミング図を用いて説明する。図１６においてＴ_１ 〜Ｔ_５ は時刻を表す。転送クロックはφ_１ 〜φ_３ であり、φ_１ はＴ_１ 〜Ｔ_２ およびＴ_４ 〜Ｔ_５ の間、φ_２ はＴ_２ 〜Ｔ_３ の間、φ_３ はＴ_３ 〜Ｔ_４ の間がハイレベルとなっている。シフトレジスタ出力Ｖ_Ｏ （１）〜Ｖ_Ｏ （３）はそれぞれφ_１ 〜φ_３ に同期して取り出され、出力はローレベルとして与えられる。画像信号Ｖ_ＩＮは時刻Ｔ_２ 〜Ｔ_３ にハイレベルとなり、ビット番号（２）の発光素子に書き込む。
【００６０】
今、時刻Ｔ_１ 〜Ｔ_２ の間を考える。このときシフトレジスタの出力として、出力Ｖ_Ｏ （１）がローレベルとして取り出される。この出力Ｖ_Ｏ （１）は、書き込みスイッチであるトランジスタＴｒ_３ （１）のベースに接続され、トランジスタＴｒ_３ （１）を書き込み可能状態にする。しかしここで、画像信号Ｖ_ＩＮはローレベルであるから、発光素子への書き込みは行われない。
【００６１】
一方、出力Ｖ_Ｏ （１）は同時にリセットスイッチであるトランジスタＴｒ_４ （２）のベースにも印加される。この出力Ｖ_Ｏ （１）は零ボルト程度まで下がるため、トランジスタＴｒ_４ （２）のエミッタ電圧もほぼ零ボルトとなり、発光素子をオフ状態にしてしまう。したがって、ビット番号（２）の発光素子は、リセットされたことになる。
【００６２】
次に時刻Ｔ_２ 〜Ｔ_３ の間を考える。シフトレジスタ出力はＶ_Ｏ （２）であり、これがＴｒ_３ （２）のベースに印加される。ここで、画像信号Ｖ_ＩＮはハイレベルであるからトランジスタＴｒ_３ （２）に電流が流れ、発光メモリに流れ込む。この電流はトランジスタＴｒ_６ （２）のベース電流となり、これがビット番号（２）の発光素子をオンさせる。この発光は次のリセット信号まで維持される。この時、ビット番号（３）の発光素子は、Ｖ_Ｏ （２）によりリセットされる。
【００６３】
発光素子に流れる電流は抵抗Ｒ_ｅ によって制限され、デューティが大きくなったため少ない電流でよく、高信頼度の発光装置を得ることができる。
【００６４】
この自己走査型発光装置は、光プリンタの書き込みヘッド，ディスプレイ等への応用が考えられ、これらの機器の低価格化，高性能化に大きな寄与をすることができる。
【００６５】
本実施例の自己走査型発光装置においては、シフトレジスト２００の最終段のスイッチ素子に、図１１（Ａ）に示したラダー構造３０または図１１（Ｂ）に示した等価抵抗Ｒ_Ｅ を付加すれば良い。
【００６６】
【実施例８】
本実施例は、特開平４−２３３６７号公報に示された自己走査型発光装置であって、本発明の発光サイリスタを適用できる１つの例である。
【００６７】
実施例の発光装置を図１７に示す。図１７においては、スイッチ素子アレイと発光素子アレイとが、上下に分けて記載されている。
【００６８】
まず、シフトレジスタ機能を有するスイッチ素子アレイについて説明する。Ｓ（−２）〜Ｓ（２）は、スイッチ素子（ＰＮＰＮ構造を有するサイリスタ）である。φ_１ ，φ_２ は、スイッチ素子アレイを駆動する転送クロックである。そして、ＣＬ_１ は転送クロックφ_１ を供給されるクロックラインであり、ＣＬ_２ は転送クロックφ_２ を供給されるクロックラインである。
【００６９】
各スイッチ素子Ｓ（−２）〜Ｓ（２）のゲート電極Ｇ‐ _２ 〜Ｇ_２ の間は、それぞれ結合用ダイオードＤ‐_２〜Ｄ_１ によって、接続されている。このようなダイオード結合方式を採用しているために、スイッチ素子アレイは２相の転送クロックφ_１ ，φ_２ にて情報の転送動作を行うことができる。
【００７０】
また、Ｒ_Ａ１，Ｒ_Ａ２ は、それぞれ各スイッチ素子Ｓ（−２）〜Ｓ（２）のアノードとクロックラインＣＬ_１ ，ＣＬ_２ のいずれか一方とを接続するアノード負荷抵抗である。このアノード負荷抵抗Ｒ_Ａ１，Ｒ_Ａ２ は、各スイッチ素子Ｓ（−２）〜Ｓ（２）のオン状態での電流量を制限するものである。各スイッチ素子Ｓ（−２）〜Ｓ（２）のカソードはそれぞれ接地されている。
【００７１】
さらに、Ｒ_Ｌ１，Ｒ_Ｌ２は、それぞれ各スイッチ素子Ｓ（−２）〜Ｓ（２）のゲートＧ_−２〜Ｇ_２ と電源電圧Ｖ_ＧＫの直流電源とを接続するゲートの負荷抵抗である。このゲート負荷抵抗Ｒ_Ｌ１，Ｒ_Ｌ２は、電源電圧Ｖ_ＧＫの直流電源から各ゲートＧ_−２〜Ｇ_２ に流れる電流量を制限するものである。そして、各ゲートＧ_−２，Ｇ_０ ，Ｇ_２ は、それぞれダイオードＤ_−２′，Ｄ_０ ′，Ｄ_２ ′のカソードに接続されている。
【００７２】
次に、発光素子アレイについて説明する。φ_Ｒ は発光素子（発光サイリスタ）Ｌ（−２），Ｌ（０），Ｌ（２）への情報の書き込み許可／禁止を制御し、かつ書き込まれた状態をリセットするクロックである。そして、ＣＬ_Ｒ はクロックφ_Ｒ を供給する電流供給ラインである。
【００７３】
またＲ_Ａ３は、各発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のアノードと電流供給ラインＣＬ_Ｒ とを接続するアノード負荷抵抗である。このアノード負荷抵抗Ｒ_Ａ３は、各発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のオン状態での電流量を制限するものである。そして、各発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のカソードは、それぞれ接地されている。
【００７４】
さらにＲ_Ｌ３は、各発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のゲートＧ_−２′，Ｇ_０ ′，Ｇ_２ ′と電源電圧Ｖ_ＧＫとを接続するゲート負荷抵抗である。このゲート負荷抵抗Ｒ_Ｌ３は、電源電圧Ｖ_ＧＫの直流電源から、各ゲートＧ_−２′，Ｇ_０ ′，Ｇ_２ ′に流れる電流量を制限するものである。そして、各ゲートＧ_−２′，Ｇ_０ ′，Ｇ_２ ′は、それぞれダイオードＤ_−２′，Ｄ_０ ′，Ｄ_２ ′のアノードに接続されている。
【００７５】
すなわち、図１７においては、スイッチ素子Ｓ（−２），Ｓ（０），Ｓ（２）のゲートが、それぞれダイオードＤ_−２′，Ｄ_０ ′，Ｄ_２ ′を介して、発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のゲートＧ_−２′，Ｇ_０ ′，Ｇ_２ ′に個々に接続されている。
【００７６】
次に、スイッチ素子アレイの部分の動作を説明する。今、スタートパルスφ_Ｓ として、ハイレベルまたはローレベルの電圧がスイッチ素子Ｓ（−３）のアノード（図示せず）に供給されたとする。この場合に、ハイレベルの電圧が、電源電圧Ｖ_ＧＫに拡散電位Ｖ_ｄｉｆ を加えた電圧以上に高ければ、スイッチ素子Ｓ（−３）はオン状態になる。そして、次に供給されるスタートパルスφ_Ｓ のローレベルの電圧が、スイッチ素子Ｓ（−３）のオン状態維持電圧より低ければ、Ｓ（−３）はオフ状態となる。
【００７７】
オン状態では、スイッチ素子Ｓ（−３）のゲート電位はほぼ零ボルトとなり、オフ状態ではゲート電圧は電源電圧Ｖ_ＧＫと同じ電圧になる。スイッチ素子Ｓ（−３）のゲート電位が零ボルトになれば、結合用ダイオードＤ_−３（図示せず）によって、スイッチ素子Ｓ（−２）のゲート電位が低下する。そして、スイッチ素子Ｓ（−２）のターンオン電圧も低下する。したがって、転送クロックφ_２ によって、スイッチ素子Ｓ（−２）をオン状態に設定することができる。
【００７８】
このオン状態はφ_１ ，φ_２ によって順次、図１７の右方向へ転送されていく。つまり、スタートパルスφ_Ｓ のハイレベルの電圧によって、スイッチ素子アレイにオン状態が書き込まれ、それが順次右方向へ転送されていくことになる。
【００７９】
ただし、全てのビットがオン状態にある場合に、このオン状態を転送することは、このスイッチ素子アレイの動作原理上から不可能であって、１ビットおきにオンとオフを繰り返して転送することになる。すなわち、スタートパルスφ_Ｓ の波形も、転送パルスφ_１ ，φ_２ に同期して、ハイレベルとローレベルとを交互に送る必要がある。
【００８０】
今、偶数ビットのみのオン状態とオフ状態に有効な情報があるものとして、オン状態を１、オフ状態を０とすると、スタートパルスφ_Ｓ によって１または０が書き込まれ、転送クロックφ_１ ，φ_２ によって、その１，０が転送されて行くことになる。このようにして、１または０という信号（情報）がスイッチ素子アレイに書き込まれる。
【００８１】
次に、発光素子Ｌ（−２）（Ｌ（０），Ｌ（２））の動作について説明する。仮に、Ｌ（−２）が０であるとすると、クロックφ_Ｒ の電圧が零ボルトであれば、発光素子Ｌ（−２）はオン状態とはならない。すなわち、発光素子Ｌ（−２）は書き込み禁止の状態に設定される。クロックφ_Ｒ の電圧が、発光素子Ｌ（−２）のオン状態維持電圧からＶ_ＧＫ＋Ｖ_ｄｉｆ の間の電圧に設定されたとすると、発光素子Ｌ（−２）は書き込み許可の状態に設定される。そして、ゲートＧ_−２′の電位が変化させられることによって、発光素子Ｌ（−２）はオン状態に設定可能となる。
【００８２】
さて、スイッチ素子アレイから発光素子アレイへの情報の書き込みについて説明する。スイッチ素子アレイは、前述したように１または０信号が書き込まれる。最後のビットまで書き込まれた段階で、転送クロックφ_１ ，φ_２ をそれぞれローレベル，ハイレベルの状態に維持される。これによって、情報の転送動作が終了し、スイッチ素子アレイに書き込まれた情報は保持される（特に、偶数ビットにおいて保持されている）。
【００８３】
スイッチ素子アレイの偶数ビットにおいて、オン状態のスイッチ素子Ｓのゲート電位はほぼ零ボルトであり、オフ状態のスイッチ素子Ｓのゲート電位は、Ｖ_ｄｉｆ の約２倍以上である。なお、オフ状態のスイッチ素子Ｓのゲート電位については、転送方向に対して逆方向に位置する最も隣接する偶数ビットがオン状態の場合にＶ_ｄｉｆ の約２倍であり、それ以外はＶ_ｄｉｆ の約２倍の電圧よりも大きくなる。なお、ここでＶ_ｄｉｆ はＰＮ接合の拡散電位である。
【００８４】
スイッチ素子Ｓ（−２），Ｓ（０），Ｓ（２）のそれぞれのゲート電圧は、ダイオードＤ_−２′，Ｄ_０ ′，Ｄ_２ ′によって対応する発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のゲートＧ_−２′，Ｇ_０ ′，Ｇ_２ ′に伝達される。したがって、発光素子Ｌ（−２），Ｌ（０），Ｌ（２）のゲート電圧は、オン状態の場合でＶ_ｄｉｆ となり、オフ状態の場合でＶ_ｄｉｆ の３倍以上となる。そしてオン状態の場合で、発光素子のターンオン電圧はＶ_ｄｉｆ の２倍となり、オフ状態でＶ_ｄｉｆ の４倍となる。
【００８５】
一方、クロックφ_Ｒ については、いったん零ボルトに設定して全体の発光をなくし（すなわち、リセット）、その後にハイレベル電位Ｖ_ＨＲまで上昇させる。この電圧φ_ＨＲとして
２Ｖ_ｄｉｆ ＜Ｖ_ＨＲ＜４Ｖ_ｄｉｆ
の範囲に設定されていると、オン状態のスイッチ素子Ｓに対応する発光素子Ｌがオン状態となり、オフ状態のスイッチ素子Ｓの対応する発光素子Ｌはオフ状態のままになる。
【００８６】
したがって、スイッチ素子アレイに書き込まれた１，０の情報が、そのまま発光素子アレイに書き込まれることになる。
【００８７】
この後、電圧Ｖ_ＨＲは発光素子のオン状態維持電圧以上であってＶ_ｄｉｆ の２倍の電圧未満の値に再設定される。このことにより、発光素子Ｌは、スイッチ素子Ｓのゲート電位に影響されなくなり、書き込まれた情報を保持し続ける。そして、発光素子アレイが情報の保持状態にある間に、前述と同様にして、スイッチ素子アレイには次の情報が書き込まれる。
【００８８】
やがて、クロックφ_Ｒ がローレベル電圧に設定されて、各発光素子Ｌがリセットされる。リセット後、再び情報が発光素子アレイに書き込まれる。以上のようにして、一連の動作が繰り返し行われる。
【００８９】
次に図１７に示す発光装置を、光プリンタ用の書き込み光源に適用した場合について述べる。
【００９０】
例えば、発光装置が２０４８ビットの発光素子Ｌを有するものとすると、スイッチ素子Ｓはその倍の４０９６ビットを必要とする。光プリンタにおける書き込み光源の電流量は約５ｍＡであるから、全てのビットの発光素子Ｌが発光状態であるとすると、約１０Ａという電流が流れる。
【００９１】
一方、スイッチ素子Ｓからの情報転送のための電流は、ゲート負荷抵抗Ｒ_Ｌ３＝３０ｋΩの場合に０．５ｍＡであることが実験的にわかっているので、全てのビットの発光素子が発光状態であれば、１Ａ程度である。なお、この情報転送のための電流量は、光プリンティングに必要な１０Ａに比べ１割程度であり、実用上問題のない値である。
【００９２】
また、スイッチ素子Ｓからの情報が、発光素子Ｌに移動させられた段階でクロックφ_１ ，φ_２ の電圧を一旦零ボルトに低下させることにより、スイッチ素子アレイ全体がオフ状態となりリセットが行われる。この方法を用いた場合には、スイッチ素子Ｓがオン状態になる時間が考慮されると、等価的に電流値が下がることとなる。つまり、前述の１Ａに比べて等価的に０．５Ａ程度まで下がったことになる。
【００９３】
発光素子Ｌの２０４８ビットに対して、スタートパルスφ_Ｓ が供給されるデータ入力端（図示せず）が１つだけでは、情報の転送速度はかなり高速であることが必要である。この点については、データ入力端を複数設けることによって、情報の転送速度を低下させることができる。例えば、通常６４ビットまたは１２８ビットを一単位として発光素子Ｌのチップが形成され、このチップごとに情報が入力されてもよい。
【００９４】
１２８ビットごとにデータ入力を並列に行った場合、２０４８ビットに対して２０個のデータ入力端を有することになる。このため、情報の転送速度は１／２０でよいことになる。したがって、発光装置は余裕のある動作を行うことができる。
【００９５】
なお、発光素子Ｌの出力光の光量のばらつきを防ぐために、アノード負荷抵抗Ｒ_Ａ３をレーザ等により微調整することが可能である。このことによって、出力光のばらつきのない発光装置を得ることができる。
【００９６】
また、図１７では、スイッチ素子アレイにおける偶数ビットの右側に接続される結合用ダイオードＤ_−２，Ｄ_０ の特性と、奇数ビットの右側に接続される結合用ダイオードＤ_−１，Ｄ_１ の特性とが異なっている。したがって、偶数ビットと奇数ビットとで動作電流等を分けて最適化することが重要である。このために、Ｒ_Ｌ２＜Ｒ_Ｌ１，Ｒ_Ａ１＜Ｒ_Ａ２に設定するほうが望ましく、この場合には発光装置はより安定で高速な動作を行い得る。
【００９７】
さらに、図１７では、スイッチ素子アレイにダイオード結合方式と呼ばれる構成を採用しているが、結合方式はこれに限られず、抵抗結合方式であってもよい。
【００９８】
本実施例においては、スイッチ素子アレイがダイオード結合方式の場合には、最終段のスイッチ素子に、図５に示したラダー構造１０または図６に示したラダー構造２０を付加すれば良い。また、スイッチ素子アレイが抵抗結合方式の場合には、最終段のスイッチ素子に、図１１（Ａ）に示したラダー構造３０または図１１（Ｂ）に示した等価抵抗Ｒ_Ｅ を付加すれば良い。
【００９９】
【発明の効果】
本発明によれば、発光素子アレイまたはスイッチ素子アレイの終端部に、負荷抵抗補償回路を設けているので、オン状態へのスイッチング速度はほぼ一定となり、全発光素子または全スイッチ素子を通じて均一なスイッチング速度を実現することができる。
【図面の簡単な説明】
【図１】自己走査型発光装置を示す図である。
【図２】図１の発光装置のゲート電位勾配を説明する図である。
【図３】図１の発光装置の終端付近のゲート電位勾配を説明する図である。
【図４】終端付近の負荷抵抗の変化を示すグラフである。
【図５】実施例１の回路図である。
【図６】実施例２の回路図である。
【図７】実施例２における終端付近の負荷抵抗の変化を示すグラフである。
【図８】実施例２の最終段の発光サイリスタとダイオードの構造を示す断面図である。
【図９】実施例３の回路図である。
【図１０】本発明を適用できる実施例４の発光装置の回路図である。
【図１１】実施例４の発光装置に付加される負荷抵抗補償回路を示す図である。
【図１２】本発明を適用できる実施例５の発光装置の回路図である。
【図１３】本発明を適用できる実施例６の発光装置の回路図である。
【図１４】本発明を適用できる実施例７の発光装置のブロック図である。
【図１５】図１４の発光装置の等価回路図である。
【図１６】図１４の発光装置の駆動方法を示すパルスタイミング図である。
【図１７】本発明を適用できる実施例８の発光装置の回路図である。
【符号の説明】
Ｔ 発光サイリスタ
Ｄ 結合用ダイオード
Ｒ_Ｌ ゲート負荷抵抗
Ｒ_Ｉ 結合用抵抗
Ｔｒ トランジスタ
１０ ラダー構造の負荷抵抗補償回路
２０ 終端抵抗による負荷抵抗補償回路
３０ ラダー構造の終端抵抗による負荷抵抗補償回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a self-scanning light emitting device formed by integrating a large number of light emitting elements on the same substrate.
[0002]
[Prior art]
A light emitting element array in which a large number of light emitting elements are integrated on the same substrate is used as a writing light source for an optical printer or the like in combination with its driving IC. The present inventors have paid attention to a light-emitting thyristor having a PNPN structure as a component of a light-emitting element array, and have already filed patent applications (Japanese Patent Application Laid-Open Nos. 1-238962 and 2-14584, and Japanese Unexamined Patent Publication (Kokai) No. 2-92650 and Japanese Unexamined Patent Publication (Kokai) No. 2-92651) have shown that the light source for an optical printer can be easily mounted, the pitch of the light emitting elements can be reduced, and a compact self-scanning light emitting device can be manufactured.
[0003]
As an example of these inventions made by the present inventors, a light-emitting device having a light-emitting element array capable of self-scanning by two-phase clock driving using potential coupling by a diode disclosed in Japanese Patent Application Laid-Open No. 2-14584 is described. This is shown in FIG. φ₁, Φ₂Are transfer clock pulses whose ratio (duty ratio) between the high-level time and the low-level time is approximately 1: 1 as shown in FIG._GKIs a power supply (usually 5V). T₁~ T₅Is a light emitting thyristor used as a light emitting element, D₁~ D₅Is a potential coupling diode, G₁~ G₅Is the light emitting thyristor T₁~ T₅Gate electrode. R_LIs the load resistance of the gate electrode, which limits the current to the gate electrode.
[0004]
The operation will be briefly described. First, transfer clock pulse φ₂Is high level and the light emitting thyristor₂Is in an ON state (light emitting state). At this time, the gate electrode G₂Is V_GKFrom 5V to almost 0V. The effect of this potential drop is₂Gate electrode G₃To about 1 V (diode D₂(Forward rising voltage of However, the diode D₁Is in a reverse-biased state, so that the gate electrode G₁Is not connected to the gate electrode G₁Remains at 5V. Since the turn-on potential of the light emitting thyristor is approximated by the gate electrode potential + the diffusion potential of the PN junction (about 1 V), the next transfer clock pulse φ₁Is about 2 V (the light-emitting thyristor T₃Voltage required to turn on the thyristor) and about 4 V (light-emitting thyristor T).₅Voltage required to turn on the light-emitting thyristor T)₃Only the light-emitting thyristors can be turned on and the other light-emitting thyristors can be kept off. Therefore, the light emission state is transferred by two transfer clock pulses.
[0005]
[Problems to be solved by the invention]
The switching speed in the light emitting state is determined by the CR time constant on the gate electrode side of the light emitting thyristor to be turned on. FIG. 2A shows a light emitting thyristor T₂Shows the gate potential when is turned on. The gate potential is the light emitting thyristor T₂To T₃, T₄, T₅, T₆, T₇To 0, 1, 2, 3, 4, and 5V. FIG. 2B shows a gate potential gradient. Under such a gate potential gradient, the gate electrode G₂, G₃, G₄, G₅, G₆Load resistance R connected to_LCurrent flows through Now, each load resistance R_LIs 100 kΩ, the light-emitting thyristor T to be turned on next₃Gate electrode G₃When viewed from above, it appears that a load resistance R of about 30 kΩ is equivalently connected. When the parasitic capacitance is C, the switching speed of the light emitting thyristor is determined by the time constant CR as described above.
[0006]
As the light-emitting state of the light-emitting thyristor is transferred, the gate potential gradient in FIG. 2B also shifts as it is. The flowing current decreases and the equivalent resistance R increases.
[0007]
This state is shown in FIG. 32 bits for light emitting device, T for last light emitting thyristor₃₂As now, the light emitting thyristor T₂₉Is turned on. Light emitting thyristor T₂₉, T₃₀, T₃₁, T₃₂The potential gradient of the gate is as shown in FIG. In this state, the light-emitting thyristor T to be turned on next₃₀Gate electrode G₃₀The load resistance R seen from the viewpoint becomes equivalently larger than 30 kΩ, and the last light emitting thyristor T₃₂The load resistance when turning on is R_L(100 kΩ). FIG. 4 is a graph showing such a change in the load resistance near the termination.
[0008]
As the ON state of the light-emitting thyristor approaches the end, the equivalent load resistance R increases. As a result, the CR time constant increases, the switching speed decreases near the end, and a uniform switching speed through all light-emitting thyristors is obtained. The problem that it cannot be performed arises.
[0009]
An object of the present invention is to provide a structure of a self-scanning light emitting device which solves such a problem.
[0010]
[Means for Solving the Problems]
According to the present invention, a plurality of light emitting elements having a threshold voltage or a threshold current control electrode are arranged, and the control electrode of each light emitting element is connected to a control electrode of at least one light emitting element located near the light emitting element by a connection resistor. Alternatively, the power supply line is connected to the control electrode of each light-emitting element via a load resistor, and the clock pulse line is connected to each light-emitting element. Self-scanning light emitting device
A load resistance compensating circuit is provided after the connection resistor or the electric element in the last stage.
[0011]
According to the present invention, a plurality of switch elements each having a threshold voltage or threshold current control electrode for a switching operation are arranged, and the control electrode of at least one switch element located near the control electrode of each switch element is provided. Connected via a connection resistor or an electrically unidirectional electrical element, a power supply line is connected to a control electrode of each switch element via a load resistor, and a clock pulse line is connected to each switch element. A switching element array formed by connection,
A light-emitting element array comprising a plurality of light-emitting elements having threshold voltage or threshold current control electrodes,
In a self-scanning light emitting device in which each control electrode of the light emitting element array is electrically connected to a control electrode of the switch element and a line for applying a current for light emission to each light emitting element is provided.
A load resistance compensating circuit is provided after the connection resistor or the electric element in the last stage.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1
FIG. 5 shows an embodiment in which the present invention is applied to the self-scanning light emitting device of FIG. At the end of the light emitting thyristor array, four diodes D₀And four load resistors R_LA ladder structure 10 is added to compensate for an increase in load resistance. By adding such a load resistance compensating circuit having a ladder structure, the time constant on the gate side of the light emitting thyristor does not change even if the light emission state is transferred to the end of the array.₃₂Until the light emission ends, the switching speed of each light emitting thyristor is the same.
[0013]
Embodiment 2
FIG. 6 shows a circuit according to the second embodiment of the present invention. In this embodiment, since the ladder structure of the load resistor and the diode occupies an area in the embodiment of FIG. 5, the diode D in the final stage is used to reduce the occupied area.₃₂In this case, an increase in load resistance is compensated for by adding only a resistor to the load. Specifically, a load resistance R of 100 kΩ_LAre terminating resistors (100 kΩ / 3) 20 of a ladder structure in which three are connected in parallel.
[0014]
FIG. 7 shows a calculation example of the load resistance distribution when a terminal resistance of 100 kΩ / 3 is added to the final diode. As the end is approached, the load resistance slightly decreases, but this is not a problem in practical use.
[0015]
Embodiment 3
In the specific semiconductor structure of the circuit of the second embodiment, a light emitting thyristor and a diode connected to its gate are formed on one island of the PNPN structure. FIG. 8 shows the last light emitting thyristor T₃₂And diode D₃₂FIG.
[0016]
On the N-type substrate 1, an N-type semiconductor layer 24, a P-type semiconductor layer 23, an N-type semiconductor layer 22, and a P-type semiconductor layer 21 are sequentially stacked. Light emitting thyristor T with PNPN structure (21, 22, 23, 24)₃₂Is formed and the diode D is formed in the PN structure (21, 22).₃₂Is formed. Diode D₃₂Is constructed using the structure of the light emitting thyristor, so that the diode D₃₂Portion constitutes a parasitic thyristor together with the lower semiconductor layers 23 and 24. When this parasitic thyristor is turned on, the terminal resistance (R_L/ 3) If the current flowing through 20 is equal to or greater than the holding current of the parasitic thyristor,₃₂Is turned off, the parasitic thyristor keeps on, which may cause inconvenience in operation.
[0017]
Therefore, in the present embodiment, the last stage diode D₃₂Is removed. FIG. 9 shows the configuration.
[0018]
Embodiment 4
In the following examples, a self-scanning light emitting device to which the present invention can be applied will be described.
[0019]
FIG. 10 shows an equivalent circuit diagram of the light emitting device of this embodiment. The light emitting thyristors T (−2) to T (+2) are used as the light emitting elements, and the light emitting thyristors T (−2) to T (+2) each have a gate electrode G._-2~ G₊₂Is provided. Each gate electrode has a load resistance R_LSupply voltage V through_GKIs applied. In addition, each gate electrode G_-2~ G₊₂Is the resistance R to create an interaction_IAre electrically connected via In addition, three transfer clock lines (φ₁, Φ₂, Φ₃) Are connected every third element (as repeated).
[0020]
The operation will be described first.₃Becomes high level, and the light emitting thyristor T (0) is turned on. At this time, due to the characteristics of the three-terminal thyristor, the gate electrode G₀Is reduced to near zero volts. Power supply voltage V_GKIs 5 volts, the load resistance R_L, Interaction resistance R_IThe gate voltage of each light emitting thyristor is determined from this network. Then, the gate voltage of the element close to the light emitting thyristor T (0) decreases most, and thereafter, the gate voltage increases as the distance from T (0) increases. This can be expressed as:
[0021]
V_G0<V_G1= V_G-1<V_G2= V_G-2              (1)
The difference between these voltages is the load resistance R_L, Interaction resistance R_ICan be set by appropriately selecting the value of.
[0022]
Turn-on voltage V on the anode side of the three-terminal thyristor_ONIs the diffusion potential V_difIt is known that only a high voltage results.
[0023]
V_ON≒ V_G+ V_dif          (2)
Therefore, the voltage applied to the anode is determined by this turn-on voltage V_ONIf it is set higher, the light emitting thyristor will be turned on.
[0024]
Now, with the light-emitting thyristor T (0) turned on, the next transfer clock pulse φ₁High-level voltage V_HIs applied. This clock pulse φ₁Is simultaneously applied to the light emitting thyristors T (+1) and T (−2), but the high level voltage V_HIs set in the following range, only the light emitting thyristor T (+1) can be turned on.
[0025]
V_G-2+ V_dif> V_H> V_{G + 1}+ V_dif    (3)
This means that the light emitting thyristors T (0) and T (+1) are simultaneously turned on. And the clock pulse φ₃When the high-level voltage is turned off, the light-emitting thyristor T (0) is turned off, and the on-state transfer is completed.
[0026]
As described above, in this embodiment, by connecting the gate electrodes of the light emitting thyristors by the resistance network, the light emitting thyristors can have a transfer function.
[0027]
From the principle described above, the transfer clock φ₁, Φ₂, Φ₃Of the light-emitting thyristors are sequentially transferred if the high-level voltages are set so as to slightly overlap each other in order. That is, the light emitting points are sequentially transferred, and a self-scanning light emitting device can be realized.
[0028]
In such a self-scanning light emitting device, as shown in FIG.₃₂And a load resistance R as a load resistance compensation circuit._LAnd interaction resistance R_IAnd a terminating resistor 30 having a ladder structure consisting of
[0029]
Since this ladder structure consists of only a resistor, its equivalent resistance R_EIs represented by the following equation.
[0030]
(Equation 1)

[0031]
Therefore, in practice, as shown in FIG. 11B, this equivalent resistance R_EIt is only necessary to add only.
[0032]
Embodiment 5
This embodiment is a self-scanning light-emitting device disclosed by the present inventors in Japanese Patent Application Laid-Open No. 2-263668, and is one of the examples to which the present invention can be applied.
[0033]
FIG. 12 shows an equivalent circuit diagram for explaining the principle of the light emitting device of this embodiment.
[0034]
This light-emitting device includes switch elements T (-1) to T (2) and write light-emitting elements L (-1) to L (2). The configuration of the switch element portion shows an example using diode connection. Gate electrode G of switch element_-1~ G₁Is also connected to the gate of the light emitting element for writing. The write signal S is applied to the anode of the light emitting element for writing._inHas been added.
[0035]
The operation of the light emitting device will be described below. Now, assuming that the switching element T (0) is in the ON state, the gate electrode G₀Voltage is V_GK(Here, it is assumed to be 5 volts) and becomes almost zero volt. Therefore, the write signal S_inIs equal to or higher than the diffusion potential of the PN junction (about 1 volt), the light emitting element L (0) can be made to emit light.
[0036]
On the other hand, the gate electrode G_-1Is about 5 volts and the gate electrode G₁Is about 1 volt. Therefore, the writing voltage of the light emitting element L (-1) is about 6 volts, and the writing voltage of the light emitting element L (1) is about 2 volts. From now on, the write signal S that can be written only to the light emitting element L (0)_inWill be in the range of about 1-2 volts. When the light emitting element L (0) is turned on, that is, enters the light emitting state, the write signal S_inSince the line voltage is fixed at about 1 volt, an error that another light emitting element is selected can be prevented.
[0037]
The emission intensity is the write signal S_inIs determined by the amount of current flowing through the device, and an image can be written at an arbitrary intensity. In order to transfer the light emission state to the next element, the write signal S_inIt is necessary to reduce the voltage of the line to zero volt once and to turn off the light emitting element once.
[0038]
In the self-scanning light emitting device of this embodiment, the ladder structure 10 shown in FIG. 5 or the ladder structure 20 shown in FIG.
[0039]
Embodiment 6
The present embodiment is a self-scanning light-emitting device in which a plurality of light-emitting elements can emit light simultaneously. FIG. 13 shows an equivalent circuit diagram of the light emitting device.
[0040]
12 is different from the circuit in FIG. 12 in that the light emitting elements in each block are three blocks, and the light emitting elements in one block are controlled by one switch element._in1, S_in2, S_in3 is connected to control the light emission of the light emitting element. In the figure, the light emitting element L₁  (-1), L₂  (-1), L₃  (-1), light emitting element L₁(0), L₂  (0), L₃  (0), light emitting element L₁(1), L₂  (1), L₃  (1) And the like indicate blocked light emitting elements.
[0041]
The operation is the same as that of the circuit of FIG._inIn this case, a plurality of light-emissions are written, and a plurality of light-emissions are written at the same time to emit light, and the light is transferred for each block.
[0042]
Considering the use of this light emitting device as a light source for a generally known optical printer such as an LED printer, a print corresponding to the short side of A4 (about 21 cm) is printed at a resolution of 16 dots / mm. Requires a light emitting element of about 3400 bits.
[0043]
In the light emitting device described in the fourth embodiment, there is always one light emitting point, and in the above case, an image is written by changing the intensity of this light emission. When an optical printer is formed by using this, an image writing LED is compared with a commonly used LED array for an optical printer (which is controlled by a driving IC so that LEDs located at points where an image is written are emitted simultaneously). Sometimes a luminance of 3400 times is required, and if the luminous efficiency is the same, a current of 3400 times needs to flow. However, the light emission time is 1/3400 of that of a normal LED array.
[0044]
However, the light emitting element generally has a tendency to shorten its life at an accelerating rate when the current increases, and has a problem that the life is shorter than that of a conventional LED printer even though the duty is 1/3400. I was
[0045]
However, according to this embodiment, when the total number of bits is compared under the same condition, in this example, three elements are included in one block.5The light emitting time of one element is three times as long as that of the light emitting device. Therefore, the current flowing through the light emitting element in the ON state may be reduced to 1/3.5It is possible to extend the life as compared to
[0046]
In this embodiment, the case where one block includes three elements has been exemplified. However, the larger the number of elements, the smaller the write current and the longer the life.
[0047]
In the self-scanning light emitting device of this embodiment, the ladder structure 10 shown in FIG. 5 or the ladder structure 20 shown in FIG.
[0048]
Embodiment 7
Hereinafter, an example of a self-scanning light emitting device capable of further improving the duty will be described with reference to FIGS. 14, 15 and 16. FIG. Figure14FIG. 2 is a block diagram of the light emitting device of the present embodiment.
[0049]
The light emitting device of this embodiment includes a shift register 200, a write switch array 201, a reset switch array 202, and a light emitting element array 203. Each array is composed of N elements, and their numbers are (1) to (N).
[0050]
The shift register 200 has a power supply V₁, A plurality of transfer pulses φ, and a start pulse φ_SAnd the ON state is transferred (self-scanning). Here, the transfer direction is from left to right, that is, (1) to (N).
[0051]
The write switch array 201 outputs the image signal V_INIs written into the light emitting element array 203 and is synchronized with the shift register 200. That is, the bit of the light emitting element array 203 corresponding to the shift register 200 which is in the ON state at the time t is set to the image signal V._INIt has the function of writing (t).
[0052]
This image signal V_INIn this embodiment, each bit is written in the same number. The light-emitting information once written is held in the light-emitting element array 203.
[0053]
On the other hand, the shift register 200 is configured to address the reset switch array 202 at the same time. However, the output of the shift register of the number (1) is connected to the reset switch of the number (2), and the output of the shift register of the number (2) is connected to the reset switch of the number (3). ing.
[0054]
When the reset switch is addressed, the light emitting element is reset. That is, when the shift register is turned on, the light emitting element that has advanced in the 1-bit transfer direction from the shift register is once returned to the non-light emitting state (off state) regardless of the light emitting state or the non-light emitting state.
[0055]
With such a configuration, a time change of the image signal is written as a position change of the light emitting element, and image information is written in the light emitting element to form an image pattern by light emission. Then, when writing the next image signal, the image information written by the reset switch is erased, and immediately thereafter, new image information is written. For this reason, the light emitting element is almost always in a state of almost lighting, and the duty is substantially 1.
[0056]
Here, only one shift register 200 is provided and this output is used for both image signal writing and resetting. However, two shift registers may be provided and used for image signal writing and resetting, respectively.
[0057]
FIG. 15 shows a circuit in which the function described in FIG. 14 is configured by a light emitting thyristor and a transistor. The shift register 200 has a thyristor T_S(1)-T_SIt is constituted by (4). Each thyristor is a transistor Tr₁, Tr₂The gate of which is a load resistance R_L, Coupling resistor R_IThyristor and power supply V₁Connected to. The output of this shift register is taken out from the gate, and the output voltage V_O(1) -V_O(3) is displayed. (1) to (3) are the numbers of each bit. In the figure, a resistor for limiting the current of the transfer clock line is a resistor R_eIt is represented by
[0058]
As a write switch, a PNP transistor Tr₃(1)-Tr₃Using (3), an NPN transistor Tr is used as a reset switch.₄(1)-Tr₄(3) is used. Resistance R_eIs a resistor that limits the current flowing through the light emitting element. As a light emitting element, a transistor Tr₅, Tr₆Are used. As a characteristic of the light emitting thyristor, once it is turned on, it is kept on until the power is turned off, and this is used as a light emitting memory function.
[0059]
The operation of this circuit will be described with reference to a pulse timing chart shown in FIG. In FIG. 16, T₁~ T₅Represents time. The transfer clock is φ₁~ Φ₃And φ₁Is T₁~ T₂And T₄~ T₅During, φ₂Is T₂~ T₃During, φ₃Is T₃~ T₄Is at a high level. Shift register output V_O(1) -V_O(3) is φ₁~ Φ₃And the output is given as a low level. Image signal V_INIs time T₂~ T₃At a high level, and write to the light emitting element of bit number (2).
[0060]
Now, time T₁~ T₂Think between. At this time, the output V_O(1) is taken out as a low level. This output V_O(1) The transistor Tr which is a write switch₃The transistor Tr is connected to the base of (1).₃(1) is set to a writable state. However, here, the image signal V_INIs at a low level, so that writing to the light emitting element is not performed.
[0061]
On the other hand, output V_O(1) is a transistor Tr which is a reset switch at the same time.₄It is also applied to the base of (2). This output V_O(1) Since the voltage drops to about zero volt, the transistor Tr₄The emitter voltage in (2) also becomes almost zero volt, and the light emitting element is turned off. Therefore, the light emitting element of the bit number (2) is reset.
[0062]
Next, at time T₂~ T₃Think between. The shift register output is V_O(2), which is Tr₃(2) is applied to the base. Here, the image signal V_INIs a high level, so the transistor Tr₃A current flows through (2) and flows into the light emitting memory. This current is applied to the transistor Tr₆This becomes the base current of (2), which turns on the light emitting element of bit number (2). This light emission is maintained until the next reset signal. At this time, the light emitting element of bit number (3)_OReset by (2).
[0063]
The current flowing through the light emitting element is a resistor R_eAnd the duty is increased, a small current is required, and a highly reliable light emitting device can be obtained.
[0064]
This self-scanning light-emitting device can be applied to a writing head, a display, and the like of an optical printer, and can greatly contribute to cost reduction and high performance of these devices.
[0065]
In the self-scanning light-emitting device of this embodiment, the ladder structure 30 shown in FIG. 11A or the equivalent resistance R shown in FIG._EMay be added.
[0066]
Embodiment 8
This embodiment is a self-scanning light emitting device disclosed in Japanese Patent Application Laid-Open No. Hei 4-23367, and is one example to which the light emitting thyristor of the present invention can be applied.
[0067]
FIG. 17 shows a light emitting device of the example. In FIG. 17, the switch element array and the light emitting element array are separately illustrated in upper and lower parts.
[0068]
First, a switch element array having a shift register function will be described. S (-2) to S (2) are switch elements (thyristors having a PNPN structure). φ₁, Φ₂Is a transfer clock for driving the switch element array. And CL₁Is the transfer clock φ₁Is supplied to the clock line CL₂Is the transfer clock φ₂Is supplied to the clock line.
[0069]
Gate electrode G of each switch element S (-2) to S (2)- ₂ ~ G₂  Between the coupling diodes D-₂~ D₁  Are connected by Since such a diode-coupling method is employed, the switch element array has a two-phase transfer clock φ.₁  , Φ₂  Can perform an information transfer operation.
[0070]
Also, R_A1, R_A2    Are the anodes of the switch elements S (-2) to S (2) and the clock line CL, respectively.₁, CL₂The anode load resistance is connected to either one of these. This anode load resistance R_A1, R_A2    Is to limit the amount of current in the ON state of each of the switch elements S (-2) to S (2). The cathodes of the switch elements S (-2) to S (2) are grounded.
[0071]
Further, R_L1, R_L2Are the gates G of the switch elements S (-2) to S (2), respectively._-2~ G₂And power supply voltage V_GKIs the load resistance of the gate connecting to the DC power supply. This gate load resistance R_L1, R_L2Is the power supply voltage V_GKFrom each DC power supply to each gate G_-2~ G₂This limits the amount of current flowing through the device. And each gate G_-2, G₀, G₂Is a diode D_-2', D₀', D₂′ Is connected to the cathode.
[0072]
Next, the light emitting element array will be described. φ_RIs a clock that controls permission / prohibition of writing information to the light emitting elements (light emitting thyristors) L (-2), L (0), L (2) and resets the written state. And CL_RIs the clock φ_RIs a current supply line for supplying the current.
[0073]
Also R_A3Is the anode of each light emitting element L (-2), L (0), L (2) and the current supply line CL._RAnd the anode load resistance that connects This anode load resistance R_A3Limits the amount of current in the ON state of each light emitting element L (-2), L (0), L (2). The cathodes of the light emitting elements L (-2), L (0), L (2) are each grounded.
[0074]
Further R_L3Is the gate G of each light emitting element L (-2), L (0), L (2)._-2', G₀', G₂'And the power supply voltage V_GKAnd a gate load resistance connecting the This gate load resistance R_L3Is the power supply voltage V_GKFrom the DC power supply of each gate G_-2', G₀', G₂′ Is limited. And each gate G_-2', G₀', G₂'Are diodes D_-2', D₀', D₂′ Anode.
[0075]
That is, in FIG. 17, the gates of the switch elements S (−2), S (0), and S (2) are respectively connected to the diode D_-2', D₀', D₂′, The gates G of the light emitting elements L (−2), L (0), L (2)_-2', G₀', G₂′.
[0076]
Next, the operation of the switch element array will be described. Now, start pulse φ_SAssume that a high-level or low-level voltage is supplied to the anode (not shown) of the switch element S (-3). In this case, the high level voltage is equal to the power supply voltage V_GKTo the diffusion potential V_difIf the voltage is higher than the voltage obtained by adding, the switching element S (-3) is turned on. Then, the next supplied start pulse φ_SIs lower than the on-state maintaining voltage of the switch element S (-3), S (-3) is turned off.
[0077]
In the on state, the gate potential of the switch element S (-3) is substantially zero volt, and in the off state, the gate voltage is equal to the power supply voltage V._GKAnd the same voltage. When the gate potential of the switch element S (-3) becomes zero volt, the coupling diode D_-3(Not shown), the gate potential of the switch element S (-2) decreases. Then, the turn-on voltage of the switch element S (-2) also decreases. Therefore, the transfer clock φ₂Thereby, the switch element S (-2) can be set to the ON state.
[0078]
This ON state is φ₁, Φ₂Are sequentially transferred to the right in FIG. That is, the start pulse φ_S, The ON state is written in the switch element array, and the ON state is sequentially transferred to the right.
[0079]
However, when all the bits are in the ON state, it is impossible to transfer this ON state due to the operation principle of the switch element array. become. That is, the start pulse φ_SThe waveform of the transfer pulse φ₁, Φ₂, It is necessary to alternately send high level and low level.
[0080]
Now, assuming that there is valid information in the ON state and the OFF state of only the even bits, the ON state is set to 1 and the OFF state is set to 0._S1 or 0 is written by the transfer clock φ₁, Φ₂Thus, the 1,0 are transferred. Thus, a signal (information) of 1 or 0 is written to the switch element array.
[0081]
Next, the operation of the light emitting element L (-2) (L (0), L (2)) will be described. If L (-2) is 0, the clock φ_RIs zero volt, the light emitting element L (-2) is not turned on. That is, the light emitting element L (-2) is set in a write-protected state. Clock φ_RFrom the on-state maintaining voltage of the light emitting element L (-2) to V_GK+ V_dif, The light-emitting element L (−2) is set to a write-enabled state. And the gate G_-2', The light emitting element L (-2) can be set to the ON state.
[0082]
Now, writing of information from the switch element array to the light emitting element array will be described. The 1 or 0 signal is written in the switch element array as described above. When the last bit has been written, the transfer clock φ₁, Φ₂Are maintained at a low level and a high level, respectively. As a result, the information transfer operation is completed, and the information written in the switch element array is held (especially, the even-numbered bits are held).
[0083]
In the even-numbered bits of the switch element array, the gate potential of the switch element S in the on state is substantially zero volt, and the gate potential of the switch element S in the off state is V_difAbout twice or more. The gate potential of the switch element S in the off state is set to V when the nearest even bit located in the opposite direction to the transfer direction is in the on state._difAbout twice as much as V_difIs larger than about twice the voltage. Here, V_difIs the diffusion potential of the PN junction.
[0084]
The gate voltage of each of the switch elements S (-2), S (0), and S (2) is equal to the diode D_-2', D₀', D₂', The gate G of the corresponding light emitting element L (-2), L (0), L (2)_-2', G₀', G₂'. Therefore, the gate voltage of the light emitting elements L (-2), L (0), L (2) is V_difAnd V in the off state_difIs three times or more. In the case of the ON state, the turn-on voltage of the light emitting element is V_difAnd V in the off state_dif4 times of
[0085]
On the other hand, the clock φ_RIs set once to zero volts to eliminate the entire light emission (that is, reset), and then the high level potential V_HRUp to This voltage φ_HRAs
2V_dif<V_HR<4V_dif
, The light emitting element L corresponding to the switch element S in the on state is turned on, and the light emitting element L corresponding to the switch element S in the off state remains in the off state.
[0086]
Therefore, the information of 1, 0 written in the switch element array is written in the light emitting element array as it is.
[0087]
Thereafter, the voltage V_HRIs equal to or higher than the on-state maintaining voltage of the light emitting element and V_difIs reset to a value less than twice the voltage of As a result, the light emitting element L is not affected by the gate potential of the switch element S, and keeps the written information. Then, while the light emitting element array is in the information holding state, the next information is written to the switch element array in the same manner as described above.
[0088]
Eventually, the clock φ_RIs set to the low level voltage, and each light emitting element L is reset. After the reset, information is written to the light emitting element array again. As described above, a series of operations is repeatedly performed.
[0089]
Next, a case where the light emitting device shown in FIG. 17 is applied to a writing light source for an optical printer will be described.
[0090]
For example, assuming that the light emitting device has a light emitting element L of 2048 bits, the switching element S needs 4096 bits, which is twice that number. Since the current amount of the writing light source in the optical printer is about 5 mA, if the light emitting elements L of all the bits are in a light emitting state, a current of about 10 A flows.
[0091]
On the other hand, the current for information transfer from the switch element S is the gate load resistance R_L3Since it is experimentally known that the current is 0.5 mA when = 30 kΩ, it is about 1 A when the light emitting elements of all the bits emit light. The amount of current for information transfer is about 10% of 10 A required for optical printing, which is a value that does not cause any practical problem.
[0092]
At the stage when the information from the switch element S is moved to the light emitting element L, the clock φ₁, Φ₂Is once reduced to zero volts, the entire switch element array is turned off, and reset is performed. In the case where this method is used, the current value equivalently decreases when the time when the switch element S is turned on is considered. That is, it is equivalently reduced to about 0.5A compared to the above-described 1A.
[0093]
For the 2048 bits of the light emitting element L, the start pulse φ_SWhen only one data input end (not shown) is supplied, the information transfer rate needs to be considerably high. In this regard, by providing a plurality of data input terminals, the transfer rate of information can be reduced. For example, a chip of the light emitting element L is usually formed with 64 bits or 128 bits as one unit, and information may be input for each chip.
[0094]
If data input is performed in parallel every 128 bits, there will be 20 data input terminals for 2048 bits. For this reason, the information transfer rate may be 1/20. Therefore, the light-emitting device can perform a marginal operation.
[0095]
Note that, in order to prevent variations in the amount of output light of the light emitting element L, the anode load resistance R_A3Can be finely adjusted with a laser or the like. This makes it possible to obtain a light emitting device having no variation in output light.
[0096]
In FIG. 17, the coupling diode D connected to the right side of the even-numbered bit in the switch element array is shown._-2, D₀And the coupling diode D connected to the right of the odd bit_-1, D₁Characteristics are different. Therefore, it is important to separately optimize the operating current and the like for the even-numbered bits and the odd-numbered bits. For this, R_L2<R_L1, R_A1<R_A2Is preferable, and in this case, the light emitting device can perform a more stable and high-speed operation.
[0097]
Further, in FIG. 17, a configuration called a diode coupling system is adopted for the switch element array. However, the coupling system is not limited to this, and may be a resistance coupling system.
[0098]
In this embodiment, when the switch element array is a diode-coupled type, the ladder structure 10 shown in FIG. 5 or the ladder structure 20 shown in FIG. 6 may be added to the last-stage switch element. When the switch element array is of the resistance coupling type, the ladder structure 30 shown in FIG. 11A or the equivalent resistance R shown in FIG._EMay be added.
[0099]
【The invention's effect】
According to the present invention, since the load resistance compensating circuit is provided at the end of the light emitting element array or the switch element array, the switching speed to the ON state becomes substantially constant, and uniform switching is performed through all the light emitting elements or all the switching elements. Speed can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a self-scanning light emitting device.
FIG. 2 is a diagram illustrating a gate potential gradient of the light emitting device of FIG.
3 is a diagram illustrating a gate potential gradient near the end of the light emitting device of FIG.
FIG. 4 is a graph showing a change in load resistance near a termination.
FIG. 5 is a circuit diagram of the first embodiment.
FIG. 6 is a circuit diagram of a second embodiment.
FIG. 7 is a graph showing a change in load resistance near a termination in Example 2.
FIG. 8 is a sectional view showing the structure of a light emitting thyristor and a diode in the last stage of Example 2.
FIG. 9 is a circuit diagram of a third embodiment.
FIG. 10 is a circuit diagram of a light emitting device according to a fourth embodiment to which the present invention can be applied.
FIG. 11 is a diagram illustrating a load resistance compensation circuit added to the light emitting device according to the fourth embodiment.
FIG. 12 is a circuit diagram of a light emitting device according to a fifth embodiment to which the present invention can be applied.
FIG. 13 is a circuit diagram of a light emitting device according to a sixth embodiment to which the present invention can be applied.
FIG. 14 is a block diagram of a light emitting device according to a seventh embodiment to which the present invention can be applied.
15 is an equivalent circuit diagram of the light emitting device of FIG.
16 is a pulse timing chart showing a driving method of the light emitting device of FIG.
FIG. 17 is a circuit diagram of a light emitting device according to an eighth embodiment to which the present invention can be applied.
[Explanation of symbols]
T light emitting thyristor
D coupling diode
R_L  Gate load resistance
R_I  Coupling resistor
Tr transistor
10 Ladder structure load resistance compensation circuit
20 Load resistance compensation circuit with terminating resistor
30 Load resistance compensation circuit with ladder structure termination resistor

Claims (12)

A plurality of light emitting elements having threshold voltage or threshold current control electrodes are arranged, and the control electrode of each light emitting element is electrically unidirectional to the control electrode of at least one light emitting element located in the vicinity thereof. A self-scanning light emitting device formed by connecting a power line to the control electrode of each light emitting element via a load resistor, and connecting a clock pulse line to each light emitting element,
A self-scanning light-emitting device, further comprising a load resistance compensating circuit having a ladder structure including the load resistance and the electric element, provided after the last electric element. A plurality of light emitting elements having threshold voltage or threshold current control electrodes are arranged, and the control electrode of each light emitting element is electrically unidirectional to the control electrode of at least one light emitting element located in the vicinity thereof. A self-scanning light emitting device formed by connecting a power line to the control electrode of each light emitting element via a load resistor, and connecting a clock pulse line to each light emitting element,
A self-scanning light-emitting device, further comprising a load resistance compensation circuit having a ladder structure in which one or more resistors are connected in parallel after the last electric element. A plurality of light emitting elements having threshold voltage or threshold current control electrodes are arranged, and the control electrode of each light emitting element is electrically unidirectional to the control electrode of at least one light emitting element located in the vicinity thereof. A self-scanning light emitting device formed by connecting a power line to the control electrode of each light emitting element via a load resistor, and connecting a clock pulse line to each light emitting element,
A self-scanning light-emitting device, further comprising a load resistance compensation circuit having a ladder structure in which one or more resistors are connected in parallel after the last light-emitting element. A plurality of light-emitting elements having threshold voltage or threshold current control electrodes are arranged, and the control electrode of each light-emitting element is connected to a control electrode of at least one light-emitting element located in the vicinity thereof via a connection resistor. And a self-scanning light emitting device formed by connecting a power supply line to the control electrode of each light emitting element via a load resistor, and connecting a clock pulse line to each light emitting element.
A self-scanning light-emitting device, further comprising a load resistance compensating circuit having a ladder structure including the load resistance and the connection resistance at a stage subsequent to the last connection resistance. The self-scanning light emitting device according to claim 4, wherein the ladder structure including the load resistance and the connection resistance is replaced with one equivalent resistance. A plurality of switch elements having threshold voltage or threshold current control electrodes for switching operation are arranged, and the control electrode of each switch element is electrically connected to the control electrode of at least one switch element located near the switch element. A switching element array formed by connecting a power supply line to a control electrode of each switch element via a load resistor, and connecting a clock pulse line to each switch element, while connecting the control elements of the switch elements via a unidirectional electric element. When,
A light-emitting element array in which a plurality of light-emitting elements each having a threshold voltage or a threshold current control electrode for light-emitting operation are arranged,
In a self-scanning light emitting device in which each control electrode of the light emitting element array is electrically connected to a control electrode of the switch element and a line for applying a current for light emission to each light emitting element is provided.
A self-scanning light-emitting device, further comprising a load resistance compensating circuit having a ladder structure including the load resistance and the electric element, provided after the last electric element. A plurality of switch elements having threshold voltage or threshold current control electrodes for switching operation are arranged, and the control electrode of each switch element is electrically connected to the control electrode of at least one switch element located near the switch element. A switching element array formed by connecting a power supply line to a control electrode of each switch element via a load resistor, and connecting a clock pulse line to each switch element, while connecting the control elements of the switch elements via a unidirectional electric element. When,
A light-emitting element array in which a plurality of light-emitting elements each having a threshold voltage or a threshold current control electrode for light-emitting operation are arranged,
In a self-scanning light emitting device in which each control electrode of the light emitting element array is electrically connected to a control electrode of the switch element and a line for applying a current for light emission to each light emitting element is provided.
A self-scanning light-emitting device, further comprising a load resistance compensation circuit having a ladder structure in which one or more resistors are connected in parallel after the last electric element. A plurality of switch elements having threshold voltage or threshold current control electrodes for switching operation are arranged, and the control electrode of each switch element is electrically connected to the control electrode of at least one switch element located near the switch element. A switching element array formed by connecting a power supply line to a control electrode of each switch element via a load resistor, and connecting a clock pulse line to each switch element, while connecting the control elements of the switch elements via a unidirectional electric element. When,
A light-emitting element array in which a plurality of light-emitting elements each having a threshold voltage or a threshold current control electrode for light-emitting operation are arranged,
In a self-scanning light emitting device in which each control electrode of the light emitting element array is electrically connected to a control electrode of the switch element and a line for applying a current for light emission to each light emitting element is provided.
A self-scanning light-emitting device, further comprising a load resistance compensation circuit having a ladder structure in which one or more resistors are connected in parallel after the last light-emitting element. A plurality of switch elements having threshold voltage or threshold current control electrodes for switching operation are arranged, and the control electrodes of each switch element are connected to control electrodes of at least one switch element located near the switch elements. A switching element array formed by connecting via a resistor, connecting a power supply line to a control electrode of each switch element via a load resistor, and connecting a clock pulse line to each switch element;
A light-emitting element array in which a plurality of light-emitting elements each having a threshold voltage or a threshold current control electrode for light-emitting operation are arranged,
In a self-scanning light emitting device in which each control electrode of the light emitting element array is electrically connected to a control electrode of the switch element and a line for applying a current for light emission to each light emitting element is provided.
A self-scanning light-emitting device, further comprising a load resistance compensating circuit having a ladder structure including the load resistance and the connection resistance at a stage subsequent to the last connection resistance. 10. The self-scanning light emitting device according to claim 9, wherein the ladder structure including the load resistance and the connection resistance is replaced with one equivalent resistance. A writing head for an optical printer, comprising the self-scanning light emitting device according to claim 1. An optical printer comprising the write head of the optical printer according to claim 11.

Images