JP4284983B2 - Self-scanning light emitting element array chip and optical writing head - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a self-scanning light emitting element array chip and an optical writing head.
[0002]
[Prior art]
A light emitting element array in which a large number of light emitting elements are integrated on the same substrate is used as an optical writing head such as an optical printer head in combination with a driving IC. The inventors have paid attention to a three-terminal light-emitting thyristor having a PNPN structure as a constituent element of the light-emitting element array, and have already filed a patent application (see Patent Documents 1, 2, 3, and 4) that self-scanning of the light-emitting point can be realized. It has been shown that it is easy to mount as an optical printer head, that the light emitting element pitch can be made fine, and that a compact self-scanning light emitting element array (SLED) can be produced.
[0003]
Furthermore, the present inventors have proposed a self-scanning light-emitting element array having a structure separated from a light-emitting element (light-emitting thyristor) array, which is a light-emitting part, using a switch element (light-emitting thyristor) array as a shift part (Patent Document 5). reference).
[0004]
[Patent Document 1]
JP-A-1-238996
[Patent Document 2]
Japanese Patent Laid-Open No. 2-14584
[Patent Document 3]
Japanese Patent Laid-Open No. 2-92650
[Patent Document 4]
JP-A-2-92651
[Patent Document 5]
JP-A-2-263668
[0005]
FIG. 1 shows an equivalent circuit diagram of a diode-coupled self-scanning light emitting element array chip in which the shift unit and the light emitting unit are separated. This self-scanning light-emitting element array includes a thyristor T₁ , T₂ , T_Three ,... And a thyristor L₁ , L₂ , L_Three ,... Are included. The configuration of the shift unit uses a diode connection. That is, between the gates of the thyristors, the diode D₁ , D₂ , ... are combined. V_GAIs a power supply, and the load resistance R from the power supply wiring 15_L And is connected to the gate of each shift unit thyristor. The gate of the shift unit thyristor is also connected to the gate of the light emitting unit thyristor. Thyristor T₁ The gate of the start pulse φ_S Connected to the terminal. The cathode of the shift unit thyristor is connected to clock pulse φ1 and φ2 terminals via transfer clock pulse φ1 and φ2 wirings 16 and 17 alternately. The resistors R1 and R2 are current limiting resistors inserted in the wirings 16 and 17, respectively. In addition, the cathode of the light emitting unit thyristor passes through the write signal wiring 18 and the write signal φ_I Connected to the terminal. Resistance R_I These are current limiting resistors inserted in the wiring 18. Start pulse φ_S Terminal, clock pulse φ1, φ2 terminal, write signal φ_IThe terminal is connected to a driver (not shown).
[0006]
In the self-scanning light emitting element array chip having such a structure, the ON state of the shift unit thyristor is transferred, and the light emitting unit thyristor is sequentially turned ON in response to this. That is, φ_I This is a self-scanning light emitting element array chip that can light only one light emitting section thyristor (light emitting point) per wiring.
[0007]
A plurality of such self-scanning light emitting element array chips are arranged and combined with a lens array to constitute an optical writing head. Such an optical writing head is disposed, for example, near the photosensitive drum of an optical printer.
[0008]
In the case of the optical writing head configured to place the drive substrate outside the head, assuming that 60 chips of FIG. 1 having 128 light emitting points are used for the A3 size head, a total of 60 (φ_I ) + 5 (φ1, φ2, φ_S, Φ_GA, Substrate potential terminal) is required. If the number of lead-out wires increases, the cable becomes thicker and difficult to handle, and the connector becomes larger, making it difficult to reduce the size. Furthermore, when high light output is required, φ per chip_I Although the number of wirings may be increased, the number of extraction wirings is further increased.
[0009]
On the other hand, the inventors_I An optical writing head using a self-scanning light emitting element array chip capable of lighting a plurality of light emitting points per wiring is also proposed. According to this optical writing head, the number of wirings is (number of chips + 5) regardless of the number of light emitting points per chip. However, one φ per chip_I Since wiring is necessary, the number of wirings could not be reduced. In addition, although a plurality of light emitting points can be turned on, for example, if 128 light emitting points on one chip are turned on simultaneously and a current of 10 mA flows to each light emitting point, a current of 1 A or more is φ_I It will flow to the wiring and φ_I Wiring may overheat.
[0010]
An object of the present invention is to provide an optical writing head that can operate with a small number of external wirings.
[0011]
Another object of the present invention is to provide a self-scanning light-emitting element array chip that is used in such an optical writing head and has a structure in which a plurality of lights can be turned on and data writing can be interrupted.
[0012]
Still another object of the present invention is to provide an optical printer using such an optical writing head.
[0013]
Still another object of the present invention is to provide a self-scanning light-emitting element array chip and an optical writing head driving method.
[0014]
[Means for Solving the Problems]
  In a typical self-scanning light-emitting element array chip of the present invention, a plurality of first three-terminal light-emitting thyristors are arranged one-dimensionally, the gates of adjacent first thyristors are connected to each other by a diode, and each gate is connected to each other. Connected to the power supply wiring through the gate load resistor, the anode of the odd first thyristorOrThe cathode is connected to the first clock pulse wiring, and the even-numbered first thyristor anodeOrA shift unit in which the cathode is connected to the second clock pulse wiring and a plurality of second three-terminal light-emitting thyristors are arranged one-dimensionally, and are divided into blocks for each predetermined number of second thyristors. The gates of the thyristors are set to the gates of the corresponding first thyristors of the shift unit, which are blocked for each predetermined number of first thyristors, leaving two odd and even first thyristors in between. Connected through a diode, the anode of each second thyristorOrCathode to anodeOrA light emitting section connected to a write signal wiring via a cathode load resistor, and connecting the write signal wiring to a reset signal terminal via a diode.
[0015]
  In this self-scanning light-emitting element array chip driving method, the first and second clock pulses are applied to the first and second clock pulse wirings to change the ON state of the first thyristor of the shift unit. Sequentially transferring and when the first thyristor of the shift unit is in an on state,Write signal wiringBy applying a voltage to the second thyristor corresponding to the first thyristor in the on state, and an odd-numbered thyristor of the two first thyristors in the shift unit When the on-state is turned on, a voltage is applied to the write signal wiring of the light-emitting unit to turn on the second thyristor in the on-state, and the reset signal terminal is set to 0 volts so that the light emission Turning off the second thyristor that is lit.
[0016]
A typical optical writing head of the present invention has the above-described N (N is an integer of 2 or more) self-scanning light emitting element array chips as one group, and M group (M is an integer of 2 or more) in one dimension. An array of self-scanning light emitting element arrays, N first clock pulse common lines to which the first clock pulse lines of the N chips are sequentially connected, and second clock pulses of all the chips One second clock pulse common wiring to which wiring is connected, one power common wiring to which the power wiring of all the chips is connected, and one reset signal terminal of all the chips are connected Reset signal common wires and M write signal common wires to which the write signal wires of the chips of each group are connected.
[0017]
The method of driving the optical writing head includes the steps of turning on the first thyristor of the same block of the same chip of each group and the M thyristors when the first thyristor is on. By applying a voltage to the write signal common line, the step of turning on the second thyristor corresponding to the first thyristor in the on state and the above steps are performed for all the same chips. After that, the step of turning on the second thyristor in the on state by applying a voltage to the M write signal common wires and turning on the reset signal common wire to 0 volts make the lights on. A step of turning off the second thyristor, and a step of repeating the above steps for the first thyristors of all the same blocks. Including the.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the embodiment of the present invention will be described in the case of using a three-terminal light-emitting thyristor with the anode as a common potential, but the three-terminal light-emitting thyristor with the cathode as a common potential is also used by changing the polarity of the circuit. be able to.
[0019]
[Example 1]
An equivalent circuit diagram of a self-scanning light-emitting element array chip used in the optical writing head is shown in FIG. The circuit is roughly divided into a shift unit 1 and a light emitting unit 2. In the figure, the circuit configuration of the top portion of the chip is shown, in which the shift unit 1 shows eight three-terminal light-emitting thyristors, and the light-emitting unit 2 shows six three-terminal light-emitting thyristors.
[0020]
In the shift unit 1, the cathodes of the odd-numbered thyristors are connected to the φ1 wiring 16, and the cathodes of the even-numbered thyristors are connected to the φ2 wiring 17. The gate of each thyristor is connected to the gate of the thyristor on the right side through the coupling diode 43, and is connected to the power supply wiring 15 through the gate load resistor 42. Further, the gate of the 6n + 1, 6n + 2, 6n + 3, 6n + 4 (n is an integer of 0 or more) th thyristor is connected to the gate of the thyristor 45 of the light emitting unit 2 through the coupling diode 44. On the other hand, the 6n + 5 and 6n + 6th shift unit thyristors have no corresponding light emitting unit thyristors to be connected. By not providing the corresponding light emitting unit thyristor, data writing can be interrupted as will be described later.
[0021]
In the light emitting unit 2, the cathode of the thyristor 45 is φ through a cathode load resistor 46._I Connected to the wiring 18.
[0022]
The φ1 wiring 16 and the φ2 wiring 17 are connected to the φ1 terminal 11 and the φ2 terminal 12 through the φ1 resistor 21 and the φ2 resistor 22. The gate of the first shift unit thyristor 41 is connected to the φ2 wiring 17 through the start diode 31. By providing such a start diode, in the conventional self-scanning light-emitting element array chip shown in FIG._s Terminals can be omitted.
[0023]
Furthermore, φ_I The wiring 18 is connected to a reset signal φ via a diode 30._R It is connected to the terminal 14. When the light emitting unit thyristor 45 is on, the reset signal φ_R Is set to 0 V, all the light-emitting thyristors that are lit are turned off.
[0024]
In the figure, 10 is a power supply terminal, 13 is φ_I Reference numeral 20 denotes a terminal for applying a potential (GND) to the common back electrode of the thyristor.
[0025]
A schematic diagram of the chip structure of FIG. 2 is shown in FIGS. FIG. 4 shows an enlarged plan view and an enlarged sectional view of a portion surrounded by a dotted line in FIG. FIG. 4B is a cross-sectional view taken along line XX in FIG. In the figure, 76 is a p-type GaAs substrate, 72 is an n-type cathode layer, 73 is a p-type gate layer, 74 is an n-type gate layer, and 75 is a p-type anode layer. Reference numeral 77 denotes a cathode electrode, 78 denotes a gate electrode, and 79 denotes a back surface common electrode. In addition, the same reference number is attached | subjected and shown to the component same as FIG.
[0026]
In this structure, the diodes 43 and 44 use a pn junction between the cathode layer 72 and the gate p layer 73. The resistors 42 and 46 use the cathode layer 72. Alternatively, a metal Schottky contact may be formed on the layer and used as a diode. The metal can be selected from Al, Au, Cr, Ni, W, Pt, Pd, Pb, NiCr, and the like. In this case, the forward voltage is smaller than that of a pn junction diode and is about 0.8 V. Therefore, the forward voltage can be used for various voltages by combining with a pn junction diode.
[0027]
The operation of the self-scanning light emitting element array chip of FIG. 2 will be described. First, the back surface common electrode terminal 20 is set to 0V, and the power supply terminal 10 is set to −3.3V. Φ_R The terminal 14 is also set to −3.3V. The operation of the shift unit 1 is a normal operation of the self-scanning light emitting element array, and the ON state is transferred by the clock pulses φ1 and φ2. When the nth shift unit thyristor 41 is in the on state, its gate voltage is approximately 0V. The forward voltage of the coupling diodes 43 and 44 is 1.2V, and the ON condition of the light emitting unit thyristor is
V_K <V_G -1.2 (V)
However, V_K Is the cathode voltage, V_G Is the gate voltage
Then, the ON voltage of the nth light emitting unit thyristor 45 is −2.4V. Note that the ON voltage of the (n + 1) th light emitting unit thyristor is further decreased by 1.2V to −3.6V. The on-voltage of the other light emitting unit thyristors is −3.3−1.2 = −4.5V.
[0028]
When the nth shift unit thyristor 41 is in the on state and all the light emitting unit thyristors 45 are not on, φ_I The potential of the wiring 18 is −2.4V. φ_I The wiring 18 is connected to the reset terminal (−3.3 V) via the diode 30, but the diode 30 is in the OFF state, so that φ_I The wiring 18 is floating.
[0029]
Now, φ_I When the terminal 13 is set to −3.3V, the nth light emitting unit thyristor is turned on. However, the (n + 1) th light-emitting thyristor cannot be turned on at −3.3V. Therefore, only the light emitting unit thyristor of the block 40 in which the shift unit thyristor is on can be selectively turned on. After the nth light emitting unit thyristor is turned on, φ_I When the terminal 13 is set to high impedance, the diode 30 is turned on and power is supplied from the reset terminal 14. Current I at this time_S Is the resistance value of the cathode load resistor 46 R_I Then,
I_S = (3.3-1.2-1.2) / R_I = 0.9 / R_I
It becomes. Since the diode 30 is on, φ_I The wiring 18 is fixed at −3.3 + 1.2 = −2.1V.
[0030]
On the other hand, when the nth shift unit thyristor is on, φ_I When the terminal 13 is set to high impedance, the nth light emitting unit thyristor is not turned on.
[0031]
Subsequently, in a state where the m-th shift unit thyristor (m is an integer of m> n) is turned on, φ_I If the terminal is -3.3V, the mth light emitting unit thyristor is also turned on. On the other hand, the n-th light emitting unit thyristor that was previously turned on also maintains the on state. In this way, while sequentially transferring the ON state of the shift unit thyristor, φ_I A plurality of light emitting unit thyristors can be turned on by applying a voltage (−3.3 V) to the wiring.
[0032]
In FIG. 2, four light emitting unit thyristors constituting one block are shown as an example. The first to fourth thyristors 45 constitute the first block. For this one block, after turning on the desired light emitting unit thyristor as described above, the on state of the shift unit thyristor is transferred to the fifth thyristor not connected to the light emitting unit thyristor, and φ_I By setting the wiring to −3.3 V, the light emitting unit thyristor that has been turned on shines brightly, that is, lights up. Thereby, the photosensitive drum is exposed for a predetermined time.
[0033]
Current I flowing in the light-emitting unit thyristor when lit_S Is
I_S = (3.3-1.2) / R_I = 2.1 / R_I
It is. When the exposure time is over, φ_I Terminal 13 is set to high impedance and φ_R By setting the terminal 14 to 0V (more precisely, -1.2V or more), all the light emitting unit thyristors that have been lit can be turned off, so that the on state of the thyristor in the shift unit is sixth and seventh. In the same manner, the second and subsequent blocks are written.
[0034]
FIG. 5 shows a circuit example of an optical writing head using this self-scanning light emitting element array chip. Here, four chips are set as one set, and two sets are shown. FIG. 5A shows an arrangement of terminals (bonding pads) in one chip, and FIG. 5B shows an arrangement of eight chips. In FIG. 5A, reference numeral 60 denotes a light emission point sequence, and the other reference numbers are the same as the reference numbers of the components in FIG. Circle numbers (1) to (8) in FIG. 5 (B) indicate chip numbers.
[0035]
The power supply terminals 10 of all the chips are connected to the power supply wiring 110, the φ2 terminal 12 of all the chips is connected to the φ2 wiring 112, the back surface common electrode terminal 20 of all the chips is connected to the common wiring 120, and the φ of all the chips are connected._R The terminals 14 are connected to the reset lines 114, respectively. The φ1 terminal 11 of the 4m + k (m is 0 or 1, k = 1, 2, 3, 4) -th chip is connected to 111-k among the φ1 wirings 111-1 to 111-4. Also, φ of 4m + kth chip_I The terminal has two φ_I Of the wirings 113-1 and 113-2, φ_I It is connected to the wiring 113- (m + 1).
[0036]
FIG. 6 and FIG. 7 show driving waveforms of the circuit of FIG. 6 shows the first half of the drive waveform, and FIG. 7 shows the second half of the drive waveform. In the figure, in the φ1-1, φ1-2, φ1-3, φ1-4 and φ2 waveforms, the round numbers and numbers shown at the L level are the chip number and the number of the shift unit thyristor which is turned on. is there. For example, (1) (5) 1 in the upper left indicates that the first shift unit thyristor of the chips (1) and (5) is in the ON state. Φ_I -1, φ_I For the -2 waveform, the H level is high impedance and the L level is -3.3V.
[0037]
First, when the φ2 waveform is at the H level and the φ1-1 waveform is at the L level, the first shift unit thyristors of the chips (1) and (5) are turned on. After this, φ_I -1, φ_I -2 waveform writes data to the first light emitting unit thyristor of the chip (1), (5). That is, if it is desired to emit the light emitting unit thyristor corresponding to the thyristor in which the shift unit is turned on, φ_I -1, φ_I -2 If the waveform is set to L level, the light emitting unit thyristor is turned on, and it is not desired to emit light, φ_I -1, φ_I -2 The waveform is set to high impedance and the light emitting unit thyristor is turned off. When data writing of the first to fourth light emitting unit thyristors of the chips (1) and (5) is completed, the fifth shift unit thyristor is turned on, and then the first to fourth of the chips (2) and (6) are turned on. Write to the light emitting thyristor. During this time, every time the φ2 waveform becomes L level, the sixth shift unit thyristor of the chips (1) and (5) is also turned on, but in the chips (1) and (5), the φ1-1 waveform remains at the L level. Therefore, the transfer of the shift part does not proceed. That is, the data writing is interrupted in the chips (1) and (5).
[0038]
Similarly, the writing of the first to fourth light emitting unit thyristors of the chips (3) and (7) and the writing of the first to fourth light emitting unit thyristors of the chips (4) and (8) are performed. Then, during the exposure time, φ_I -1, φ_I -2 waveform becomes L level, and the light emitting unit thyristor in the on state is turned on. When the exposure time is over, φ_I -1, φ_I -2 Set the waveform to high impedance,_R The waveform is once set to 0 V, and all the light emitting unit thyristors that are lit are turned off. Thereafter, the same processing is performed for the next block (7th to 10th light emitting thyristors).
[0039]
In the present embodiment, the write head having a 4-chip 2-block configuration in which four light emitting unit thyristors and six shift unit thyristors are configured as one block has been described. However, the number of light emitting unit thyristors may be selected in any way. However, if the number of thyristors in one block increases, the number of light-emitting thyristors that can emit light simultaneously increases, and there is a possibility of overheating.
[0040]
Also, the number of chips in one block may be selected in any way. However, if the number of chips is increased too much, it takes time for writing, and the time for lighting is reduced. Further, the product NM of the number of chips N and the number of blocks M in one block is the total number of chips, but the number of wirings is N + M + 4 (φ2, reset, power supply, back surface common electrode). If selected, the number of wires can be reduced. For example, when 60 chips are used, if N = 6 and M = 10 are selected, 6 + 10 + 4 = 20 wirings are sufficient.
[0041]
Although the shift unit has been described with respect to the diode coupling method controlled by the two-phase clock pulses φ1 and φ2, a clock pulse of three or more phases may be used, or a method other than diode coupling such as resistance coupling may be used. Good. Further, the number of thyristors not connected to the light emitting unit may be any number as long as it is two or more. Further, when the head is configured, it is advantageous in terms of the configuration that the φ2 line is common, but it may be divided into a plurality of lines. φ_I Line and φ_R The terminal is connected via a diode in the chip._R Terminals may be omitted, or simply φ_I The line may be at three voltage levels: light emission, writing (eg -3.3V), holding (eg -2.1V) and extinguishing (eg 0V).
[0042]
[Example 2]
In the first embodiment, the power supply voltage is −3.3V. FIG. 8 shows an equivalent circuit diagram of the self-scanning light emitting element array chip when the power supply voltage is −5.0V. The number of coupling diodes 44 in the light emitting portion, which was one in the chip of FIG. 2, is three. As a result, the on-voltage of the nth light emitting unit thyristor when the nth shift unit thyristor is on is −4.8V. On the other hand, the ON voltage of the (n + 1) th light emitting unit thyristor is −6.0V.
[0043]
Other structures are the same as those of the chip of FIG. 2, and the same components are denoted by the same reference numerals. Since the operation is the same as that of the first embodiment, the description is not repeated.
[0044]
[Example 3]
In the first embodiment, when data is written, φ_I When terminal 13 is at H level (high impedance), φ_I The voltage of the wiring 18 is -2.1 V, and φ is exposed during exposure._I When the terminal 13 is at L level, the voltage is −3.3V. The current flowing through each light emitting unit thyristor is 0.9 / R, respectively._I And 2.1 / R_I It ’s only about twice as much. For this reason, unless driving is performed so that the writing time is sufficiently small with respect to the exposure time, the chips (1) and (5) are lit first at the time of writing, and light emission is continued during the writing of other chips thereafter. To do. For this reason, there is a problem that a difference in exposure amount occurs for each chip. Therefore, in this embodiment, the light emitting unit thyristor shown in FIG. 2 is used for data latch, and a light emitting unit thyristor is provided separately.
[0045]
FIG. 9 shows an equivalent circuit diagram of the self-scanning light emitting element array chip having such a structure. The data latch unit 3 has the same configuration as the light emitting unit shown in FIG. 2, 47 is a thyristor, and 48 is a cathode load resistance. Each thyristor 45 of the light emitting unit 2 is connected to the light emitting signal wiring 26 via the cathode load resistor 46. Reference numeral 25 denotes a light emission signal terminal. A light emission signal φ for lighting the light emitting unit thyristor 45 is connected to this terminal._E Is supplied. Other structures are the same as those in FIG. 2, and the same reference numerals are given to the same components as those in FIG.
[0046]
FIG. 10 is a plan view of the chip. The shift unit 1, the data latch unit 3, and the light emitting unit 2 are surrounded by a dotted line. In this structure, the light emitting unit thyristor 45 and the latch unit thyristor 47 are connected by the same gate layer, but may be different islands as long as they are electrically connected.
[0047]
The thyristor 47 of the latch unit 3 covers the light emitting region with a cathode electrode so that light does not leak as much as possible. The value of the cathode load resistor 48 is selected to be smaller than the resistance value through which the holding current of the thyristor 47 can flow. Further, the value of the cathode load resistance 46 of the light emitting unit 2 is determined from the necessary light emission amount.
[0048]
11A and 11B are circuit diagrams of an optical writing head using the self-scanning light emitting element array chip. The drive waveforms of the circuit of FIG. 11 are shown in FIGS.
[0049]
The difference from the circuit diagrams of FIGS. 5A and 5B is that the chip has a light emission signal terminal 25, and the light emission signal terminal of each chip is connected to one light emission signal wiring 125. .
[0050]
The driving waveforms in FIGS. 12 and 13 differ from the driving waveforms in FIGS. 6 and 7 in that the emission signal waveform φ_E Is added.
[0051]
In the self-scanning light-emitting element array chip having such a structure, data is latched in the latch unit at the write time, that is, the thyristor 47 is turned on or off, and the light emission signal waveform φ is exposed at the exposure time._E Is turned to L level, and the light emitting unit thyristor 45 corresponding to the latch unit thyristor 47 in the on state is turned on.
[0052]
For example, in the case of “1200 dpi light emission points, 8 light emission points as one block, and a chip including 32 blocks (8 × 32 = 256 light emission points)” with 4 blocks as 1 block, the A4 horizontal size is 60 sheets / When printing in minutes, the time given for one line exposure is 102 μs. Since this is divided into 32 blocks, it becomes 3.2 μs per block. During this time, 8 shift bits × 4 chips × 50 ns (transfer rate) = 1.92 μs, and the remaining 1.28 μs is used for lighting. Now, assuming that the output of one light emitting point is 50 μW, the exposure energy density is 0.14 J / m.² It becomes. When the transmittance of the lens is 4%, 5.6 mJ / m² Thus, the energy is sufficient to expose a standard photoelectric conversion drum.
[0053]
In this embodiment, the gates of the light emitting unit thyristor 45 and the latch unit thyristor 47 are in a floating state when the diode 30 is off and the potential is not determined. However, since there is no problem in operation, the gate is not pulled down by a resistor. If further high-speed operation is required, the gates of the thyristors 45 and 47 may be connected to the power supply wiring 15 through an appropriate pull-down resistor.
[0054]
[Example 4]
In Example 3, the light emission signal waveform φ is obtained after writing for four chips is completed._E Since L is at the L level (exposure time), the lighting time is short. For example, in the above-described example, data writing is performed up to 1.92 μs out of the time 3.2 μs given to one line, and the lighting time is only 1.28 μs. In order to enable higher-speed printing, it is desirable that light can be emitted during data writing. Therefore, as shown in FIG. 14, the number of light emission signal wirings 125 is four corresponding to the φ1 wirings 111-1 to 111-4. Reference numerals 125-1 to 125-4 denote four light emission signal wirings. As a result, it can be turned on except for the time written in itself.
[0055]
15 and 16 show drive waveforms. For example, after writing data to the latch portions of the chips (1) and (5), the light emission signal waveform φ_E By setting −1 to L level, the light emitting unit thyristor corresponding to the latch unit thyristor in the on state is turned on.
[0056]
Reset signal φ_R In each chip, the continuous lighting for exposure ends, and before data is newly written, it is raised to H level once to erase the data in the latch portion. By using this waveform, the time during which lighting was not possible was changed from 1.92 μs to ¼, 0.48 μs, and the time during which lighting was possible was doubled.
[0057]
[Example 5]
  In the configuration shown in the fourth embodiment, it cannot be turned on while writing to the thyristor of the latch unit. Therefore, in order to shorten the writing time, as shown in FIG.Write signal wiringAre doubled to 18-1, 18-2, and theseWrite signal wiringEach of these was connected to the reset signal terminal 14 via a diode 30. Reference numerals 13-1 and 13-2 denote data write terminals. As can be seen from the figure, the cathodes of the latch unit thyristors 47 are connected to the data write wirings 18-1 and 18-2 in turn, and the gates of the one thyristor 41 of the shift unit corresponding to every two units. Connected to the gate.
[0058]
18A and 18B are circuit diagrams of an optical writing head using the self-scanning light emitting element array chip. Drive waveforms of the circuit of FIG. 18 are shown in FIGS.
[0059]
  As shown in FIG. 18, each chip has twoWrite signal wiringAs shown in FIGS. 19 and 20, two latch unit thyristors can be turned on simultaneously.
[0060]
With such a configuration, the writing speed is doubled. It is also possible for triple or more.
[0061]
[Example 6]
Next, an optical printer using the optical writing head described above will be described. FIG. 21 shows a configuration of an optical printer including such an optical printer head 140. A photoconductive material (photosensitive member) such as amorphous Si is formed on the surface of the cylindrical photosensitive drum 142. This drum rotates at the speed of printing. The surface of the photosensitive drum of the rotating drum is uniformly charged by the charger 144. Then, the optical printer head 140 irradiates the photosensitive member with light of a dot image to be printed, and neutralizes the charging where the light hits. Subsequently, the developing device 148 applies toner to the photoconductor in accordance with the charged state on the photoconductor. Then, the toner is transferred onto the paper 154 sent from the cassette 152 by the transfer device 150. The paper is heated and fixed by the fixing device 146 and sent to the stacker 158. On the other hand, the drum that has been transferred is neutralized by the erasing lamp 160 over the entire surface, and the remaining toner is removed by the cleaner 62.
[0062]
【The invention's effect】
According to the present invention, it is possible to realize an optical writing head that can operate with a small number of external wirings. Further, according to the optical writing head of the present invention, the number of simultaneous lighting increases, so that high-speed printing is possible.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a diode-coupled self-scanning light emitting element array chip in which a shift unit and a light emitting unit are separated.
FIG. 2 is an equivalent circuit diagram of a self-scanning light emitting element array chip used for an optical writing head.
FIG. 3 is a plan view of the chip structure of FIG. 2;
4 is a partially enlarged plan view of the chip structure of FIG. 2 and a cross-sectional view thereof.
FIG. 5 is a circuit example of an optical writing head using the self-scanning light emitting element array chip of FIG.
6 is a diagram showing drive waveforms of the circuit of FIG.
7 is a diagram showing drive waveforms of the circuit of FIG.
FIG. 8 is an equivalent circuit diagram of the self-scanning light-emitting element array chip when the power supply voltage is −5.0V.
FIG. 9 is an equivalent circuit diagram of a self-scanning light emitting element array chip having another structure.
10 is a plan view of the chip structure of FIG. 9. FIG.
11 is a circuit diagram of an optical writing head using the self-scanning light emitting element array chip of FIG. 9. FIG.
12 is a diagram showing drive waveforms of the circuit of FIG.
13 is a diagram showing drive waveforms of the circuit of FIG.
FIG. 14 is a diagram showing an optical writing head having a structure with four light emitting signal lines.
15 is a diagram showing drive waveforms of the circuit of FIG.
16 is a diagram showing drive waveforms of the circuit of FIG.
FIG. 17 is a circuit diagram of an optical write head in which data write wirings are doubled.
FIG. 18 is an equivalent circuit diagram of a self-scanning light-emitting element array chip having another structure.
19 is a plan view of the chip structure of FIG. 18. FIG.
20 is a circuit diagram of an optical writing head using the self-scanning light emitting element array chip of FIG.
FIG. 21 is a diagram showing the structure of an optical printer using the optical writing head of the present invention.
[Explanation of symbols]
1 Shift section
2 Light emitting part
10 Power supply terminal
11 φ1 terminal
12 φ2 terminal
13 φ_I Terminal
14 φ_R Terminal
15 Power supply wiring
16 φ1 wiring
17 φ2 wiring
18 φ_I wiring
20 Back side common electrode terminal
21,22 resistance
31 Start diode
41 Thyristor for shift section
42 Gate load resistance
43,44 Coupling diode
45 Light emitting unit thyristor
72 n-type cathode layer
73 p-type gate layer
74 n-type gate layer
75 p-type anode layer
76 p-type GaAs substrate
77 Cathode electrode
78 Gate electrode
79 Back side common electrode
110 Power supply wiring
111 φ1 wiring
112 φ2 wiring
113 φ_I wiring
114 φ_R wiring

Claims (16)

A plurality of first three-terminal light-emitting thyristors are arranged in a one-dimensional manner, the gates of adjacent first thyristors are connected to each other by a diode, each gate is connected to a power supply line through a gate load resistor, A shift unit in which the anode or cathode of the first thyristor is connected to the first clock pulse wiring, and the anode or cathode of the even-numbered first thyristor is connected to the second clock pulse wiring;
A plurality of second three-terminal light-emitting thyristors are arranged in a one-dimensional manner, are divided into blocks for each predetermined number of second thyristors, and two odd-numbered and even-numbered gates are provided between the second thyristors of each block. The first thyristors are connected to the gates of the corresponding first thyristors of the shift unit, which are blocked for each predetermined number of first thyristors, via diodes, and the anodes of the second thyristors. or cathode through the anode or cathode load resistor connected to the write signal line, via a diode the write signal line, a light emitting unit connected to the reset signal terminal,
A self-scanning light emitting element array chip comprising: A plurality of first three-terminal light-emitting thyristors are arranged in a one-dimensional manner, the gates of adjacent first thyristors are connected to each other by a diode, each gate is connected to a power supply line through a gate load resistor, A shift unit in which the anode or cathode of the first thyristor is connected to the first clock pulse wiring, and the anode or cathode of the even-numbered first thyristor is connected to the second clock pulse wiring;
A plurality of second three-terminal light-emitting thyristors are arranged in a one-dimensional manner, are divided into blocks for each predetermined number of second thyristors, and two odd-numbered and even-numbered gates are provided between the second thyristors of each block. The first thyristors are connected to the gates of the corresponding first thyristors of the shift unit, which are blocked for each predetermined number of first thyristors, via diodes, and the anodes of the second thyristors. or cathode through the anode or cathode load resistor connected to the write signal line, via a diode the write signal line, a latch portion which is connected to the reset signal terminal,
Arranging a plurality of third three-terminal light-emitting thyristor in one dimension, the gate of the third each thyristor is connected to the gate of a corresponding second thyristor of the latch portion, the anode of the third individual thyristors or A light-emitting portion having a cathode connected to a light-emitting signal wiring via an anode or a cathode load resistor; and
A self-scanning light emitting element array chip comprising: A plurality of first three-terminal light-emitting thyristors are arranged in a one-dimensional manner, the gates of adjacent first thyristors are connected to each other by a diode, each gate is connected to a power supply line through a gate load resistor, A shift unit in which the anode or cathode of the first thyristor is connected to the first clock pulse wiring, and the anode or cathode of the even-numbered first thyristor is connected to the second clock pulse wiring;
A plurality of second three-terminal light-emitting thyristors are arranged in a one-dimensional manner, are divided into blocks for each predetermined number of second thyristors, and each gate of K blocks (K is an integer of 2 or more) of each block. To the gates of one corresponding first thyristor of the shift section, which is blocked for each predetermined number of first thyristors, leaving two odd and even first thyristors in between. Are connected via diodes, and the anode or cathode of the second thyristor of each block is sequentially connected to K write signal wires via the anode or cathode load resistor, and each write signal wire is connected via a diode. A latch connected to one reset signal terminal,
Arranging a plurality of third three-terminal light-emitting thyristor in one dimension, the gate of the third each thyristor is connected to the gate of a corresponding second thyristor of the latch portion, the anode of the third individual thyristors or A light-emitting portion having a cathode connected to a light-emitting signal wiring via an anode or a cathode load resistor; and
A self-scanning light emitting element array chip comprising:   The self-scanning light-emitting element array chip according to claim 1, wherein each thyristor has a PNPN structure. A method of driving the self-scanning light-emitting element array chip according to claim 1,
Sequentially transferring the ON state of the first thyristor of the shift unit by applying first and second clock pulses to the first and second clock pulse wirings;
When the first thyristor of the shift unit is in the on state, the second thyristor corresponding to the first thyristor in the on state is turned on by applying a voltage to the write signal wiring of the light emitting unit. Steps,
When an odd-numbered thyristor of the two first thyristors of the shift unit is turned on, a voltage is applied to the write signal wiring of the light emitting unit, thereby the second thyristor in the on state. Step to light up,
Turning off the second thyristor in which the light emitting unit is lit by setting the reset signal terminal to 0 volts;
A driving method including: A method of driving the self-scanning light-emitting element array chip according to claim 2,
Sequentially transferring the ON state of the first thyristor of the shift unit by applying first and second clock pulses to the first and second clock pulse wirings;
When the first thyristor of the shift unit is in the on state, a voltage is applied to the write signal wiring of the latch unit to turn on the second thyristor corresponding to the first thyristor in the on state. Steps,
When the odd-numbered thyristor of the two first thyristors of the shift unit is turned on, a voltage is applied to the light emission signal wiring of the light emitting unit, thereby the second thyristor in the on state. Lighting a third thyristor corresponding to
Turning off the second thyristor in which the latch unit is turned on by setting the reset signal terminal to 0 volts;
A driving method including: A method of driving the self-scanning light-emitting element array chip according to claim 3,
Sequentially transferring the ON state of the first thyristor of the shift unit by applying first and second clock pulses to the first and second clock pulse wirings;
When the first thyristor of the shift unit is in the on state, a voltage is applied to the K write signal wirings of the latch unit, whereby K second thyristors corresponding to the first thyristor in the on state are provided. Turning on the thyristor;
When the odd-numbered thyristor of the two first thyristors of the shift unit is turned on, a voltage is applied to the light emission signal wiring of the light emitting unit, thereby the second thyristor in the on state. Lighting a third thyristor corresponding to
Turning off the second thyristor in which the latch unit is turned on by setting the reset signal terminal to 0 volts;
A driving method including: A self-scanning light-emitting element in which M groups (M is an integer of 2 or more) are arranged one-dimensionally with the N (N is an integer of 2 or more) self-scanning light-emitting element array chips according to claim 1 as one group. An array,
N first clock pulse common lines to which the first clock pulse lines of the N chips are sequentially connected;
1 to N second clock pulse common wires to which the second clock pulse wires of all the chips are connected;
One power common wiring to which the power wirings of all the chips are connected;
One reset signal common wiring to which the reset signal terminals of all the chips are connected;
M write signal common lines to which the write signal lines of the chips of each group are respectively connected;
An optical writing head comprising: A self-scanning light-emitting element in which N groups (N is an integer of 2 or more) according to claim 2 are arranged as one group and M groups (M is an integer of 2 or more) are arranged one-dimensionally. An array,
N first clock pulse common lines to which the first clock pulse lines of the N chips are sequentially connected;
1 to N second clock pulse common wires to which the second clock pulse wires of all the chips are connected;
One power common wiring to which the power wirings of all the chips are connected;
One reset signal common wiring to which the reset signal terminals of all the chips are connected;
Wherein the write-inclusive signal common wirings M book written inclusive signal lines of each group of chips are connected,
One light emission signal common line to which the light emission signal lines of all the chips are connected;
An optical writing head comprising: A self-scanning light-emitting element in which N groups (N is an integer of 2 or more) according to claim 2 are arranged as one group and M groups (M is an integer of 2 or more) are arranged one-dimensionally. An array,
N first clock pulse common lines to which the first clock pulse lines of the N chips are sequentially connected;
1 to N second clock pulse common wires to which the second clock pulse wires of all the chips are connected;
One power common wiring to which the power wirings of all the chips are connected;
One reset signal common wiring to which the reset signal terminals of all the chips are connected;
Wherein the write-inclusive signal common wirings M book written inclusive signal lines of each group of chips are connected,
An optical writing head comprising: N light emission signal common lines to which N chips of each group are connected in sequence. 4. A self-scanning light-emitting element in which N (N is an integer of 2 or more) self-scanning light-emitting element array chips according to claim 3 are grouped into one group, and M groups (M is an integer of 2 or more) are arranged one-dimensionally. An array,
N first clock pulse common lines to which the first clock pulse lines of the N chips are sequentially connected;
1 to N second clock pulse common wires to which the second clock pulse wires of all the chips are connected;
One power common wiring to which the power wirings of all the chips are connected;
One reset signal common wiring to which the reset signal terminals of all the chips are connected;
Wherein the write-inclusive signal common wire of K × M book written inclusive signal lines of each group of chips are connected,
An optical writing head comprising: N light emission signal common lines to which N chips of each group are connected in sequence. A method for driving an optical writing head according to claim 8, comprising:
Turning on the first thyristor of the same block of the same chip of each group;
Turning on the second thyristor corresponding to the first thyristor in the on state by applying a voltage to the M write signal common lines when the first thyristor is in the on state; ,
After performing the above steps for all the same chips, applying a voltage to the M write signal common wires to turn on the second thyristor in the on state;
Turning off the second thyristor that is turned on by setting the reset signal common wiring to 0 volts;
Repeating the above steps for the first thyristors of all the same blocks;
A driving method including: A method for driving an optical writing head according to claim 9, comprising:
Turning on the first thyristor of the same block of the same chip of each group;
Turning on the second thyristor corresponding to the first thyristor in the on state by applying a voltage to the M write signal common lines when the first thyristor is in the on state; ,
After performing the above steps for all the same chips, applying a voltage to the light emission signal common wiring turns on the third thyristor corresponding to the on-state second thyristor; ,
Turning off the second thyristor that is turned on by setting the reset signal common wiring to 0 volts;
Repeating the above steps for the first thyristors of all the same blocks;
A driving method including: A method for driving an optical writing head according to claim 10, comprising:
Turning on the first thyristor of the same block of the same chip of each group;
Turning on the second thyristor corresponding to the first thyristor in the on state by applying a voltage to the M write signal common lines when the first thyristor is in the on state; ,
Lighting a third thyristor corresponding to the on-state second thyristor by applying a voltage to the corresponding light emission signal common wiring;
Turning off the second thyristor that is turned on by setting the reset signal common wiring to 0 volts;
Performing the above steps for all the same chips;
A driving method including: A method for driving an optical writing head according to claim 11, comprising:
Turning on the first thyristor of the same block of the same chip of each group;
When the first thyristor is in the on state, a voltage is applied to the K × M write signal common lines to turn on the second thyristor corresponding to the first thyristor in the on state. Steps,
Lighting a third thyristor corresponding to the on-state second thyristor by applying a voltage to the corresponding light emission signal common wiring;
Turning off the second thyristor that is turned on by setting the reset signal common wiring to 0 volts;
Performing the above steps for all the same chips;
A driving method including:   An optical printer comprising the optical writing head according to claim 8, 9, 10, or 11.

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