JP5116832B2 - Optical print head and image forming apparatus - Google Patents

Description

  The present invention relates to an optical print head in which a plurality of light emitting elements are arranged, and an image forming apparatus that forms an image using the optical print head.

  In a conventional image forming apparatus, for example, an electrophotographic printer, an electrostatic latent image is formed by selectively irradiating a charged photosensitive drum according to print information, and toner is attached to the electrostatic latent image. Development is performed to form a toner image, and the toner image is transferred to a sheet and fixed. Among such electrophotographic printers, those using a light emitting thyristor as a light source in addition to a light emitting diode (LED) are known.

  In the case where a light emitting diode is used as the light source, the drive circuit and the light emitting element are provided in a one-to-one correspondence, and the light emission / non-light emission state depends on whether or not a current is directly passed between the anode terminal and the cathode terminal. To switch. On the other hand, in a device using a light-emitting thyristor, a drive circuit and a light-emitting element are provided so as to correspond to 1 to N (N> 1), an element to emit light is specified using a gate terminal, and an anode terminal and The light emission power is controlled by the current flowing between the cathode terminals. The drive circuit and the light emitting element are configured as different board units, and both are electrically connected by a connection cable. As an example of disclosing an image forming apparatus using such a light emitting thyristor, Japanese Patent Laid-Open No. 2007-81081 is cited.

  A conventional optical print head using LEDs will be described with reference to the drawings. FIG. 32 is a circuit diagram showing an optical print head using a conventional general LED. In the following description, an LED head that can print on an A4 size paper at a resolution of 600 dots per inch will be taken as an example, and a specific configuration will be described. In the example of FIG. 32, the total number of LED elements is 4992 dots, and 26 LED arrays are arranged to constitute this, and each LED array includes 192 LED elements. In the LED element, the cathodes of odd-numbered LEDs and the cathodes of even-numbered LEDs are connected, and the anode terminals of two adjacent LED elements are connected to each other. These LEDs are driven in a time-sharing manner.

  In FIG. 32, CHP1 and CHP2 are LED arrays, and descriptions of CHP3 to CHP26 are omitted. IC1 and IC2 are driver ICs arranged corresponding to CHP1 and CHP2, which are configured by the same circuit and connected in cascade with adjacent driver ICs. IC3 to IC26 are not shown. Reference numerals 31 to 38 denote LED elements, which are arranged 192 for each LED array. Reference numerals 41 and 42 denote power MOS transistors. The drain of the power MOS transistor 41 is connected to the cathodes of the LEDs 31, 33, 35, 37, etc., and the drain of the power MOS transistor 42 is connected to the cathodes of the LEDs 32, 34, 36, 38, etc. It is connected. The sources of the power MOS transistors 41 and 42 are connected to the ground. The gate of the power MOS transistor 41 is connected to the KDRV terminal of IC1, and the gate of the power MOS transistor 42 is connected to the KDRV terminal of IC2. The gate terminal signal of the power MOS transistor 41 is represented by ODD, and the gate terminal signal of the power MOS transistor 42 is represented by EVEN, which are shown in the figure.

  In the configuration shown in FIG. 32, there are four print data signals, and data for four pixels of odd-numbered or even-numbered pixels among the eight adjacent LED elements can be simultaneously transmitted for each clock signal. For this reason, print data signals HD-DATA 3 to 0 output from a print controller (not shown) are input to the LED head together with the clock signal HD-CLK, and the bit data of 4992 dots described above passes through the shift register formed of a flip-flop circuit. Sequentially transferred. Next, a latch signal HD-LOAD is input to the LED head, and the bit data is latched by each latch circuit provided corresponding to the flip-flop circuit.

Subsequently, according to the bit data and the print drive signal HD-STB-N, a light emitting element (light emitting diode: LED in this example) corresponding to dot data at a high (high) level is turned on. . VDD is a power supply, GND is a ground, and HD-HSYNC-N is a synchronization signal for setting an initial state of whether the LED drive is odd-numbered or even-numbered in the time-division drive described above. VREF is a reference voltage for instructing a drive current value for LED driving, and is generated by a reference voltage generation circuit (not shown) provided in the LED head.
JP 2007-81081 A

  The LED head is formed by arranging a large number of light emitting elements (LEDs), and the total number of LEDs is several thousand. For this reason, when the elements are simultaneously turned on, a large current is generated in the common wiring connected to the elements. In the configuration according to the prior art, a large number of LED elements are divided into a plurality of groups and driven in a time-sharing manner for each group. However, each common wiring provided for each group has a power MOS as a switch element. It was necessary to connect the transistors to perform the group selection operation.

  Since the power MOS transistor is required to have a capability of driving a large current, the chip size is inevitably large. For this reason, since the LED head substrate on which the LED head substrate is disposed occupies a large area, it is not desirable because the size reduction of the head is restricted. Further, since the power MOS transistor element needs to be mounted, the cost of the member of the head is increased, which has been a major obstacle in reducing the cost of the head.

In order to solve the above problems, the optical print head of the present invention has a first terminal, a second terminal, and a control terminal for controlling conduction between the first terminal and the second terminal. A plurality of light emitting elements that emit light when a current flows between the first terminal and the second terminal; and the light emitting elements provided corresponding to at least two of the plurality of light emitting elements. A drive circuit that emits light by passing a current between the first terminal and the second terminal of the element; and a control circuit and one end of the light-emitting element that are provided corresponding to each of the plurality of light-emitting elements. A bidirectional voltage drop generating circuit that is configured by a pair of diodes that are connected and reversely connected to each other, and that commonly connects the other ends of the plurality of bidirectional voltage drop generating circuits. Pair with the bus and the common bus Te, is characterized in that a buffer circuit for outputting a control signal to be supplied to the control terminal of the light emitting element.

According to the present invention having the above-described configuration, each of the first terminal, the second terminal, and a control terminal for controlling conduction between the first terminal and the second terminal is provided. A plurality of light emitting elements that emit light when a current flows between a terminal and the second terminal, and the first light emitting element is provided corresponding to at least two of the plurality of light emitting elements. A driving circuit that emits light by passing a current between the terminal and the second terminal; and a plurality of the light emitting elements, the control terminal and one end of the light emitting element are connected to each other, and are opposite to each other. A bidirectional voltage drop generating circuit configured to include a pair of connected diodes that generates a voltage drop in both directions, a common bus that commonly connects the other ends of the plurality of bidirectional voltage drop generating circuits, and the common The light emitting element is Since a structure in which a buffer circuit for outputting a control signal to be supplied to the control terminal, it is possible to suppress the variation in light output of the light emitting element, to eliminate the need for power MOS transistor for driving the light emitting element Thus, a space-saving and low-cost optical print head and image forming apparatus can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element which is common in each figure. FIG. 1 is a block diagram showing an electrophotographic printer according to the present invention, and FIG. 2 is a circuit diagram showing an optical print head according to a first embodiment. In each embodiment described below, an electrophotographic printer will be described as an example of the image forming apparatus.

  In FIG. 1, reference numeral 1 denotes a print control unit including a microprocessor, a ROM, a RAM, an input / output port, a timer, and the like. The entire printer is sequence-controlled by a video signal (one-dimensionally arranged dot map data) SG2 or the like, and a printing operation is performed.

  When the print instruction is received by the control signal SG1, the print controller 1 first detects whether or not the fixing device 22 including the heater 22a is within the usable temperature range by the fixing device temperature sensor 23, and the temperature range. If not, the heater 22a is energized to heat the fixing device 22 to a usable temperature. Next, the development / transfer process motor (PM) 3 is rotated via the driver 2, and at the same time, the charging voltage power supply 25 is turned on by the charge signal SGC to charge the developing device 27.

  Then, the presence / absence and size of the unillustrated paper set are detected by the paper remaining amount sensor 8 and the paper size sensor 9, and paper feeding suitable for the paper is started. Here, the paper feed motor (PM) 5 can be rotated in both directions via the driver 4, and the paper is set in advance until it is first reversed and detected by the paper inlet sensor 6. Send only the amount. Subsequently, the sheet is rotated forward to convey the sheet into a printing mechanism inside the printer.

  When the paper reaches a printable position, the print control unit 1 transmits a timing signal SG3 (including a main scanning synchronization signal and a sub-scanning synchronization signal) to the upper controller, and receives a video signal SG2 from the upper controller. Receive. The video signal SG2 edited for each page in the host controller and received by the print control unit 1 is transferred to the optical print head (recording head) 19 as a print data signal HD-DATA. The optical print head 19 has a plurality of light emitting thyristors arranged for printing one dot (pixel) on a line.

When the print control unit 1 receives a video signal for one line, it transmits a latch signal HD-LOAD to the optical print head 19 to hold the print data signal HD-DATA in the optical print head 19. The print control unit 1 can also print the print data signals HD-DATA3 to HD-DATA0 held in the optical print head 19 while receiving the next video signal SG2 from the host controller. HD-CLK is a clock signal for transmitting print data signals HD-DATA3 to HD-DATA0 to the optical print head 19. HD-HSYNC-N is a main scanning synchronization signal and HD-STB.
-N is a strobe signal.

  Transmission / reception of the video signal SG2 is performed for each print line. Information printed by the optical print head 19 is formed into a latent image as a dot having an increased potential on a photosensitive drum (not shown) charged to a negative potential. Then, in the developing device 27, the toner for image formation charged to a negative potential is attracted to the latent image dots by an electrical attraction force to form a toner image.

  Thereafter, the toner image is sent to the transfer unit 28, and on the other hand, the transfer high voltage power supply 26 is turned on to a positive potential by the transfer signal SG4, and the transfer unit 28 is on the sheet passing between the photosensitive drum and the transfer unit 28. The toner image is transferred to. The sheet on which the toner image has been transferred is brought into contact with a fixing device 22 having a built-in heater 22a and conveyed, and the toner image is fixed on the sheet by the heat of the fixing device 22. The sheet on which the toner image is fixed is further conveyed and discharged from the printer printing mechanism through the sheet discharge sensor 7 to the outside of the printer.

  In response to detection by the paper size sensor 9 and the paper inlet sensor 6, the print control unit 1 applies a voltage from the transfer high-voltage power supply 26 to the transfer device 28 only while the paper passes through the transfer device 28. When printing is completed and the paper passes through the paper discharge sensor 7, the application of the voltage to the developing device 27 by the charging high-voltage power supply 25 is finished, and at the same time, the rotation of the developing / transfer process motor 3 is stopped. Thereafter, the above operation is repeated.

FIG. 2 is a diagram illustrating the structure of the optical print head according to the first embodiment. In the description of the present embodiment, as an example, an LED head capable of printing at a resolution of 600 dots per inch on an A4 size paper will be taken and its specific configuration will be described. In this example, the total number of light emitting elements is 4992 dots, and 26 light emitting element arrays are arranged to constitute this, and each light emitting element array includes 192 light emitting elements. In each light-emitting element, the cathode terminal is connected to the ground, and the anode terminals of two light-emitting elements arranged adjacent to each other are connected, and the odd-numbered light-emitting elements and the even-numbered light-emitting elements are time-shared. Driven.

In FIG. 2, CHP1 and CHP2 are light emitting element arrays, and descriptions of CHP3 to CHP26 are omitted. IC1 and IC2 are driver ICs arranged corresponding to CHP1 and CHP2, which are configured by the same circuit and connected in cascade with adjacent driver ICs. IC3 to IC26 are not shown. 101 to 108 are light emitting thyristor elements, and 192 are arranged for each light emitting element array. The light emitting thyristor includes an anode that is a first terminal, a cathode that is a second terminal, and a gate that is a third terminal, and the anode terminal is connected to each of two adjacent light emitting thyristors, It is connected to each terminal of DO1 to DO96 of the driver IC. The cathode terminal of the light emitting thyristor is connected to the ground. Further, the gate terminals of the odd-numbered light-emitting thyristors in the light-emitting thyristor array and the gate terminals of the even-numbered light-emitting thyristors are connected to each other and to the gate drive terminal of the driver IC.

For example, the anode terminals of the light emitting thyristor 101 and the light emitting thyristor 102 are connected to each other, connected to the DO 96 which is the anode driving terminal of the driver IC (IC1), the cathodes of the light emitting thyristor 101 and the light emitting thyristor 102 are connected to the ground, The gate terminals of the light-emitting thyristor 101 and the light-emitting thyristor 103 are connected to each other and connected to a gate driving terminal G2 provided in the driver IC (IC1), and the gate terminals of the light-emitting thyristor 102 and the light-emitting thyristor 104 are connected to each other and connected to the driver IC ( IC1) is connected to a gate drive terminal G1 provided in IC1).

In the configuration shown in FIG. 2, there are four print data signals, and among the eight adjacent light-emitting thyristors, data for four odd-numbered or even-numbered pixels can be sent simultaneously for each clock signal. . For this reason, the print data signals HD-DATA 3 to 0 output from the print control unit 1 are input to the optical print head 19 together with the clock signal HD-CLK, and the bit data for 4992 dots described above comprises a flip-flop circuit described later. The data is sequentially transferred through the shift register. Next, a latch signal HD-LOAD is input to the optical print head 19, and the bit data is latched by each latch circuit provided corresponding to the flip-flop circuit.

Subsequently, the bit data and the print drive signal HD-STB-N turn on the light emitting elements corresponding to the dot data at the high (high) level. Note that VDD is a power supply, GND is a ground, and HD-HSYNC-N is a synchronization signal for setting an initial state as to whether it is odd-numbered LED driving or even-numbered LED driving in the time-division driving described above. , VREF is a reference voltage for instructing a drive current value for LED driving, and is generated by a reference voltage generation circuit (not shown) provided in the optical print head 19.

FIG. 3 is a diagram showing a configuration of the light-emitting thyristor shown in FIG. FIG. 3A shows a circuit symbol, and the light-emitting thyristor 101 includes three terminals: an anode terminal A, a cathode terminal K, and a gate terminal G. FIG. 3B is a view showing a cross-sectional structure of the light emitting thyristor shown in FIG. The light-emitting thyristor 101 shown in the figure is formed by using a GaAs wafer base material and epitaxially growing a predetermined crystal on the upper layer of the base material by a known MO-CVD (Metal Organic-Chemical Vapor Deposition) method.

  First, after epitaxial growth of a predetermined buffer layer and sacrificial layer (not shown), an N-type layer 133 containing an N-type impurity in an AlGaAs base material, and a P-type layer 132 formed by containing a P-type impurity, A wafer having an NPN three-layer structure in which an N-type layer 131 containing an N-type impurity is sequentially laminated is formed. Next, a P-type impurity region 134 is selectively formed in a part of the uppermost N-type layer by a known photolithography method. Further, element isolation is performed by forming a groove by a known dry etching method. Further, a part of the N-type region 133 which is the lowermost layer of the thyristor is exposed during the etching process, and metal wiring is formed in the region 133 to form a cathode electrode. At the same time, an anode electrode and a gate electrode are formed in the P-type region 134 and the N-type region 131, respectively.

  FIG. 3C shows another embodiment of the light emitting thyristor. In this configuration, a GaAs wafer substrate is used, and a predetermined crystal is epitaxially grown on the upper layer of the substrate by a known MO-CVD method. First, after epitaxial growth of a predetermined buffer layer and sacrificial layer (not shown), an N-type layer 133 containing an N-type impurity in an AlGaAs base material, and a P-type layer 132 formed by containing a P-type impurity, A wafer having a four-layer structure of PNPN in which an N-type layer 131 containing an N-type impurity and a P-type layer 135 containing a P-type impurity and laminated is sequentially formed.

  Further, element isolation is performed by forming a groove by a known dry etching method. Further, a part of the N-type region 133 which is the lowermost layer of the light emitting thyristor is exposed during the etching process, and a metal wiring is formed in the region 133 to form a cathode electrode. Similarly, a part of the P-type region 135 which is the uppermost layer is exposed, and a metal wiring is formed in the region 135 to form an anode electrode. At the same time, a gate electrode is formed in the N-type region 131.

FIG. 3D is an equivalent circuit of a light-emitting thyristor drawn in comparison with FIGS.
The light-emitting thyristor 101 includes a PNP transistor 141 and an NPN transistor 142. The emitter of the PNP transistor 141 corresponds to the anode terminal A of the thyristor, and the base of the PNP transistor 141 corresponds to the gate terminal G of the thyristor. The collector of NPN transistor 142 is also connected. The collector of the PNP transistor 141 is connected to the base of the NPN transistor 142, and the emitter of the NPN transistor 142 corresponds to the cathode terminal K of the thyristor.

  In the thyristor shown in FIG. 3, an AlGaAs layer is formed on a GaAs wafer substrate. However, the present invention is not limited to this, and a material such as GaP, GaAsP, or AlGaInP may be used. A material such as GaN or AlGaN may be formed on a sapphire substrate. The above-described thyristor element is bonded to a wafer on which driver ICs (shown as IC1 to IC26 in FIG. 3) are arranged using, for example, an epitaxial bonding method disclosed in Japanese Patent Application Laid-Open No. 2007-81081, and known etching is performed. Unnecessary portions are removed by the method, and terminal portions of the thyristor element are exposed. Next, each terminal planned portion of the thyristor and the terminal portion of the driver IC are connected using a thin film wiring formed by a photolithography method. Further, a composite chip composed of a light emitting element and a driving element is formed by separating the chip into a plurality of chips using a known dicing method.

  FIG. 4 is a block diagram illustrating a detailed configuration of the driver IC according to the first embodiment. In FIG. 4, reference numeral 111 denotes a resistor, which is a pull-up element connected between the strobe terminal and the power supply VDD. 112 and 113 are inverter circuits, and 114 is a NAND circuit. FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flop circuits and constitute a shift register. LTA1 to LTD1 and LTA24 to LTD24 are latch elements, and they constitute a latch circuit as a whole. 117 is a MEM2 block, and 121 is a MEM block, each of which is a memory circuit, and includes correction data (dot correction data) for correcting variation in the amount of light of each light emitting element and light amount correction data (chip correction) for each light emitting element array chip. Data) or unique data for each driver IC.

  Reference numeral 118 denotes a MUX2 block, which is a multiplexer circuit. This circuit is provided to switch between the odd-numbered dot correction data and the even-numbered dot correction data among the adjacent light emitting element dots in the dot correction data output from the memory MEM2. The DRV block (119) is a light emitting element driving circuit, the SEL block 120 is a selector circuit, and the CTRL1 block (115) is a control circuit, and a write command signal (Writing command signal ( E1, E2, W3 to W0). The CTRL2 block (116) is a control circuit, and generates a data switching command signal (S1N, S2N) between odd dot data and even dot data to the multiplexer MUX2. The data switching command signal (S1N, S2N) is also connected to the input terminals of the buffer circuits 123 and 124, and the output of the buffer circuit is connected to the G1 and G2 terminals of the driver IC. As shown in FIG. Each array is connected to the gate terminals of the light emitting thyristors 102 and 101.

  The ADJ block (122) is a control voltage generation circuit, which receives the reference voltage value VREF input from the VREF terminal and generates a control voltage for driving the light emitting element. The flip-flop circuits FFA1 to FFA25 are cascade-connected, the data input terminal D of FFA1 is connected to the data input terminal DATAI0 of the driver IC, the data outputs of FFA24 and FFA25 are input to the selector circuit SEL, and the output terminal Y0 is It is connected to the data output terminal DATAO0 of the driver IC.

Similarly, flip-flop circuits FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals D of FFB1, FFC1, and FFD1 are connected to the data input terminals DATAI1, DATAI2, and DATAI3 of the driver IC, respectively. The outputs from FFB 24 and FFB 25, FFC 24 and FFC 25, FFD 24 and FFD 25 are also connected to the selector circuit SEL, and the respective outputs are connected to the data output terminals DATAO1, DATAO2, and DATAO3 of the driver IC. Accordingly, the flip-flop circuits FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 each constitute a 25-stage shift register circuit, and the selector circuit 120 switches the number of shift stages between 24 and 25. be able to.

  The data output terminals DATAO0 to DATAO3 of the driver IC are respectively connected to the data input terminals DATAO0 to DATAI3 of the driver IC at the next stage. Therefore, with all the shift registers of the driver ICs IC1 to IC26, the data signal HD-DATA3 input from the print control unit 1 to the first-stage driver IC DRV1 is shifted in synchronization with the clock signal in 24 × 26 stages or 25 × 26 stages. A stage shift register circuit is configured. Similarly, the data signals HD-DATA2, HD-DATA1, and HD-DATA0 input from the print control unit 1 to the first stage driver IC IC1 are shifted in synchronization with the clock signal with all the shift registers of the driver ICs IC1 to IC26. Each of the 24 × 26 stage or 25 × 26 stage shift register circuits is configured.

  The latch circuits LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, and LTD1 to LTD24 are latched by a latch signal LOAD-P. The latch circuits LTA1 to LTA24 latch the data signal HD-DATA0 stored in the flip-flop circuits FFA1 to FFA24. Similarly, the latch circuits LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flop circuits FFB1 to FFB24. LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flop circuits FFC1 to FFC24. LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flop circuits FFD1 to FFD24. The NAND circuit 114 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the terminal LOAD via the inverter circuits 112 and 113, and outputs to the light emitting element driving unit DRV. A signal for controlling on / off of the drive is generated.

  FIG. 5 is a circuit configuration diagram of the memory circuit MEM2 shown in FIG. In the configuration of this embodiment, the dot correction data for correcting the light amount of the light emitting element is 4 bits, and the light amount can be corrected by adjusting the driving current in 16 steps for each dot. FIG. 5 shows two (two dots) adjacent memory cell circuits, each of which is divided into regions 151 and 152 surrounded by broken lines. The left circuit 151 stores correction data for odd-numbered dots (for example, dot No. 1), and the right circuit 152 stores correction data for even-numbered dots (for example, dot No. 2). is there. The memory circuit MEM2 includes a buffer circuit 181 and includes an inverter 182 provided for generating a data signal complementary thereto, inverters 153 to 160 constituting correction memory cells, and NMOS transistors 161 to 176. .

  The memory cell circuit MEM2 includes a correction data input terminal D, an enable signal E1 that permits data writing on the odd-numbered dot side, an enable signal E2 that permits data writing on the even-numbered dot side, and a memory cell selection terminal. W0 to W3, correction data output terminals ODD0 to ODD3 for odd-numbered dots, and correction data output terminals EVN0 to EVN3 for even-numbered dots are provided.

The data input terminal D of the memory cell circuit MEM2 shown in FIG. 5 is connected to the data output terminals Q of the flip-flop circuits FFA1, FFB1, FFC1, FFD1, FFA2,... FFA24, FFB24, FFC24, FFD24, etc. shown in FIG. Yes. The write control signals W0 to W3 from the control circuit CTRL1 (115) are input to the memory cell selection terminals W0 to W3, respectively, and the control circuit CT is connected to the write enable terminal of the memory MEM2.
Write enable signals E1 and E2 from RL1 (115) are input.

  The input terminal of the buffer circuit 181 is a correction data input terminal D, and the output terminal of the buffer circuit 181 is connected to the first terminals of the NMOS transistors 161, 165, 169, and 173. The input terminal of the inverter 182 is connected to the output of the buffer 181, and the output of the inverter 182 is connected to the first terminals of the NMOS transistors 164, 168, 172, 176. The inverter 153 and the inverter 154, the inverter 155 and the inverter 156, the inverter 157 and the inverter 158, the inverter 159 and the inverter 160 are connected in series, and each form a memory cell. Further, the NMOS transistor 161 and the NMOS transistor 162, the NMOS transistor 163 and the NMOS transistor 164, the NMOS transistor 165 and the NMOS transistor 166, the NMOS transistor 167 and the NMOS transistor 168, the NMOS transistor 169 and the NMOS transistor 170, the NMOS transistor 171 and the NMOS transistor 172, The NMOS transistor 173 and the NMOS transistor 174, and the NMOS transistor 175 and the NMOS transistor 176 are connected in series, respectively, and one end of the series connection is connected to the output of the buffer 181 and the inverter 182 respectively.

  The gate terminals of the NMOS transistors 162 and 163 are connected to the terminal W0. The gate terminals of the NMOS transistors 166 and 167 are connected to the terminal W1. The gate terminals of the NMOS transistors 170 and 171 are connected to the terminal W2. The gate terminals of the NMOS transistors 174 and 175 are connected to the terminal W3. The enable signal E1 is connected to the gate terminals of NMOS transistors 161, 164, 165, 168, 169, 172, 173, and 176.

The output from the inverter 153 is connected to the terminal ODD0. The output from the inverter 155 is connected to the terminal ODD1. The output from the inverter 157 is connected to the terminal ODD2. The output from the inverter 159 is connected to the terminal ODD3. The above is for the memory cell 151, but the enable signal connected to the memory cell 152 is also E2.
, Except that the output signal names are EVN0 to EVN3.

  FIG. 6 shows a multiplexer circuit shown as the MUX2 block in FIG. FIG. 6 is composed of four independent multiplexer circuits, and 191 to 198 are PMOS transistors. The gates of the PMOS transistors 191, 193, 195, and 197 are connected to the S1N terminal, the gates of the PMOS transistors 192, 194, 196, and 198 are connected to the S2N terminal, and the first terminal of the PMOS transistor 191 is connected to the ODD0 terminal. The second terminal of the PMOS transistor 192 is connected to the EVN0 terminal, and the second terminals of the PMOS transistor 191 and the PMOS transistor 192 are connected to the terminal Q0.

  The circuit composed of the PMOS transistors 193 to 198 has the same configuration. The first terminal of the PMOS transistor 193 is connected to the ODD1 terminal, the second terminal of the PMOS transistor 294 is connected to the EVN1 terminal, and the PMOS transistor 193 and the PMOS transistor 194 are connected. The second terminals are connected to the terminal Q1. The first terminal of the PMOS transistor 195 is connected to the ODD2 terminal, the second terminal of the PMOS transistor 196 is connected to the EVN2 terminal, and the second terminals of the PMOS transistor 195 and the PMOS transistor 196 are connected to the terminal Q2. . Further, the first terminal of the PMOS transistor 197 is connected to the ODD3 terminal, the second terminal of the PMOS transistor 198 is connected to the EVN3 terminal, and the second terminals of the PMOS transistor 197 and the PMOS transistor 198 are connected to the terminal Q3. .

  In the configuration of the multiplexer circuit described above, the PMOS transistor is used as the switch element for the following reason, and a novel device capable of reducing the number of elements used while preventing operational troubles. It has a configuration. That is, when the S1N signal is set to the low level to turn on the PMOS transistor 191, if the ODD0 signal is at the high level, a voltage substantially equal to the signal level is output from the Q0 terminal. In this way, if the transmission is at a high level, there is no problem even if the PMOS transistor is used as a switching element. Similarly, if the ODD0 signal is at the low level (approximately 0V), the second terminal of the PMOS transistor 191 falls to a potential close to the threshold voltage of the PMOS transistor 191, but falls to the low level (approximately 0V). There is no. Thus, the low-level transmission function has a disadvantage that is not perfect.

  In order to eliminate such drawbacks, in the configuration according to the prior art, an analog switch in which an NMOS transistor is connected in parallel with the PMOS transistor is configured as a switch means for data selection. In this configuration, an output potential substantially equal to the input signal potential to be transmitted can be obtained, and there is no difference between the input potential and the output potential due to the presence of the switch means. On the other hand, it is necessary to provide a pair of PMOS and NMOS transistors for each data signal, which requires twice the number of elements as compared with the configuration of FIG. 6, and increases the chip area of the IC for arranging them. The disadvantage of occupying was inherent.

  On the other hand, the configuration of FIG. 6 has the advantage that the number of elements is half that of a circuit configured using a general analog switch, but the low level transmission function is not perfect. Is inherent. However, as will be described later, in the DRV circuit, which is a subsequent circuit to which the output of the multiplexer MUX2 is connected, an input voltage that is substantially equal to the VDD potential is required as the High level, whereas the Low level drops to a Vcont potential that will be described later. This is sufficient, and a low level potential that drops to approximately 0 V is not required. Therefore, by using the multiplexer circuit shown in FIG. 6, it is possible to reduce the number of required elements while avoiding restrictions on circuit operation.

  FIG. 7 shows a light emitting element driving circuit corresponding to the DRV block shown in FIG. The element driving circuit includes PMOS transistors 200 to 205, an NMOS transistor 206, NAND circuits 210 to 213, and a NOR circuit 207. The element drive circuit DRV includes a print data input terminal E, an input terminal S for commanding on / off of element drive, an input terminal V, correction data input terminals Q0 to Q3, and a drive current output terminal DO. I have.

  A print data input terminal E of the element driving circuit is connected to QN outputs of latch circuits such as LTA1 to LTD1 and LTA12 to LTD12 in FIG. The input terminals Q3 to Q0 are connected to correction data output terminals Q3 to Q0 from the multiplexer circuit MUX2 in FIG. An element drive ON / OFF command signal output from the NAND circuit 114 of FIG. 4 is input to the terminal S. A control voltage Vcont from the control voltage generation circuit ADJ of FIG. The drive current output terminal DO is connected to the anode of the light emitting thyristor by a bonding wire (not shown) or a thin film wiring described later. Two input terminals of the NOR circuit 207 are connected to a terminal S and a terminal E, respectively. The first input terminals of the NAND circuits 210 to 213 are connected to the output terminal of the NOR circuit 207. The second input terminals of the NAND circuits 213 to 210 are connected to the correction data input terminals Q3 to Q0, respectively.

  The gate terminals of the PMOS transistors 200 to 203 are connected to the output terminals of the NAND circuits 210 to 213, respectively. The source terminals of the PMOS transistors 200 to 205 are connected to the power supply VDD, and the drain terminals of the PMOS transistors 200 to 204 are connected to the drive current output terminal DO. On the other hand, the power supplies of the NAND circuits 210 to 213 and the NOR circuit 207 are connected to a power supply VDD (not shown), and the ground of these circuits is connected to the terminal V and kept at a potential of Vcont.

  As will be described later, the potential difference between the potential of the power supply VDD and the potential of Vcont is substantially equal to the gate-source voltage when the PMOS transistors 200 to 204 are turned on. By changing this voltage, the drain current of the PMOS transistors 200 to 204 is changed. Can be adjusted. The control voltage generation circuit ADJ of FIG. 4 is provided for receiving the reference voltage Vref and controlling the control voltage Vcont so that the drain current of the PMOS transistors 200 to 204 and the like becomes a predetermined value.

  Returning to the description of FIG. 7, when the print data is on (at this time, the input level of the terminal E is Low), and the drive on / off command signal S of the light emitting element is Low to command the drive on. The output of the NOR circuit 207 becomes High. At this time, according to the terminal data of Q3 to Q0, the output signal level of the NAND circuits 210 to 213 and the output of the inverter constituted by the PMOS transistor 205 and the NMOS transistor 206 become the VDD potential or the Vcont potential. The PMOS transistor 204 is a main drive transistor that supplies a main drive current to the light-emitting element, and the PMOS transistors 200 to 203 are auxiliary drive transistors for adjusting the light-emitting element drive current for each dot to correct the light amount.

  The main drive transistor 204 is driven according to the print data. The auxiliary drive transistors 200 to 203 are selectively driven according to the outputs of the multiplexer outputs Q3 to Q0 when the output of the NOR circuit 207 is at a high level. As will be described later, from the multiplexer outputs Q3 to Q0, correction memory data storing correction data for correcting the light emission variation of each dot of the light emitting element is output. That is, together with the main drive transistor 204, the auxiliary drive transistors 200 to 203 are selectively driven according to the correction data, and a drive current obtained by adding the drain current of the selected auxiliary drive transistor to the drain current of the main drive transistor 204 is obtained. , And supplied from the terminal DO to the light emitting element.

  When the PMOS transistors 200 to 203 are driven, the outputs of the NAND circuits 210 to 213 are at a low level (that is, a level substantially equal to the control voltage Vcont), so that the gate potentials of the PMOS transistors 200 to 203 are almost equal to the control voltage. Equal to Vcont. At this time, the PMOS transistor 205 is in the off state, the NMOS transistor 206 is in the on state, and the gate potential of the PMOS transistor 204 is also substantially equal to the control voltage Vcont. Therefore, the drain current values of the PMOS transistors 200 to 204 can be collectively adjusted by the control voltage Vcont. At this time, since the NAND circuits 210 to 213 operate with the power supply potential VDD and the ground potential Vcont as the power supply and the ground potential, respectively, the potential of the input signal is also in accordance with the power supply potential VDD and the ground potential Vcont. Well, the Low level does not necessarily need to be 0V. Therefore, even if the multiplexer having the configuration shown in FIG.

  FIG. 8 is a circuit diagram showing a configuration of the control circuit CTRL1 block (115) shown in FIG. In FIG. 8, 221 to 225 are flip-flop circuits, 226 is a NOR circuit, 227 and 228 are AND circuits, and 230 to 233 are AND circuits. The negative logic reset terminals (R) of the flip-flop circuits 221 to 225 are connected to the LOAD terminal, and the latch signal LOAD-P is input thereto. The clock terminals of the flip-flop circuits 221 and 222 are connected to the STB terminal, and the STB-P signal is input. The Q outputs of the flip-flop circuit 221 and the flip-flop circuit 222 are connected to the input of the NOR circuit 226, and the output of the NOR circuit 226 is connected to the D input of the flip-flop circuit 221.

  The clock terminal of the flip-flop circuit 223 is connected to the Q output terminal of the flip-flop circuit 221, and the QN output of the flip-flop circuit 223 is connected to its own D input terminal. The Q output of the flip-flop circuit 223 is connected to one input terminal of the AND circuit 227, the QN output terminal of the flip-flop circuit 223 is connected to one input terminal of the AND circuit 228, and the other of the AND circuit 227 and the AND circuit 228 The LOAD-P signal is input to the input terminal. Further, the outputs of the AND circuits 227 and 228 are connected to the terminals E1 and E2, and serve as a write enable signal for the memory circuit MEM2 in FIG.

  The clock terminals of the flip-flop circuits 224 and 225 are connected to the output of the AND circuit 227, the D terminal of the flip-flop circuit 224 is connected to the Q output terminal of the flip-flop circuit 225, and the D input terminal of the flip-flop circuit 225 is the flip-flop. The QN output terminal of the circuit 224 is connected. The first input of the AND circuit 233 is connected to the Q terminal of the flip-flop circuit 225, the second input of the AND circuit 233 is connected to the QN terminal of the flip-flop circuit 224, and the first input of the AND circuit 232 is the flip-flop circuit 225. The second input of the AND circuit 232 is connected to the Q terminal of the flip-flop circuit 224, the first input of the AND circuit 231 is connected to the QN terminal of the flip-flop circuit 225, and the AND circuit 231 has a second input. The two inputs are connected to the Q terminal of the flip-flop circuit 224, the first input of the AND circuit 230 is connected to the QN terminal of the flip-flop circuit 225, and the second input of the AND circuit 230 is connected to the QN terminal of the flip-flop circuit 224. The third input of the AND circuits 230 to 233 is the Q of the flip-flop circuit 222. It is connected to the force. The output terminals of the AND circuits 230 to 233 are connected to the W0 to W3 terminals, and serve as write command signals for the memory circuit MEM2 in FIG.

  FIG. 9 is a circuit diagram showing a configuration of the control circuit CTRL2 block (116) shown in FIG. In FIG. 9, 241 is a flip-flop circuit, 242 and 243 are buffer circuits. The clock terminal of the flip-flop circuit 241 is connected to the LOAD terminal and the LOAD-P signal is input. The negative logic reset terminal (R) is connected to the HSYNC terminal and the HSYNC-N signal is input. The D terminal is connected to its own QN terminal. The input terminal of the buffer circuit 242 is connected to the Q terminal of the flip-flop circuit 241, and the input terminal of the buffer circuit 243 is connected to the QN terminal of the flip-flop circuit 241. The outputs of the buffer circuits 243 and 242 are connected to the S1N and S2N terminals, and are output as data selection command signals for the multiplexer circuit MUX2 in FIG.

  FIG. 10 is a control voltage generation circuit shown as ADJ block (122) in FIG. 4, and one circuit is provided for each driver IC chip. In FIG. 10, 251 is an operational amplifier, 252 is a PMOS transistor, and 253 is an analog multiplexer circuit. The source of the PMOS transistor 252 is connected to the power supply VDD, and the gate terminal is connected to the output terminal of the operational amplifier 251 and to the terminal V. The PMOS transistor 252 has the same gate length as that of the PMOS transistors 200 to 204 shown in FIG. The drain current of the PMOS transistor 252 is entered as Iref in the figure.

  On the other hand, the inverting input terminal of the operational amplifier 251 is connected to the VREF terminal, a potential of Vref is applied, the non-inverting input terminal is connected to the output terminal Y of the multiplex 253 described later, and the output terminal of the operational amplifier 251 is the PMOS transistor. It is connected to the gate terminal of 252 and is connected to the terminal V and is connected to the circuit of FIG. R00 to R15 are resistors. The multiplexer circuit 253 includes 16 input terminals P0 to P15 to which analog voltages are input, an output terminal Y to output analog voltages, and four input terminals S3 to S0 to which logic signals are input. One of the P0 to P15 terminals is selected by the combination of 16 signal logics set by the logic signal, and the potential applied to the terminal is output from the output terminal Y. In other words, one of the P0 to P15 terminals is selected according to the logic signal level of the input terminals S3 to S0, and a current path is formed between the output terminal Y and the terminal.

A feedback control circuit is configured by a circuit including the operational amplifier 251, the resistor string R00 to R15, and the PMOS transistor 252, and the potential of the non-inverting input terminal of the operational amplifier 251 is controlled to be substantially equal to Vref. . Therefore, the drain current (Iref) of the PMOS transistor 252 in FIG. 10 is determined from the combined resistance value of the portion selected by the multiplexer 253 among the resistors R00 to R15 and the reference voltage Vref input to the operational amplifier 251. Will be. More specifically, when the logical value of the input terminals S3 to S0 is “1111” and the maximum correction state is commanded, the P15 terminal and the Y output terminal of the multiplexer 253 are electrically connected. And the potential of the P15 terminal is controlled to be substantially equal to the Vref potential. As a result, the drain current Iref of the PMOS transistor 252 is
Iref = Vref / R00
It becomes.

On the other hand, when the logical values of the input terminals S3 to S0 are “0111” and the center of the correction state is commanded, the P7 terminal and the Y output terminal of the multiplexer 253 are brought into conduction, and the P7 terminal Is controlled to be substantially equal to the Vref potential. As a result, the drain current Iref of the PMOS transistor 252 is Iref = Vref / (R00 + R01 + .. + R07 + R08).
It becomes.

Further, when the logical values of the input terminals S3 to S0 are “0000” and the minimum correction state is instructed, the P0 terminal and the Y output terminal of the multiplexer 253 are brought into conduction, and the P0 terminal Is controlled to be substantially equal to the Vref potential. As a result, the drain current Iref of the PMOS transistor 252 is Iref = Vref / (R00 + R01 + .. + R14 + R15).
It becomes.

  As described above, the PMOS transistors 200 to 204 and the PMOS transistor 252 shown in FIG. 7 have the same gate length and are configured to operate in the saturation region, so that each transistor has a current mirror relationship. Thus, when the PMOS transistors 200 to 204 are turned on, a drain current proportional to the Iref is generated. As a result, the Iref current can be adjusted in 16 steps according to the logical value state applied to the input terminals S3 to S0 of the multiplexer 253, and the drain current of the PMOS transistors 200 to 204 in FIG. 7 can also be adjusted in 16 steps. be able to.

  FIG. 11 shows the configuration of the drive buffer circuits 123 and 124 for the gate terminals of the thyristor shown in FIG. FIG. 11A is a circuit diagram symbol of the buffer circuit 123, and FIG. 11B shows its circuit configuration. In FIG. 11B, 301 and 302 are inverter circuits, and 303 and 304 are PMOS transistors. The input of the inverter circuit 301 corresponds to the input terminal of the buffer circuit 123, and the output of the inverter circuit 301 is connected to the input of the inverter circuit 302 while being connected to the gate of the PMOS transistor 303. The output of the inverter circuit 302 is connected to the gate of the PMOS transistor 304. The source of the PMOS transistor 303 is connected to the power supply VDD, and its drain terminal is connected to the source of the PMOS transistor 304 and to the output terminal of the buffer circuit 123. The drain terminal of the PMOS transistor 304 is connected to the ground.

  FIG. 12 is a perspective view of a substrate unit of an optical print head in which the light emitting element / driving element composite chip is arranged on a printed wiring board. In FIG. 12, 401 is a printed wiring board, 402 is the IC chip (IC1 to IC26, etc.) shown in FIG. Reference numeral 404 denotes a bonding wire that connects each terminal of the driver IC (IC1 or the like) to a wiring pad (not shown) on the printed wiring board 401.

  FIG. 13 is a cross-sectional view schematically showing the configuration of the optical print head. As shown in FIG. 13, the optical print head 19 includes a base member 411, a printed wiring board 401 fixed by the base member 411, a rod lens array 412 in which a large number of columnar optical elements are arranged, a rod A holder 413 that holds the lens array 412 and clamp members 414 and 415 that fix the printed wiring board 401, the base member 411, and the holder 413 are configured. Reference numeral 402 denotes an IC chip on which the above-described drive circuit and the like are integrated. Reference numeral 403 denotes a light-emitting thyristor array arranged on the element.

  Next, the operation of the first embodiment will be described. FIG. 14 shows a time chart when a printing operation is performed using the optical print head having the configuration shown in FIG. Prior to the start of time-division driving of the light emitting element, the synchronization signal HD-HSYNC-N is input (A part). Next, in order to transfer drive data (Odd print data) of odd-numbered light emitting elements in the B section, data signals HD-DATA 3 to 0 are input in synchronization with the clock signal HD-CLK. In this optical print head, 26 driver ICs are connected in cascade, each IC has 96 LED drive terminals, and print data for 4 pixels is transferred at a time by one pulse clock signal. Is done. Therefore, the number of clock pulses necessary for one data transfer is (96/4) × 26 = 24 × 26 = 624.

  When transfer of odd-numbered dot data of one line data is completed in the B section, a latch signal HD-LOAD signal is input as shown in the C section, and a shift register composed of flip-flop circuits (FFA1 to FFD25) is installed. The data input via the latch is latched by the latch circuits (LTA1 to LTD24). At this time, the gate drive signal G1 of the light-emitting thyristor becomes Low level (L part), and the gate drive signal G2 becomes High level (N part). Next, a strobe signal HD-STB-N for instructing driving of the light emitting thyristor is input (D section). Accordingly, the DO1 to DO96 terminals of the driver IC (IC1 to IC26, etc.) are selectively turned on based on the command value by the print data, and the drive current is output (Q section).

The light emitting elements driven at this time are thyristor elements in which the G1 signal is connected to the gate terminal, such as 102 and 104 in FIG. For this reason, when a drive current flows from the DO1 terminal of the driver IC IC1, a current path is formed from the thyristor element 104 to the ground through the anode and cathode terminals of the thyristor element 104, while the thyristor 103 is a gate terminal. The level is high and is turned off, so that the drive current from the DO1 terminal of the driver IC IC1 does not flow and the light is kept off. As a result, the thyristor element 104 emits light (not shown in FIG. 1) to form an electrostatic latent image on the photosensitive drum, thereby generating printed dots. Next, when the negative logic strobe signal HD-STB-N becomes High level in the F section, the driving by the driver IC is turned off and all the thyristor elements are turned off (R section).

  Further, in order to transfer drive data (Even print data) of even-numbered LEDs in the E section, data signals HD-DATA 3 to 0 are input in synchronization with the clock signal HD-CLK. When the transfer of even-dot data out of one line data is completed in the E section, the latch signal HD-LOAD signal is input as shown in the G section, and the data input through the shift register is latched by the latch circuit. The At this time, the gate drive signal G1 of the light emitting thyristor becomes High level (M portion), and the gate drive signal G2 becomes Low level (O portion).

Next, a strobe signal HD-STB-N for instructing LED driving is input (H section). Accordingly, the DO1 to DO96 terminals of the driver IC (IC1 to IC26, etc.) are selectively turned on based on the command value by the print data, and the drive current is output (S section). The light emitting element driven at this time is a thyristor element in which the G2 signal is connected to the gate terminal, such as 101 and 103 in FIG.
For this reason, when a drive current flows out from the DO1 terminal of the driver IC IC1, a current path is formed from the thyristor element 103 to the ground through the anode and cathode terminals of the thyristor element 103, while the thyristor 104 has a gate terminal. The level is high and is turned off, so that the drive current from the DO1 terminal of the driver IC IC1 does not flow and the light is kept off.

  As a result, the thyristor element 103 emits light (not shown in FIG. 1) to form an electrostatic latent image on the photosensitive drum, thereby generating printed dots. Then, when the negative logic strobe signal HD-STB-N becomes High level in the J section, the driving by the driver IC is turned off and all the thyristor elements are turned off (T section). In this manner, the light emitting elements for one line can be driven by sequentially driving the odd-numbered elements and the even-numbered elements in the light-emitting element array in a time-sharing manner.

  FIG. 15 is a time chart showing the correction data transfer process performed on the optical print head having the configuration of the first embodiment after the printer is turned on, and the print data transfer operation performed thereafter. In FIG. 15, prior to the start of transfer of correction data, the HD-LOAD signal is set to High to indicate that the subsequent data transfer is correction data (part I). Next, among the odd-numbered dots, correction data consisting of 4 bits per dot, bit 3 data is input from HD-DATA 3 to 0 in synchronization with the clock HD-CLKI, and the flip-flop circuit (FFA1) of FIG. Shift input into a shift register composed of .about.FFD25). When the shift input is completed, three pulses of the HD-STB-N signal are input as shown in part A, and the operation of the circuit shown in FIG. 8 is performed.

  15, Q1 and Q2 are the Q outputs of the flip-flop circuits 221 and 222 shown in FIG. 8. Similarly, Q3 is the Q output of the flip-flop circuit 223, Q4 is the Q output of the flip-flop circuit 225, and Q5 is The Q output signal of the flip-flop circuit 224 is shown. E1 and E2 are outputs of the AND circuits 227 and 228, and signals W3 to W0 are output signals of the AND circuits 233 to 230. Further, the signals S1N and S2N are output from the buffer circuits 243 and 242 shown in FIG.

  In the A part of FIG. 15, when the first pulse of HD-STB-N is inputted, the Q1 signal is generated as shown in the J part, and then in the second part of the HD-STB-N, shown in the K part. Thus, the Q2 signal is generated. Each time the Q1 signal rises, the state of the Q3 signal is inverted, and the Q3 signal transitions to a high level as in the L part. Following the transition of the Q3 signal, the E1 and E2 signals are generated. Following the rising edge of the E1 signal, the Q4 signal rises like the M portion, the Q5 signal rises at the next rising edge of the E1 signal, the Q4 signal falls at the next rising edge of the E1 signal, and the next rising edge of the E1 signal. The Q5 signal falls.

  The W3 to W0 signals are generated following the Q2 signal, but the W3 signal is output twice as in the O part and P part, and then each of the W2, W1, and W0 signals also has two pulses. Generate a signal. Data is written to the memory circuit MEM2 in FIG. 4 every time the above-described pulse signals W3 to W0 are generated, and data is written to the memory elements for odd dots at the first pulse of W3 to W0. Data is written to the memory element for even dots in the second pulse. The data write command signal for the first pulse described above is generated based on the HD-STB-N signal input in the A part, the C part, the E part, and the G part. The data write command signal is generated based on the HD-STB-N signal input in the B part, D part, F part, and H part.

  When all the data writing of the correction data bit3 to bit0 is completed through the above-described process, the HD-LOAD signal is set to Low as in the Q section, and the print data can be transferred. At the start of printing one line, the HD-HSYNC-N signal is input to indicate that the subsequent data transfer is for odd dots (R section). Next, odd-dot print data is transferred in the U portion, and the data shifted in the shift registers (FFA1 to FFD1,..., FFA24 to FFD24) is latched by the HD-LOAD signal pulse in the S portion. LTD1, ..., LTA24-LTD24). Further, the HD-STB-N signal transitions to Low as in the W unit, and the LED element is driven to emit light. When the print data is on, the LED element is driven to emit light during the period when the HD-STB-N signal of the W section and the X section is low. Similarly, even-dot data transfer is performed in the V section, and the data is latched by pulses in the T section.

  As shown in FIG. 4, the S1N signal output from the CTRL2 block (116) becomes the G1 signal via the buffer circuit 123, and drives the gate terminal of the odd-numbered thyristor. The S2N signal output from the CTRL2 block (116) becomes the G2 signal via the buffer circuit 124, and drives the gate terminal of the even-numbered thyristor. Therefore, the gate drive signals G1 and G2 described above with reference to FIG. 14 can be generated.

  16 to 19 show detailed waveforms of correction data transfer when the driver IC is simplified to only one chip in the time chart shown in FIG. FIG. 16 shows details of the A part and the B part in FIG. FIG. 17 shows details of the C and D parts in FIG. FIG. 18 shows details of the E and F parts in FIG. FIG. 19 shows details of the G and H portions in FIG.

  Returning to FIG. 15, it is sufficient that the chip correction data set for each driver IC is performed once for either odd dot transfer (for example, A portion) or even dot transfer (for example, B portion). For this reason, in FIGS. 16 to 19, when the correction data of odd dots in the A part, C part, E part, and G part is transferred, the number of shift registers is switched to be increased by one, and chip correction is performed at the head of the transmission data string. Data (Chip-b3, Chip-b2, Chip-b1, Chip-b0, etc.) is assigned and transmitted.

  FIG. 20 illustrates the operation of the gate terminal driving buffer circuits 123 and 124 of the light emitting thyristor shown in FIG. FIG. 20A is a diagram showing an essential part of the buffer circuit 124 and the thyristor 101 connected thereto, and FIG. 20B shows the internal configuration of the buffer circuit 124 and the equivalent circuit of the thyristor 101. ing. In FIG. 20B, reference numeral 124 surrounded by a broken line is a buffer circuit, and reference numeral 101 surrounded by a broken line is a thyristor. Reference numerals 301 and 302 denote inverter circuits, 303 and 304 denote PMOS transistors, 141 denotes a PNP transistor, and 142 denotes an NPN transistor.

  Now, in FIG. 20A and FIG. 20B, it is assumed that the input of the buffer circuit 124 is at a low level in order to explain the turn-on process of the thyristor 101. At this time, the output of the inverter circuit 301 is at a high level, and the output of the inverter 302 is at a low level. As a result, the PMOS transistor 303 is in an off state and the PMOS transistor 304 is in an on state, and the source terminal level can be lowered to a potential approximately Vt potential higher than the ground potential. Note that Vt described above is a threshold voltage of the PMOS transistor.

  Next, a DO terminal output of a driver IC (not shown) is generated to drive the thyristor 101, and an anode current shown as Ia is generated. At this time, the current flows as a forward current through the PN junction between the anode and gate of the thyristor 101, that is, between the emitter and base of the PNP transistor 141, and generates a gate current shown as Ig. As a result of the above-described current flow, the potential described in the figure is generated at each terminal of the thyristor 101. In FIG. 20A, the anode terminal potential is Va and the gate terminal potential is Vg. In FIG. 20B, which also shows the inside of FIG. 20A, the gate current Ig corresponds to the base current Ib of the PNP transistor 141 inside the thyristor 101, and the gate current Ig flows through the gate current Ig. The PNP transistor 141 starts to be turned on, and a collector current is generated at the collector of the PNP transistor 141. The collector current becomes the base current of the NPN transistor 142 and shifts the NPN transistor 142 to the ON state.

  The collector current generated thereby enhances the base current Ib of the PNP transistor 141 and accelerates the transition of the PNP transistor 141 to the on state. On the other hand, after the NPN transistor 142 is completely turned on, the collector-emitter voltage decreases to a potential lower than the threshold voltage Vt of the PMOS transistor 304 described above. As a result, the current Ig flowing from the gate terminal of the thyristor 101 to the output terminal side of the buffer circuit 124 becomes substantially zero, and the cathode current Ik substantially equal to the anode current Ia flows to the cathode terminal of the thyristor 101. The thyristor 101 is completely turned on.

  FIG. 20C is a diagram for explaining the turn-on process of the thyristor 101 described above, in which the horizontal axis indicates the anode current Ia and the vertical axis indicates the anode terminal potential Va. When the thyristor 101 is turned off, the anode current is substantially zero and is at the origin (0, 0) of the graph. As the thyristor 101 is turned on, when the anode is driven, the anode potential rises and reaches the Vp potential as shown by the arrow in the figure. The voltage corresponds to the sum of the emitter-base voltage of the PNP transistor 141 and the Vt voltage, and when this voltage is applied in the forward direction, the gate current (this corresponds to the base current of the PNP transistor 141). Is equal).

  A point (Ip, Vp) indicated by a circle in FIG. 20C corresponds to a boundary between the off region (A) and the on transition region (B) of the thyristor 101. Next, as the anode current Ia increases, the anode potential Va decreases and reaches a point (Iv, Vv) indicated by a circle. This point corresponds to the boundary between the ON transition region (B) and the ON region (C) of the thyristor 101, and the gate current Ig at this time has dropped to substantially zero, and the buffer circuit 124 is substantially It is in a state equivalent to being disconnected from the thyristor 101. As the anode current Ia further increases, the anode potential Va increases and reaches a point (I1, V1) indicated by a circle. This point is the final operation point of light emission driving of the light emitting thyristor, and light emission driving is performed with a predetermined light emission power by a current value (I1) equal to the anode current Ia supplied from the driver IC side.

  Although the turn-on process of the thyristor has been described with reference to FIG. 20, by using the gate drive circuit indicated by 124, the gate current is prevented from flowing from the thyristor 101 in the on state, and the anode current Ia and the cathode current Ik are reduced. The on-state drive can be made substantially equal, and the light emission power can be obtained by adjusting the anode current Ia.

  Such an operation is due to the fact that the output stage of the buffer circuit 124 is configured as a push-pull drive circuit using a PMOS transistor, and when an NMOS transistor is used instead of the PMOS transistor 304 as in a normal CMOS output circuit. Therefore, the base current of the PNP transistor 141 continues to flow as Ig to the buffer circuit side, and the collector current of the NPN transistor 142 is reduced accordingly, and the thyristor is reduced. The cathode current Ik of 101 also decreases. As a result, the light emission output of the thyristor fluctuates and cannot be operated in a desired state, making it difficult to realize an optical print head using the light emitting thyristor.

 On the other hand, in the configuration using the gate drive buffer shown in FIG. 20, the above-described problems do not occur, and mounting of the power MOS transistors (41 and 42 in FIG. 32) that had to be provided in the conventional configuration is provided. An optical print head that can be dispensed with and saves space can be realized.

  FIG. 21 is a diagram for explaining the behavior when the elements sharing the gate wiring of the thyristor element are lit simultaneously in the configuration of FIG. In FIG. 21, two thyristor elements 101 and 103 are taken up to simplify the description, and other elements are omitted. FIG. 21A is a diagram showing a connection between the gate drive buffer 124 in FIG. 4 and the thyristors 101 and 103 shown in FIG. FIG. 21B is a diagram drawn in comparison with FIG. 21A, in which the thyristor elements 101 and 103 are surrounded by a broken line, and the internal equivalent circuit is shown as a PNP transistor 141 and an NPN transistor 142. . In FIG. 21A, the input level of the gate drive buffer 124 is set to Low in order to indicate the simultaneous ON state of the thyristors, and the gate wiring G connected to the output is connected to the gate terminals of the plurality of thyristors 101 and 103. Yes.

  FIG. 21B shows a situation in which a plurality of thyristor elements 101 and 103 are simultaneously turned on. As described with reference to FIG. 20, in the buffer circuit 124 using the configuration of the first embodiment, Because of the turn-on command, after the output level is set to Low and the thyristor element is turned on, the current flowing from the gate terminal of the element toward the output terminal of the buffer circuit 124 can be made substantially zero. For this reason, in FIG. 21B, the buffer circuit 124 connected to the gate wiring G is drawn with a broken line.

  Now, it is assumed that the thyristor 101 is on and a drive current Ia flows from its anode terminal. At this time, the current Ia is the sum of the three current components I1, I2, and I3. That is, the current I1 is a current indicated by a solid line arrow passing from the anode terminal to the ground through the base and emitter of the PNP transistor 142 through the emitter and collector of the PNP transistor 141. The current I2 is a current indicated by a broken-line arrow passing from the anode terminal through the emitter and base of the PNP transistor 141 to the ground through the collector and emitter of the NPN transistor 142. The current I3 passes from the anode terminal to the emitter and base of the PNP transistor 141, flows from the gate terminal of the thyristor 103 through the gate wiring G, and reaches the ground through the collector and emitter of the NPN transistor in the thyristor 103. This is the current indicated by the arrow.

In the thyristor set in the first embodiment, the light emission has a characteristic mainly due to the current flowing through the PNP transistor 141, and the light emission power (P) components (Pi1, Pi2, Pi3) of the currents I1, I2, and I3. ) In descending order of contribution to
Pi1 >> Pi2 >> Pi3
It becomes. For this reason, even if a part of the gate current of another thyristor that emits light at the same time flows through its own gate terminal as in the case of the current I3, the influence is slight. It is necessary to provide such characteristics. In a situation where it is difficult to provide such thyristor characteristics, it is necessary to further include configurations of Embodiments 2 and 3 of the present invention described below, and details thereof will be described later.

  As described above, in the configuration of the first embodiment, the light emitting thyristor is used instead of the two-terminal LED element as the light emitting element, and the gate terminal is driven by the push-pull drive buffer circuit using the PMOS transistor provided in the driver IC. The configuration is to be performed. As a result, a part of the anode current for driving the thyristor is used for the gate drive in the turn-on process of the thyristor, and the current flowing through the gate drive buffer disappears after the element is turned on. Was configured to be separated. Therefore, although the thyristor is a three-terminal element, it can be operated substantially in the same manner as a two-terminal LED, and can be operated in a form compatible with a conventional LED head. Further, it is not necessary to mount power MOS transistors (41 and 42 in FIG. 32) that are required in the conventional configuration, and an optical print head that saves space and is lower in cost than the LED head of the conventional configuration can be realized. It became.

  Next, Example 2 will be described. FIG. 22 is a diagram illustrating the structure of an optical print head according to the second embodiment. Also in the description of the present embodiment, as an example, an optical print head capable of printing on an A4 size paper at a resolution of 600 dots per inch will be taken and its specific configuration will be described. In this example, the total number of light emitting elements is 4992 dots, and 26 light emitting element arrays are arranged to constitute this, and each light emitting element array includes 192 light emitting elements, In each light emitting element, the cathode terminal is connected to the ground, and the anode terminals of two adjacent light emitting elements are connected to each other, and the odd-numbered light-emitting elements and the even-numbered light-emitting elements are driven in a time-sharing manner. Is done.

  In FIG. 22, CHP1 and CHP2 are light emitting element arrays, and descriptions of CHP3 to CHP26 are omitted. IC101 and IC102 are driver ICs arranged corresponding to CHP1 and CHP2, which are constituted by the same circuit and are connected in cascade with adjacent driver ICs. IC103 to IC1026 are not shown. 101 to 108 are light emitting thyristor elements, and 192 are arranged for each light emitting element array. The light emitting thyristor includes an anode that is a first terminal, a cathode that is a second terminal, and a gate that is a third terminal, and the anode terminal is connected to each of two adjacent light emitting thyristors, It is connected to each terminal of DO1 to DO96 of the driver IC. Each cathode terminal of the light emitting thyristor is connected to the ground.

  Further, the gate terminals of the odd-numbered light-emitting thyristors and the gate terminals of the even-numbered light-emitting thyristors in the light-emitting thyristor array are individually connected to the gate drive terminals G1 and G2 provided on the driver IC. For example, the anode terminals of the light emitting thyristor 101 and the light emitting thyristor 102 are connected to each other, connected to the DO 96 that is the anode driving terminal of the driver IC (IC1), the cathodes of the light emitting thyristor 101 and the light emitting thyristor 102 are connected to the ground, and The gate terminal of the light emitting thyristor 101 is connected to the G2 terminal arranged in the vicinity of the DO96 terminal of the driver IC, and the gate terminal of the light emitting thyristor 102 is connected to the G1 terminal arranged in the vicinity of the DO96 terminal of the driver IC. .

  The anode terminals of the light emitting thyristor 103 and the light emitting thyristor 104 are connected to each other, connected to DO1 which is an anode driving terminal of the driver IC (IC1), the cathodes of the light emitting thyristor 103 and the light emitting thyristor 104 are connected to the ground, and the light emitting thyristor. The gate terminal 103 is connected to the G2 terminal arranged near the DO1 terminal of the driver IC, and the gate terminal of the light emitting thyristor 104 is connected to the G1 terminal arranged near the DO1 terminal of the driver IC.

  In the configuration shown in FIG. 22, there are four print data signals, and among the eight adjacent light-emitting thyristors, data for four odd-numbered or even-numbered pixels can be sent simultaneously for each clock signal. . For this reason, the print data signals HD-DATA 3 to 0 output from the print control unit 1 are input to the optical print head 19 together with the clock signal HD-CLK, and the bit data for 4992 dots described above comprises a flip-flop circuit described later. The data is sequentially transferred through the shift register. Next, a latch signal HD-LOAD is input to the optical print head 19, and the bit data is latched by each latch circuit provided corresponding to the flip-flop circuit.

  Subsequently, the bit data and the print drive signal HD-STB-N turn on the light emitting elements corresponding to the dot data at the high (high) level. Note that VDD is a power supply, GND is a ground, and HD-HSYNC-N is a synchronization signal for setting an initial state as to whether it is odd-numbered LED driving or even-numbered LED driving in the time-division driving described above. , VREF is a reference voltage for instructing a drive current value for LED driving, and is generated by a reference voltage generation circuit (not shown) provided in the optical print head 19.

  FIG. 23 is a block diagram illustrating a detailed configuration of the driver IC according to the second embodiment. In FIG. 23, reference numeral 111 denotes a resistor, which is a pull-up element connected between the strobe terminal and the power supply VDD. 112 and 113 are inverter circuits, and 114 is a NAND circuit. FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flop circuits and constitute a shift register. LTA1 to LTD1 and LTA24 to LTD24 are latch elements, and they constitute a latch circuit as a whole. 117 is a MEM2 block, and 121 is a MEM block, each of which is a memory circuit, and includes correction data (dot correction data) for correcting variation in the amount of light of each light emitting element and light amount correction data (chip correction) for each light emitting element array chip. Data) or unique data for each driver IC.

  Reference numeral 118 denotes a MUX2 block, which is a multiplexer circuit. This circuit is provided to switch between the odd-numbered dot correction data and the even-numbered dot correction data among the adjacent light emitting element dots in the dot correction data output from the memory MEM2. The DRV block (119) is a light emitting element drive circuit, the SEL block 120 is a selector circuit, and the CTRL1 block (115) is a control circuit, and a write command signal for writing the correction data to the memories MEM2 and MEM ( E1, E2, W3 to W0). The CTRL2 block (116) is a control circuit, and generates a data switching command signal (S1N, S2N) between odd dot data and even dot data to the multiplexer MUX2. The data switching command signal (S1N, S2N) is also connected to the input terminals of the buffer circuits 501 and 502, and the output of the buffer circuit is connected to the G1 and G2 terminals of the driver IC via the individual buffer circuits 503 to 506. As shown in FIG. 22 described above, each light emitting element array is individually connected to the gate terminals of the light emitting thyristors 102 and 101.

  The ADJ block (122) is a control voltage generation circuit, which receives the reference voltage value VREF input from the VREF terminal and generates a control voltage for driving the light emitting element. Reference numerals 501 and 502 denote the above-described common buffer circuits, and reference numerals 503 to 506 denote individual buffer circuits in which output terminals are individually arranged in the vicinity of anode drive output terminals DO1 to DO96 described later.

The flip-flop circuits FFA1 to FFA25 are cascade-connected, the data input terminal D of FFA1 is connected to the data input terminal DATAI0 of the driver IC, the data outputs of FFA24 and FFA25 are input to the selector circuit SEL120, and the output of the selector circuit 120 The terminal Y0 is connected to the data output terminal DATAO0 of the driver IC. Similarly, flip-flop circuits FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals D of FFB1, FFC1, and FFD1 are connected to the data input terminals DATAI1, DATAI2, and DATAI3 of the driver IC, respectively. The outputs from FFB 24 and FFB 25, FFC 24 and FFC 25, FFD 24 and FFD 25 are also connected to the selector circuit SEL120, and the respective outputs Y1, Y2, and Y3 are connected to the data output terminals DATAO1, DATAO2, and DATAO3 of the driver IC, respectively. .

  Accordingly, the flip-flop circuits FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 each constitute a 25-stage shift register circuit, and the selector circuit 120 switches the number of shift stages between 24 and 25. be able to.

  The data output terminals DATAO0 to DATAO3 of the driver IC are respectively connected to the data input terminals DATAO0 to DATAI3 of the driver IC at the next stage. Therefore, with all the shift registers of the driver ICs IC1 to IC26, the data signal HD-DATA3 input from the print control unit 1 to the first-stage driver IC DRV1 is shifted in synchronization with the clock signal in 24 × 26 stages or 25 × 26 stages. A stage shift register circuit is configured. Similarly, the data signals HD-DATA2, HD-DATA1, and HD-DATA0 input from the print control unit 1 to the first stage driver IC IC1 are shifted in synchronization with the clock signal with all the shift registers of the driver ICs IC1 to IC26. Each of the 24 × 26 stage or 25 × 26 stage shift register circuits is configured.

  The latch circuits LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, and LTD1 to LTD24 are latched by a latch signal LOAD-P. The latch circuits LTA1 to LTA24 latch the data signal HD-DATA0 stored in the flip-flop circuits FFA1 to FFA24. Similarly, the latch circuits LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flop circuits FFB1 to FFB24. The latch circuits LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flop circuits FFC1 to FFC24. The latch circuits LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flop circuits FFD1 to FFD24. The NAND circuit 114 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the terminal LOAD via the inverter circuits 112 and 113, and outputs to the light emitting element driving unit DRV. A signal for controlling on / off of the drive is generated.

  FIG. 24 shows the configuration of the individual drive buffer circuits 503 to 506 of the gate terminal of the thyristor shown in FIG. FIG. 24A shows a circuit diagram symbol of the buffer circuit 503 as an example, and FIG. 24B shows its circuit configuration. In FIG. 24B, 511 and 512 are inverter circuits, and 513 and 514 are PMOS transistors. The input of the inverter circuit 511 corresponds to the input terminal of the buffer circuit 503, and the output of the inverter circuit 511 is connected to the input of the inverter circuit 512, and is also connected to the gate of the PMOS transistor 513. The output of the inverter circuit 512 is connected to the gate of the PMOS transistor 514. The source of the PMOS transistor 513 is connected to the power supply VDD, and its drain terminal is connected to the source of the PMOS transistor 514, while being connected to the output terminal of the buffer circuit 503. The drain terminal of the PMOS transistor 514 is connected to the ground.

  FIG. 25 shows another configuration of the individual drive buffer circuits 503 to 506 of the gate terminal of the thyristor shown in FIG. FIG. 25A is a circuit diagram symbol of the buffer circuit 503, and FIG. 25B shows its circuit configuration. In FIG. 25B, 511 is an inverter circuit, 513 is a PMOS transistor, 521 is a diode, and 522 is an NMOS transistor. The input of the inverter circuit 511 corresponds to the input terminal of the buffer circuit 503, and the output of the inverter circuit 511 is connected to the gate of the PMOS transistor 513 and the gate of the NMOS transistor 522. The source of the PMOS transistor 513 is connected to the power supply VDD, and the drain terminal is connected to the output terminal of the buffer circuit 503 and the anode terminal of the diode 521. The cathode terminal of the diode 521 is connected to the drain terminal of the NMOS transistor 522, and the source terminal of the NMOS transistor 522 is connected to the ground. The circuit shown in FIG. 25 can perform the same operation as the circuit shown in FIG. 24. The difference in characteristics is the difference between the threshold voltage Vt of the PMOS transistor 514 in FIG. 24 and the forward voltage Vf of the diode in FIG. This is due to

  Next, the operation of the second embodiment will be described. FIG. 26 illustrates the operation of the gate terminal driving buffer circuits 503 to 506 of the light emitting thyristor shown in FIG. FIG. 26 (a) is a diagram showing extracted main portions of the buffer circuits 503 and 505 and the thyristors 101 and 103 connected thereto, and the description of other buffer circuits and thyristor elements is omitted for the sake of simplicity. ing. FIG. 26B also shows an internal configuration of the buffer circuits 503 and 505 and an equivalent circuit of the thyristors 101 and 103. In FIG. 26B, reference numerals 503 and 505 indicated by broken lines are buffer circuits, and reference numerals 101 and 103 indicated by broken lines are thyristors.

  In FIG. 26B, 511a, 512a, 511b and 512b are inverter circuits, 513a, 514a, 513b and 514b are PMOS transistors, 141a and 141b are PNP transistors, and 142a and 142b are NPN transistors. Now, in FIG. 26A, in order to explain the turn-on process of the thyristor 101, it is assumed that the input of the buffer circuit 503 is at the low level. At this time, the output of the inverter circuit 511a is at a high level, and the output of the inverter 512a is at a low level. As a result, the PMOS transistor 513a is in an off state and the PMOS transistor 514a is in an on state, so that the source terminal level can be lowered to a potential approximately Vt potential higher than the ground potential. Note that Vt described above is a threshold voltage of the PMOS transistor.

  Next, it is assumed that an output is generated at the DO terminal of a driver IC (not shown) to drive the thyristor 101, and an anode current shown as Ia1 is generated. At this time, the anode current flows as a forward current to the PN junction between the anode and the gate of the thyristor 101 to generate a gate current. As a result of the above-described current flow, a gate potential is generated at the gate terminal of the thyristor 101. The buffer circuit 505 and the thyristor 103 have the same configuration as described above, and each performs the same operation.

  In FIG. 26 (b), the gate current Ig corresponds to the base current of the PNP transistor 141a in the thyristor 101, and when this current flows, the PNP transistor 141a starts to be turned on. A collector current is generated at the collector of the element. The collector current becomes the base current of the NPN transistor 142a and shifts the NPN transistor 142a to the on state. The collector current thus generated enhances the base current of the PNP transistor 141a and accelerates the transition of the PNP transistor 141a to the on state.

  On the other hand, after the NPN transistor 142a is completely turned on, the collector-emitter voltage decreases to a potential lower than the threshold voltage Vt of the PMOS transistor 514a described above. As a result, the gate current flowing from the gate terminal of the thyristor 101 toward the output terminal of the buffer circuit 503 becomes substantially zero, and the cathode current Ik substantially equal to the anode current Ia flows through the cathode terminal of the thyristor 101. The thyristor 101 is completely turned on. As is apparent with reference to FIG. 26, the gate terminals of the thyristors 101 and 103 are individually provided with gate drive buffer circuits 503 and 505, etc. Since they are not directly connected, no current component flows between the gate terminals.

In the thyristor set in the first embodiment, as described with reference to FIG. 21, the light emission has characteristics mainly due to the current flowing in the PNP transistor 141, and the light emission power (P) component (Pi1) for each current. , Pi2, Pi3) in descending order of contribution to
Pi1 >> Pi2 >> Pi3
It was necessary to become. For this reason, even if a part of the gate current of another thyristor that emits light at the same time flows in through its own gate terminal like the current I3, the effect of minimizing the influence is provided. It was necessary to let them. On the other hand, in the configuration of the second embodiment, since the gate terminals of the thyristors that are turned on simultaneously are not directly connected, no current component flows between the terminals, so that it is not necessary to provide the above-described conditions.

  Thus, in the configuration of the second embodiment, similarly to the first embodiment, it is not necessary to mount the power MOS transistors (41 and 42 in FIG. 32) that had to be provided in the conventional configuration. LED can be realized as a head, and in addition to that, it is possible to eliminate the characteristic restrictions on the thyristor that had to be provided in the configuration of the first embodiment, and further improvements have been made.

  That is, in the second embodiment, as described with reference to FIG. 24, a light-emitting thyristor is used instead of a two-terminal LED element as a light-emitting element, and the gate terminal is driven by a push-pull transistor provided in a driver IC. The driving buffer circuit is used. As a result, a part of the anode current for driving the thyristor is used for the gate drive in the turn-on process of the thyristor, and the current flowing through the gate drive buffer disappears after the element is turned on. Was configured to be separated. Therefore, although the thyristor is a three-terminal element, it can be operated substantially in the same manner as a two-terminal LED, and can be operated in a form compatible with a conventional LED head. This eliminates the need for mounting power MOS transistors (41 and 42 in FIG. 32) that are required in the conventional configuration, and realizes a space-saving and low-cost optical print head compared to the LED head of the conventional configuration. It became so.

  Next, Example 3 will be described. In the configuration of the third embodiment, instead of the individual buffer circuit used in the configuration of the second embodiment, an individual circuit having a diode reverse connection configuration is provided. Therefore, since the configuration diagram of the optical print head in the third embodiment is the same as the configuration diagram in the second embodiment (FIG. 22), the description thereof is omitted, and the configuration of the driver ICs (IC1 to IC26) used in the configuration in FIG. State. FIG. 27 is a block diagram illustrating a detailed configuration of the driver IC according to the third embodiment.

  In FIG. 27, reference numeral 111 denotes a resistor, which is a pull-up element connected between the strobe terminal and the power supply VDD. 112 and 113 are inverter circuits, and 114 is a NAND circuit. FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are flip-flop circuits and constitute a shift register. LTA1 to LTD1 and LTA24 to LTD24 are latch elements, and they constitute a latch circuit as a whole. 117 is a MEM2 block, and 121 is a MEM block, each of which is a memory circuit, and includes correction data (dot correction data) for correcting variation in the amount of light of each light emitting element and light amount correction data (chip correction) for each light emitting element array chip. Data) or unique data for each driver IC. Reference numeral 118 denotes a MUX2 block, which is a multiplexer circuit. This circuit is provided to switch between the odd-numbered dot correction data and the even-numbered dot correction data among the adjacent light emitting element dots in the dot correction data output from the memory MEM2.

  The DRV block (119) is a light emitting element drive circuit, the SEL block 120 is a selector circuit, and the CTRL1 block (115) is a control circuit, and a write command signal for writing the correction data to the memories MEM2 and MEM ( E1, E2, W3 to W0). The CTRL2 block (116) is a control circuit, and generates a data switching command signal (S1N, S2N) between odd dot data and even dot data to the multiplexer MUX2. The data switching command signals (S1N, S2N) are also connected to the input terminals of the buffer circuits 501 and 502, and the output of the buffer circuit is connected to the G1 and G2 terminals of the driver IC through the individual circuits described later, as described above. As shown in FIG. 22, each light emitting element array is individually connected to the gate terminal of the light emitting thyristor 102 or 101.

  The ADJ block (122) is a control voltage generation circuit, which receives the reference voltage value VREF input from the VREF terminal and generates a control voltage for driving the light emitting element. Reference numerals 501 and 502 denote common buffer circuits, and reference numerals 541 to 544 denote individual circuits (to be described later) in which output terminals are individually arranged in the vicinity of the anode drive output terminals DO1 to DO96, respectively. The flip-flop circuits FFA1 to FFA25 are cascade-connected, the data input terminal D of FFA1 is connected to the data input terminal DATAI0 of the driver IC, the data outputs of FFA24 and FFA25 are input to the selector circuit SEL, and the output terminal Y0 is It is connected to the data output terminal DATAO0 of the driver IC.

  Similarly, flip-flop circuits FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 are also cascade-connected, and the data input terminals D of FFB1, FFC1, and FFD1 are connected to the data input terminals DATAI1, DATAI2, and DATAI3 of the driver IC, respectively. The outputs from FFB 24 and FFB 25, FFC 24 and FFC 25, FFD 24 and FFD 25 are also connected to the selector circuit SEL, and each output is connected to data output terminals DATAO1, DATAO2, and DATAO3 of the driver IC. Accordingly, the flip-flop circuits FFA1 to FFA25, FFB1 to FFB25, FFC1 to FFC25, and FFD1 to FFD25 each constitute a 25-stage shift register circuit, and the selector circuit 120 switches the number of shift stages between 24 and 25. be able to.

  The data output terminals DATAO0 to DATAO3 of the driver IC are respectively connected to the data input terminals DATAO0 to DATAI3 of the driver IC at the next stage. Therefore, with all the shift registers of the driver ICs IC1 to IC26, the data signal HD-DATA3 input from the print control unit 1 to the first-stage driver IC DRV1 is shifted in synchronization with the clock signal in 24 × 26 stages or 25 × 26 stages. A stage shift register circuit is configured. Similarly, the data signals HD-DATA2, HD-DATA1, and HD-DATA0 input from the print control unit 1 to the first stage driver IC IC1 are shifted in synchronization with the clock signal with all the shift registers of the driver ICs IC1 to IC26. Each of the 24 × 26 stage or 25 × 26 stage shift register circuits is configured.

  The latch circuits LTA1 to LTA24, LTB1 to LTB24, LTC1 to LTC24, and LTD1 to LTD24 are latched by a latch signal LOAD-P. The latch circuits LTA1 to LTA24 latch the data signal HD-DATA0 stored in the flip-flop circuits FFA1 to FFA24. Similarly, the latch circuits LTB1 to LTB24 latch the data signal HD-DATA1 stored in the flip-flop circuits FFB1 to FFB24. LTC1 to LTC24 latch the data signal HD-DATA2 stored in the flip-flop circuits FFC1 to FFC24. LTD1 to LTD24 latch the data signal HD-DATA3 stored in the flip-flop circuits FFD1 to FFD24. The NAND circuit 114 receives the strobe signal HD-STB-N input to the terminal STB and the latch signal LOAD-P input from the terminal LOAD via the inverter circuits 112 and 113, and outputs to the light emitting element driving unit DRV. A signal for controlling on / off of the drive is generated.

  FIG. 28 shows the configuration of individual circuits 541 to 544 for driving the gate terminal of the thyristor shown in FIG. FIG. 28A is a circuit diagram symbol of the individual circuit 541, and FIG. 28B shows its circuit configuration. 28B, diodes 551 and 552 are diodes, the anode of the diode 551 is connected to the cathode of the diode 552, the cathode of the diode 551 is connected to the anode of the diode 552, and so on. Are connected in parallel in opposite directions, and the two connection nodes serve as first and second terminals of the individual circuit of FIG.

  In the circuit having the configuration shown in FIG. 28B, when the forward voltage of the diodes 551 and 552 is Vf, the two diodes are connected in opposite directions, so that the individual circuit shown in FIG. When a voltage is applied between the first and second terminals, regardless of whether the voltage is positive or negative, when a voltage higher than the Vf voltage is applied as an absolute value, one of the diodes 551 and 552 is applied. When a forward voltage is applied to the diode, a forward current is generated in the element. As a result, the individual circuit 541 has a function of transmitting a current when a voltage equal to or higher than the Vf voltage is applied as an absolute value. Thereby, in the individual circuit of FIG. 28, both the high level and low level logic states can be transmitted to the gate terminal of the thyristor described above.

Next, the operation of the third embodiment will be described. FIG. 29 illustrates the operation of the individual circuits 541 to 544 for driving the gate terminal of the light emitting thyristor shown in FIG. FIG. 29 (a) is a diagram showing an essential part of the individual circuit 541 and the thyristor 101 connected thereto, and FIG. 29 (b) shows an internal configuration of the individual circuit 541 and an equivalent circuit of the thyristor 101. . In FIG. 29B, 541 indicated by a broken line is an individual circuit, and 101 indicated by a broken line is a thyristor. In FIG. 29B, 501 is the common buffer circuit described in FIG. 28, 551 and 552 are diodes, 141 is a PNP transistor, and 142 is an NPN transistor. Further, the forward voltage of the diodes 551 and 552 is represented by Vf, the base current of the PNP transistor 141 is denoted by Ib, the gate current of the thyristor 101 is denoted by Ig, the terminal voltage is denoted by Vg, and the cathode current is denoted by Ik.

  Now, in FIG. 29A, in order to explain the turn-on process of the thyristor 101, it is assumed that the input of the buffer circuit 501 is at a low level. Next, a DO terminal output of a driver IC (not shown) is generated to drive the thyristor 101, and an anode current shown as Ia is generated. At this time, the output of the buffer circuit 501 becomes a low level, the current Ia injected from the anode terminal of the thyristor 101 flows as Ib between the emitter and base of the PNP transistor 141, and further, as the gate current Ig of the thyristor, of the individual circuit 541 The current flows through the diode 552 and flows into the output terminal of the buffer circuit 501. At this time, since the forward voltage of the diode 552 is Vf, even if the output terminal potential of the buffer circuit 501 is substantially zero, the gate potential Vg of the thyristor 101 is substantially equal to the forward voltage Vf described above.

  In FIG. 29 (b), the gate current Ig corresponds to the base current Ib of the PNP transistor 141 in the thyristor 101, and the PNP transistor 141 starts to shift to the ON state when the current flows. Thus, a collector current is generated at the collector of the element. The collector current becomes the base current of the NPN transistor 142 and shifts the NPN transistor 142 to the ON state. The collector current generated thereby enhances the base current Ib of the PNP transistor 141 and accelerates the transition of the PNP transistor 141 to the on state. On the other hand, after the NPN transistor 142 is completely turned on, the collector-emitter voltage decreases to a potential smaller than the forward voltage of the diode 552 described above. As a result, the current Ig flowing from the gate terminal of the thyristor 101 to the output terminal of the individual circuit 541 becomes substantially zero, and the cathode current Ik substantially equal to the anode current Ia flows to the cathode terminal of the thyristor 101. The thyristor 101 is completely turned on.

FIG. 29C is a diagram for explaining the turn-on process of the thyristor 101 described above, in which the horizontal axis indicates the anode current Ia and the vertical axis indicates the anode terminal potential Va. In the light-off state of the thyristor, the anode current is substantially zero and is in the state of the origin (0, 0) of the graph.
As the thyristor is turned on, when the anode is driven, the anode potential rises and reaches the Vp potential as shown by the arrow in the figure. This voltage corresponds to the added value of the forward voltage Vf of the diode 552 and the emitter-base voltage of the PNP transistor 141, and is applied in the forward direction to apply a gate current (this corresponds to the base current of 141). Is equal).

  A point (Ip, Vp) indicated by a circle in FIG. 29C corresponds to the boundary between the off region (A) and the on transition region (B) of the thyristor 101. Next, as the anode current Ia increases, the anode potential Va decreases and reaches a point (Iv, Vv) indicated by a circle. This point corresponds to the boundary between the ON transition region (B) and the ON region (C) of the thyristor. At this time, the gate current Ig is reduced to substantially zero, and the individual circuit 541 substantially becomes the thyristor. The state is equivalent to being disconnected from 101. As the anode current Ia further increases, the anode potential Va increases and reaches a point (I1, V1) indicated by a circle. This point is the final operation point of the light emission drive of the light emitting thyristor, and is equal to the anode current Ia supplied from the driver IC side, and the light emission drive is performed with a predetermined light emission power corresponding thereto.

  Although the turn-on process of the thyristor has been described with reference to FIG. 29, the use of the individual circuit 541 prevents the gate current from flowing from the thyristor in the on state, and the on state in which the anode current Ia and the cathode current Ik are substantially equal. Driving can be performed, and light emission power corresponding to the anode current Ia can be obtained by adjusting the anode current Ia.

  Such an operation is the effect of interposing an individual circuit 541 between the output of the buffer circuit 501 and the gate terminal of the thyristor. When the normal CMOS output circuit and the gate terminal of the thyristor are directly connected, Since the low level output drops to approximately 0 V potential, the base current of the PNP transistor 141 continues to flow as Ig to the CMOS buffer circuit 501, and the collector current of the NPN transistor 142 is reduced accordingly, and the thyristor of the thyristor is reduced. The cathode current Ik is also reduced. As a result, the light emission output of the thyristor fluctuates and cannot be operated in a desired state, making it difficult to realize an LED head using the light emitting thyristor. In contrast, in the configuration using the gate drive buffer shown in FIG. 29, the above-mentioned problems do not occur, and it is not necessary to mount power MOS transistors (41 and 42 in FIG. 32) that had to be provided in the conventional configuration. As a result, a space-saving and low-cost LED can be realized.

  FIG. 30 is a diagram for explaining the behavior when the thyristor elements are turned on simultaneously in the configuration of FIG. In FIG. 30, two thyristor elements 101 and 103 are taken up to simplify the description, and other elements are omitted. FIG. 30A is a diagram showing a connection between the gate drive individual circuits 541 to 544 in FIG. 27 and the thyristors 101 and 103 shown in FIG. FIG. 30B is a diagram drawn in contrast to FIG. 30A, in which the individual circuits 541 and 543 are surrounded by broken lines, and the diodes inside the individual circuits are shown as 551a, 552a, 551b, and 552b. . The thyristor elements 101 and 103 are surrounded by a broken line, and their internal equivalent circuits are indicated as a PNP transistor 141 and an NPN transistor 142. Further, the collector-emitter voltage of the NPN transistor 142a is denoted as Vce1, and the collector-emitter voltage of the NPN transistor 142b is denoted as Vce3.

  In FIG. 30A, the input level of the gate drive buffer 501 is set to Low in order to indicate the simultaneous ON state of the thyristors. They are connected via 541 and 542, respectively. FIG. 30B shows a situation where a plurality of thyristor elements 101 and 103 are simultaneously turned on. As described with reference to FIG. 29, in the buffer circuit 501 using the configuration of the third embodiment, Because the thyristor is turned on, the current flowing from the gate terminal of the element toward the output terminal of the buffer circuit 501 after the thyristor element is turned on with its output level set to Low can be made substantially zero. Therefore, in FIG. 30B, the influence of the buffer circuit 501 connected to the gate wiring G can be excluded, and in FIG. 30B, the buffer 501 is indicated by a broken line.

Now, it is assumed that the thyristor 101 is on and a drive current Ia1 flows from its anode terminal. At this time, a path indicated by a broken-line arrow is considered as a path through which the gate current Ig of the thyristor 101 flows. Assuming that the gate current Ig flows, the current passes between the emitter and base of the PNP transistor 141a, passes through the diode 552a in the individual circuit 541 in the forward direction, and passes through the common gate line G to another individual gate. It passes through the diode 551b in the circuit 543 in the forward direction, and flows out to the ground via the collector-emitter of the NPN transistor 142b. Therefore, the potential Vg integrated from the gate terminal of the thyristor 101 when viewed from the outflow side of the gate current Ig is Vg = 2 × Vf + Vce3.
It becomes.

  However, the collector-emitter voltage Vce1 of the NPN transistor 142a in the thyristor 101 is sufficiently smaller than the calculated value of the Vg voltage. It becomes the collector current of the NPN transistor 142a and merges as its own cathode current Ik. As apparent from FIG. 27 and FIG. 30, in the thyristors 101 and 103 that are turned on at the same time, their gate terminals are connected to the buffer circuits 501 and 502 via the individual circuits 541 to 544 and the like. Since the gate terminals 101 and 103 are not directly connected, no current component flows between the gate terminals.

In the thyristor set in the first embodiment, as described with reference to FIG. 21, the light emission has characteristics mainly due to the respective currents I1 to I3 flowing in the PNP transistor 141, and the light emission power (P) for each current. Are listed in descending order of contribution to components (Pi1, Pi2, Pi3) of
Pi1 >> Pi2 >> Pi3
It was necessary to become. For this reason, even if a part of the gate current of another thyristor that emits light at the same time flows in through its own gate terminal like the current I3, the effect of minimizing the influence is provided. It was necessary to let them. On the other hand, in the configuration of the third embodiment, the gate terminals of the thyristors that are turned on at the same time are connected to the common gate wiring through the individual circuits, and the gates of the thyristors are connected by the functions of the individual circuits. The flowing current component is not generated, and it is not necessary to provide the above-described conditions.

  As described above, in the configuration of the third embodiment, similarly to the first embodiment, it is not necessary to mount the power MOS transistors (41 and 42 in FIG. 32) that are required in the conventional configuration, and the space is saved and the cost is low. An LED head can be realized. In addition to this, it is possible to eliminate the characteristic restrictions on the thyristor that had to be provided in the configuration of the first embodiment, and further improvement was achieved.

  That is, in the third embodiment, as described with reference to FIG. 29, a light emitting thyristor is used instead of a two-terminal LED element as a light emitting element, and the gate terminal is driven in a driver IC and connected thereto. The common gate wiring thus formed and the connection between the common wiring and the gate terminal of the thyristor are made through an individual circuit. Accordingly, a part of the anode current for driving the thyristor is used for the gate drive in the turn-on process of the thyristor, and the current flowing through the gate drive buffer disappears after the element is turned on, so that the buffer is substantially It was set as the structure separated by. Therefore, although the thyristor is a three-terminal element, it can be operated substantially in the same manner as a two-terminal LED, and can be operated in a form compatible with a conventional LED head. This eliminates the need for mounting power MOS transistors (41 and 42 in FIG. 32) that are required in the conventional configuration, and realizes a space-saving and low-cost optical print head compared to the LED head of the conventional configuration. It came to be.

  The light-emitting element arrays described in Embodiments 1 to 3 can be used as a light source in an exposure process in an electrophotographic printer. Hereinafter, a tandem color printer will be taken as an example and will be described with reference to FIG. FIG. 31 is a schematic configuration diagram showing a tandem color printer using a thyristor head equipped with the semiconductor composite device of the present invention.

  In FIG. 31, a tandem color printer 600 has four process units 601 to 604 for forming images of each color of black (K), yellow (Y), magenta (M), and cyan (C). Are arranged in order from the upstream side of the conveyance path of the recording medium 605. Since the internal configurations of these process units 601 to 604 are common, the internal configuration will be described by taking the magenta process unit 603 as an example.

  In the process unit 603, a photosensitive drum 603a as an image carrier is rotatably arranged in the direction of the arrow. Around the photosensitive drum 603a, the surface of the photosensitive drum 603a is sequentially arranged from the upstream side in the rotation direction. A charging device 603b for supplying and charging an electric charge, and an exposure device 603c for selectively irradiating the surface of the charged photosensitive drum 603a to form an electrostatic latent image are provided. The optical print head (19) described in each embodiment is used. Further, a developing device 603d that generates magenta (predetermined color) toner on the surface of the photosensitive drum 603a on which the electrostatic latent image is formed, and a visible image of the toner on the photosensitive drum 603a. A cleaning device 603e is provided to remove toner remaining after the transfer. The drums or rollers used in these devices rotate by receiving power from a drive source (not shown) via gears.

  In the tandem color printer 600, a paper cassette 606 for storing a recording medium 605 such as paper is stored in a lower part thereof, and a hopping for separating and transporting the recording medium 605 one by one is provided above the paper cassette 606. A roller 607 is provided. Further, on the downstream side of the hopping roller 607 in the conveyance direction of the recording medium 605, the recording medium 605 is nipped together with the pinch roller 608, and the recording medium 605 is nipped together with the pinch roller 609. The registration roller 611 that corrects the skew of the recording medium 605 and conveys it to the process unit 601 is disposed. The hopping roller 607, the transport roller 610, and the registration roller 611 are rotated by power transmitted from a driving source (not shown) via a gear or the like.

  Transfer rollers 612 are formed of semiconductive rubber or the like at positions facing the respective photosensitive drums of the process units 601 to 604, and transfer a visible image of the toner attached on the photosensitive drum 603a to the recording medium 605. Is arranged. These transfer rollers 612 have a potential difference between the surface potentials of the photosensitive drums 601a to 604a and the surface potentials of the respective transfer rollers 612 at the time of transferring the visible image by the toner on the photosensitive drum 603a to the recording medium 605. A potential is applied.

  The fixing device 613 includes a heating roller and a backup roller, and fixes the toner transferred on the recording medium 605 by pressurizing and heating. The discharge rollers 614 and 615 disposed on the downstream side of the fixing device 613 sandwich the recording medium 605 discharged from the fixing device 613 together with the pinch rollers 616 and 617 of the discharge unit and convey the recording medium 605 to the recording medium stacker unit 618. . The fixing device 613, the discharge roller 614, and the like are rotated by transmission of power from a drive source (not shown) via gears.

  Next, the operation of the tandem color printer 600 having the above configuration will be described. First, the recording medium 605 stored in a stacked state in the paper cassette 606 is separated and transported one by one from the top by the hopping roller 607. Subsequently, the recording medium 605 is sandwiched between the conveyance roller 610, the pinch roller 608, the registration roller 611, and the pinch roller 609, and is conveyed between the photosensitive drum 601a of the yellow process unit 601 and the transfer roller 612. After that, the recording medium 605 is sandwiched between the photosensitive drum 601a and the transfer roller 612, and a toner image is transferred to the recording surface thereof, and at the same time, the recording medium 605 is conveyed further downstream by the rotation of the photosensitive drum 601a.

  Similarly, the recording medium 605 sequentially passes through the process units 602 to 604, and in the passing process, the toner of each color obtained by developing the electrostatic latent images formed by the exposure devices 601c to 604c by the developing devices 601d to 604d. Images are sequentially transferred onto the recording surface and superimposed. Then, after the toner images of the respective colors are superimposed on the recording surface, the toner image is fixed by the fixing device 613, and the recording medium 605 after fixing is a discharge roller 614 and a pinch roller 616, and a discharge roller 615 and a pinch roller 617. And is discharged to a recording medium stacker unit 618 outside the tandem color printer 600. Through the above process, a color image is formed on the recording medium 605.

  As described above, according to the image forming apparatus of the present invention, since the optical print head having the light emitting thyristor is employed as the light emitting element, a high quality image forming apparatus (printer, copier) having excellent space efficiency and light extraction efficiency. Etc.) can be provided. That is, by using the optical print heads of the first to third embodiments, the effect can be obtained not only in the above-described full-color image forming apparatus but also in a monochrome or multi-color image forming apparatus. Greater effects can be obtained in the required full-color image forming apparatus.

  As described above, the case where the light-emitting thyristor used as the light source is used has been described in each of the above embodiments. However, the present invention is not limited to other elements connected in series to the switching element, such as an organic EL element or a heating resistor. The present invention is also applicable when performing voltage application control to the body. For example, it can be used in a printer provided with an organic EL head constituted by an array of organic EL elements or a thermal printer constituted by a row of heating resistors. Furthermore, the present invention can also be applied to a thyristor used as a switching element for driving display elements, for example, display elements arranged in rows or matrices (control of voltage application). The present invention can also be applied to a thyristor having a three-terminal structure and a four-terminal thyristor SCS (Silicon) Semiconductor Controlled Switch having first and second gate terminals.

1 is a block diagram showing an electrophotographic printer according to the present invention. 2 is a circuit diagram illustrating a structure of an optical print head according to Embodiment 1. FIG. 1 is a diagram illustrating a configuration of a light-emitting thyristor according to Example 1. FIG. FIG. 3 is a block diagram illustrating a detailed configuration of a driver IC according to the first embodiment. It is a circuit block diagram of memory circuit MEM2. It is a circuit block diagram which shows a multiplexer circuit. It is a circuit block diagram which shows a light emitting element drive circuit. It is a circuit diagram which shows the structure of control circuit CTRL1. It is a circuit diagram which shows the structure of control circuit CTRL2. It is a circuit diagram which shows a control voltage generation circuit. It is a circuit diagram which shows the buffer circuit for a drive of the gate terminal of a thyristor. It is a perspective view of the board | substrate unit of an optical print head. It is sectional drawing which shows the structure of an optical print head roughly. It is a time chart which shows the printing operation in an optical print head. 6 is a time chart illustrating an operation of correction data transfer processing and print data transfer. It is a time chart which shows the detailed waveform of correction data transfer. It is a time chart which shows the detailed waveform of correction data transfer. It is a time chart which shows the detailed waveform of correction data transfer. It is a time chart which shows the detailed waveform of correction data transfer. It is a figure explaining operation | movement of the buffer circuit for gate terminal drive of a light emitting thyristor. It is a figure explaining the behavior when a thyristor element lights up simultaneously. 6 is a diagram illustrating a structure of an optical print head according to Embodiment 2. FIG. FIG. 10 is a block diagram illustrating a detailed configuration of a driver IC according to a second embodiment. It is a circuit diagram which shows the structure of the buffer circuit for individual drive of the gate terminal of a thyristor. FIG. 5 is a circuit diagram showing another configuration of the individual drive buffer circuit for the gate terminal of the thyristor. It is a circuit diagram explaining the operation of the buffer circuit for driving the gate terminal of the light emitting thyristor. FIG. 10 is a block diagram illustrating a detailed configuration of a driver IC according to a third embodiment. FIG. 6 is a circuit diagram illustrating an individual circuit according to a third embodiment. It is a figure explaining operation | movement of the separate circuit for the gate terminal drive of a light emitting thyristor. It is a figure explaining the behavior when a thyristor element lights up simultaneously. It is a schematic block diagram which shows a tandem color printer. It is a circuit diagram which shows the optical print head using the conventional general LED.

19 Optical Print Heads 101 to 108 Light Emitting Thyristor 115 Control Circuit 116 Control Circuit 117 Memory Circuit 118 Multiplexer Circuit 119 Drive Circuit 121 Memory Circuit 122 Control Voltage Generation Circuits 123 and 124 Buffer Circuits 501 and 502 Common Buffer Circuits 503 to 506 Individual Buffer Circuits 541 ~ 544 Individual circuit

Claims (4)

A first terminal; a second terminal; and a control terminal for controlling electrical continuity between the first terminal and the second terminal, wherein the control terminal is provided between the first terminal and the second terminal. A plurality of light emitting elements that emit light when an electric current flows;
A drive circuit that is provided corresponding to at least two light emitting elements among the plurality of light emitting elements , and emits light by passing a current between the first terminal and the second terminal of the light emitting element;
Bi-directionally generating a voltage drop in both directions , comprising a pair of diodes provided corresponding to each of the plurality of light-emitting elements, one end of which is connected to the control terminal of the light-emitting element and reversely connected to each other A voltage drop generation circuit;
A common bus connecting the other ends of the plurality of bidirectional voltage drop generation circuits in common;
An optical print head comprising: a buffer circuit that outputs a control signal to be supplied to a control terminal of the light emitting element with respect to the common bus. The optical print head according to claim 1, wherein the buffer circuit is provided for each of the driving circuits . A first terminal; a second terminal; and a control terminal for controlling electrical continuity between the first terminal and the second terminal, wherein the control terminal is provided between the first terminal and the second terminal. A plurality of light emitting elements that emit light when an electric current flows;
A drive circuit that is provided corresponding to at least two light emitting elements among the plurality of light emitting elements , and emits light by passing a current between the first terminal and the second terminal of the light emitting element;
Bi-directionally generating a voltage drop in both directions , comprising a pair of diodes provided corresponding to each of the plurality of light-emitting elements, one end of which is connected to the control terminal of the light-emitting element and reversely connected to each other A voltage drop generation circuit;
The plurality of light emitting elements are divided into a plurality of groups, provided corresponding to each group, and connected to the control terminals of the plurality of light emitting elements to which the group belongs. A common bus connecting the other ends in common;
An optical print head comprising: a buffer circuit that outputs a control signal to be supplied to a control terminal of the light emitting element.   An image forming apparatus comprising the optical print head according to claim 1, wherein the light emitting element of the optical print head emits light to form an image.

Images