JPH0353660B2 - - Google Patents
Info
- Publication number
- JPH0353660B2 JPH0353660B2 JP59044022A JP4402284A JPH0353660B2 JP H0353660 B2 JPH0353660 B2 JP H0353660B2 JP 59044022 A JP59044022 A JP 59044022A JP 4402284 A JP4402284 A JP 4402284A JP H0353660 B2 JPH0353660 B2 JP H0353660B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- request
- buffer memory
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59044022A JPS60189553A (ja) | 1984-03-09 | 1984-03-09 | バッファメモリ制御方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59044022A JPS60189553A (ja) | 1984-03-09 | 1984-03-09 | バッファメモリ制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60189553A JPS60189553A (ja) | 1985-09-27 |
JPH0353660B2 true JPH0353660B2 (de) | 1991-08-15 |
Family
ID=12680034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59044022A Granted JPS60189553A (ja) | 1984-03-09 | 1984-03-09 | バッファメモリ制御方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60189553A (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63257854A (ja) * | 1987-04-15 | 1988-10-25 | Nec Corp | Lruメモリ障害検出回路 |
JPWO2007096998A1 (ja) * | 2006-02-24 | 2009-07-09 | 富士通株式会社 | キャッシュメモリ装置およびキャッシュメモリ制御方法 |
-
1984
- 1984-03-09 JP JP59044022A patent/JPS60189553A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60189553A (ja) | 1985-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7376877B2 (en) | Combined tag and data ECC for enhanced soft error recovery from cache tag errors | |
US6304992B1 (en) | Technique for correcting single-bit errors in caches with sub-block parity bits | |
US5659678A (en) | Fault tolerant memory | |
US4608687A (en) | Bit steering apparatus and method for correcting errors in stored data, storing the address of the corrected data and using the address to maintain a correct data condition | |
US6480975B1 (en) | ECC mechanism for set associative cache array | |
US5267242A (en) | Method and apparatus for substituting spare memory chip for malfunctioning memory chip with scrubbing | |
US4654847A (en) | Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memory array | |
US8205136B2 (en) | Fault tolerant encoding of directory states for stuck bits | |
US6108753A (en) | Cache error retry technique | |
KR870001307B1 (ko) | 버퍼 기억장치의 단일 비트 에러처리시스템 | |
CN1220949C (zh) | 容忍多处理器数据处理系统中不可恢复差错的方法和装置 | |
US7689891B2 (en) | Method and system for handling stuck bits in cache directories | |
US6035436A (en) | Method and apparatus for fault on use data error handling | |
US6631489B2 (en) | Cache memory and system with partial error detection and correction of MESI protocol | |
JPH0353660B2 (de) | ||
JPH05165719A (ja) | メモリアクセス処理装置 | |
EP0128353A2 (de) | Fehlerbehandlung für einen nichtdurchschreibbaren Cachespeicher | |
JPS61112259A (ja) | キヤツシユメモリ装置の制御方式 | |
JPS6044709B2 (ja) | バツフアリトライ方式 | |
JPH04273348A (ja) | キャッシュ・メモリ | |
JPS63271555A (ja) | 記憶制御方式 | |
JPS6223901B2 (de) | ||
JPS59207080A (ja) | キヤツシユ記憶制御装置 | |
JPS6226492B2 (de) | ||
JPS62130443A (ja) | メモリアクセス制御装置 |