JPH0353660B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a buffer control system for a data processing device, and more particularly to a replacement control system in the event of a failure in the address array section of a buffer memory.

[Background of the invention]

Data processing devices such as medium- and large-sized machines are generally equipped with high-speed buffer memory in addition to the main memory.
Frequently used data in the main storage device is stored in a buffer memory, and when the memory is referenced, the buffer memory is referred to and the target data is read, thereby speeding up the processing. The main memory address of data stored in the buffer memory is usually registered in an address array, and when a memory request is made, first, one of the main memory addresses registered in the address array that matches the request address is registered. You can check whether there is. If there is no match, the data already stored in the buffer memory is invalidated, the required data is newly stored in the buffer memory from the main memory, and its main memory address is registered in the address array. Replacement occurs. If a fault occurs in the address array and there is an error in the main memory address read from the address array, if the fault is left unaddressed, even though the main memory address actually matches the request address, First, there was a risk that replacement would occur and double registration would occur, so some kind of countermeasure was needed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer memory control method that improves the reliability of the buffer memory address array and prevents the risk of double registration.

[Summary of the invention]

When an address is registered in the address array of a buffer memory, the present invention provides parity check bits for the registered address along with the registered address.
and ECC check code are also registered at the same time. This ECC check code is obtained by a predetermined algorithm for the written data, and when reading data, this ECC check code is used to detect whether or not there is an error in the read data, and also to detect whether or not an error has been detected. This is to correct any errors that may have occurred. This method of detecting and correcting errors using ECC check codes is called ECC (Error Check and
Correct method is commonly used as a countermeasure against memory failures in RAM devices, etc. In the present invention, this ECC check code may be provided for each row in each column of the address array, or one set may be provided for each registered address in a plurality of rows. When making a memory request, the request address and the address registered in the address array are compared together with the parity check bit to determine whether or not the data corresponding to the request address is stored in the buffer memory.Then, the request data is stored in the buffer memory. If the corresponding data is not stored, the address and ECC registered for the column
Reads the check code, and if there is no ECC error, determines the replacement throw using the normal algorithm and executes the replacement, and if there is an ECC error, replaces the row containing the bit with the error. Select as ECC
Data is written back from the buffer memory to the main memory using the corrected address.

Thereby, even if there is a failure in the address array and there is an error in the data read from the address array, it is possible to prevent the risk of double registration.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a system configuration of a data processing device to which the present invention is applied. In the figure, 101 is an input/output channel device (CH), 102 and 103 are central processing units (CPU), and these are connected to a main storage device (MS) via a storage control device 104. The storage control device 104 includes request reception units 106, 107, and 108, a priority circuit 109, a request control unit 110, a directory unit 111, a buffer memory (BS) 112, and the like.

Memory requests issued from the CH 101 or the CPUs 102 and 103 are taken into request reception units 106, 107, and 108, respectively. The priority circuit 109 selects one of the memory requests taken in by the request reception units 106 to 108, and the request control unit 11
0 to the directory unit 111. The directory unit 111 has an address array in which the MS addresses of data stored in the BS 112 are registered, and its peripheral circuits, and checks whether a memory request address is registered in the address array, and checks whether the memory request address is registered in the address array. The result is communicated to the request control unit 110. Here, if the request address is registered in the address array, In BS,
If it is not registered, it is called Not in BS. Now, in the case of a fetch request, the request control unit 110 fetches data from the BS 112 when it is In BS, and sends it to CH 101 or CPU 10.
The data is transferred to the request issuer of 2,103, and when Not in BS, the unnecessary data on BS112 is returned to MS113, and the data for each line including the request address is newly sent from MS113.
After transferring to BS112, the target data is transferred to the request source. Also, for store requests, BS1 for In BS requests.
12 (that is, this is a store-in method), and for a Not in BS request, the line containing the data is registered in the BS in the MS 113, and then the data is written.

The present invention is directed to the directory section 111 in FIG.
This is related to. FIG. 2 shows an embodiment of the present invention. For convenience, in the following description, it is assumed that the address array is composed of 256 columns x 4 rows, and data transfer between the BS and MS is performed in units of 256-byte lines.

FIG. 3 shows the bit structure of a request address, and the request address is made up of 28 bits and accompanying 4-bit parity check bits _P0 to _P3 . Of this request address,
Bits 15 to 22 are used as a column address for the address array index, and bits 0 to 14 are used as the registered address for the address array. Bits 0-22 indicate the line address, and bits 23-27 indicate the intra-line address. Figure 4 shows the registered contents of one entry in the address array, where V is a bit indicating the validity of the entry,
Vp is the parity bit of V bits, bits 0 to 14
is the registered address.

Now, in FIG. 2, the address register 30
1 is set to the request address (line address) selected by the priority circuit 109. The column address of this address register 301 is sent to the address array 30 via a line 322.
2 and the ECC array 303, and the contents of the 4 rows of the corresponding column in the address array 302, and
ECC of the same column in the ECC array 303
Read the check code. Note that the ECC array 303 contains data for four rows of registered data in the corresponding columns of the address array 302.
Assume that an ECC check code is stored.

Comparison circuits 304 ₀ to 304 ₃ are address array 3
The registered data of the corresponding row read from the address array 302 is compared with the upper address of the address register 301 given via the line 321. This comparison operation in the comparison circuits 304 ₀ to 304 ₃ is performed for all bits shown in FIG. 4 including the parity bit. Therefore, if there is an error in the data read from the address array 302, the comparison result will be In BS in the row where the data error occurred, regardless of whether a request address is actually registered in that row or not. There isn't.

When a match is detected as a result of the comparison in the comparison circuits 304 ₀ to 304 ₃ , the selection circuit 305 sends a message to the request control unit 1 via the line 324 to determine which row is In BS.
Contact 10. As a result, the request control unit 110 accesses the corresponding column and row of the BS 112, and reads and writes data to the address within the line.

The column address of address register 301 is also set in column address register 306, and the corresponding column of replacement array (RA) 308 is selected. The RA 308 stores replacement information for replacing the BS 112 in accordance with, for example, an LRU (Least Recently Used) method, corresponding to each column of the address array 302. The comparison results of each row in the comparison circuits 304 ₀ to 304 ₃ are sent to the register 3 via the selection circuit 305.
It is set to 07. In case of BS, RA308
updates the replacement information for the corresponding column based on the contents of the register 307 so that the In BS row is replaced last.

On the other hand, if no match is detected in any of the comparison circuits 304 ₀ to 304 ₃ , the selection circuit 305 selects the line 3
Request Not in BS via 24 Control Unit 1
Contact 10. When this Not in BS occurs,
It is necessary to select one of the four rows in the relevant column and replace it. In this case, generally
The replacement throw may be determined according to the instruction from the RA 308, but even though it is actually In BS, it may become Not in BS due to an error in the read data of address array 302 as described above.
In this case, if a replacement throw is determined in accordance with the instructions from the RA 308, there is a risk of double registration. To prevent this, an ECC check is performed, and if there is no error, a replacement throw is determined according to the instructions from the RA 308, but if there is an error, the row with the error is selected as the replacement throw. This will be explained below.

In the case of Not in BS, the RA 308 reads the column replacement information indicated by the column address register 306 and sets it in the register 309.
On the other hand, address array 302 and ECC array 30
The four rows of registered data read from the corresponding column No. 3 and its ECC check code are set in the register 311 via the line 323.
The ECC inspection/correction circuit 312 includes a register 311
An ECC check is performed on the contents of the bit, and if a correctable error is detected, the row address containing the correctable error bit is sent to the replace row determining circuit 3 via a line 325.
Tell 10. At the same time, if a correctable error is detected, the ECC check/correction circuit 312 corrects the error bit and sets the corrected address in the register 313.

The replacement determination circuit 310 determines a replacement row based on the replacement information in the register 309 when there is no ECC error, and replaces the row containing the correctable error detected by the ECC inspection/correction circuit 312 when there is an ECC error. Decide as low. This replacement throw number is line 3
26 to address array 302, address array 302 registers the upper address of address register 301 for that row in the appropriate column via line 320. The replacement throw number determined by the replacement throw determination circuit 310 is also given to the selection circuit 314. As a result, the selection circuit 314 selects the newly registered address on the line 321 for the row to be replaced, and selects the newly registered address on the line 321 for the row that will not be replaced.
The registered address read out from address array 302 on 23 is selected. This selection circuit 31
ECC generation circuit 315 generates a new ECC check code for output data No. 4, and stores it in the corresponding column of ECC array 303 via register 316 and line 327. In addition, if there is no ECC error, use the replace throw number on line 326,
Among the four rows of registered addresses read from the address array 302, the registered address corresponding to the replacement row number is set in the register 313.

Upon receiving the notification of Not in BS, the request control unit 110 first reads out the data of the replace throw selected by the replace throw determination circuit 310 in the corresponding column of the BS 112, and sends the data to the MS 11 indicated by the registered address in the register 313.
3. Write back to the specified area above. Then, the MS113 indicated by the line address of the request address
The data in the upper area is read and transferred to the above-mentioned replace row in the corresponding column of BS112.

If an uncorrectable error is detected in the ECC detection/correction circuit 312, a recovery operation or function reduction is attempted by, for example, a machine check interrupt. Since this is not directly related to the present invention, further explanation will be omitted.

〔Effect of the invention〕

As is clear from the above description, the following effects can be obtained according to this embodiment.

(1) In the case of In BS, there is no need to operate the ECC circuit, so no overhead is added to the BS access time due to the operation of the ECC circuit.

(2) If Not in BS occurs and an error occurs in the read data of the address array, select the corresponding row as a replacement row in the case of a correctable error and write data from the BS to the MS using the corrected address. Therefore, no data is lost and errors in the address array are recovered.

(3) Even though it is actually In BS, if an error occurs in the read data of the address array and it becomes Not in BS, the row containing the error bit is selected as the replacement row.
The risk of double registration is prevented.

〔Effect of the invention〕

As described above, according to the present invention, although the requested data is actually stored in the buffer memory, an error has occurred in the read data of the address array and the data is registered in the address array. Even if the current main memory address and the request address do not match, the risk of double registration can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a data processing device targeted by the present invention, FIG. 2 is an embodiment of the present invention and is a detailed diagram of the directory section in FIG. 1, and FIG. 3 is an example of a request address. FIG. 4 is a diagram showing an example of registered addresses in the address array. 101...I/O channel device, 102, 103
...Central processing unit, 104...Storage control device, 112
...Buffer memory, 113...Main storage device, 301
...Request address register, 302...Address array, 303...ECC array, 308...Replacement array, 310...Replace throw determination circuit, 312...ECC inspection/correction circuit, 315
...ECC check code generation circuit.

Claims (1)

[Scope of Claims] 1. A data processing device having a main memory, a buffer memory for storing a part of data in the main memory, and an address array for registering main memory addresses of data stored in the buffer memory. In the buffer memory control method, when storing part of the data in the main memory in the buffer memory, a parity check bit for the main memory address and a predetermined algorithm are obtained along with the main memory address of the data.
An ECC check code is registered in the address array, and when a request is made to the main memory, the request address and the address stored in the address array are compared together with the parity check bit, and the data corresponding to the request address is checked. Determine whether the request address exists in the buffer memory or not, and if as a result of the determination, data corresponding to the request address does not exist in the buffer memory, apply the ECC check code to the main memory address read from the address array. If no error is detected, a replacement area in the buffer memory is determined and replaced by a predetermined algorithm, and if an error is detected, the area corresponding to the registered address including the error bit is detected. Determine an area in the buffer memory as a replacement area, and
A buffer memory control method characterized in that the error is corrected using an ECC check code and replacement processing is performed.