JPH0353582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal generating device at the time of power outage recovery, which is suitable for use in a processing device that requires fail-safe characteristics, such as a train detection device.

A fail-safe processing device is generally used in a so-called uninterrupted environment to prevent power outages. However, in reality, power outages may occur due to incorrect power operation.
In such cases, devices that use electronic circuits, especially devices that use volatile memory circuits, must be reset to their initial settings after the power outage is restored. Conventionally, this initial setting was done manually. was.

The power outage recovery signal, which means that the power outage has returned, is created by inputting the power supply, differentiating this input signal with a differentiation circuit to extract the power supply rising component, and shaping the output with a waveform shaping circuit. It is possible. However, in such a circuit configuration, if a circuit for this purpose fails, for example, a reset signal may be erroneously generated even though there is no power outage. In other words, it is not possible to configure the system so that the reset output never occurs due to a failure. In other words, for example, if a symmetrical error circuit (for example, a Schmitt circuit) is used as a waveform shaping circuit, when the Schmitt circuit fails or the differential circuit fails (short-circuit failure of the capacitor), the signal will continue to be output when the power is restored. (failure condition exists). In this type of circuit configuration, an initial setting signal (reset signal) is input when it is not needed. In a train detection device that detects trains, the count value of the counter may be reset, so it cannot be used in devices that require fail-safe operation.

The present invention outputs a power outage recovery signal only when the device that generates the initial setting signal is normal (not malfunctioning) and the power has been restored, and erroneously generates a power outage recovery signal when no power outage has occurred. The purpose of the present invention is to provide a signal device for returning from a power outage that does not cause any problems.

The present invention will be described below based on embodiments shown in the drawings.

In Fig. 1, 1 is a power input terminal into which, for example, a 24V DC signal is input from the positive side of the DC power supply;
is an integration circuit that integrates the input signal from terminal 1, 3
60 is a window comparator into which the integral output signal from the integrating circuit 2 is input; 60 is a rectifier circuit 4 that rectifies the output of the window comparator 3; and 60 is a rectifier circuit 4 that delays the output signal of the rectifier circuit 4, extends it as an oscillation output, and sends it out. This is an extended oscillation unit consisting of an oscillation circuit 5, 6 is an output terminal for a signal when the power is restored, 7 is a Zener diode that converts the output of the DC power supply to, for example, 12V as a power source for use in circuits 3, 4, and 5, and 8 is the load resistance of the Zener diode 7.

Integrating circuit 2 is a general circuit in which resistor 10 and capacitor 11 are connected in series between terminal 1 and ground, and the voltage at the connection point (terminal voltage of capacitor 11)
is output to window comparator 3.

The window comparator 3 has a window defined by two upper and lower threshold levels,
This is a known circuit that oscillates and outputs oscillation only when the level of the input signal is within the range of the window, and oscillates when the level of the input signal is below the window, when it is above the window, and when the circuit malfunctions. No output is obtained, and it has so-called asymmetric error characteristics.
This kind of window comparator 3 was developed by Jitsukai Sho.
This is disclosed in Japanese Patent No. 57-4764, and an example thereof is shown in FIG.

The window comparator shown in FIG. 3 is composed of an oscillation circuit using three transistors 31, 32, and 33 in this example, and resistors 34 to 41 constitute an amplifier together with transistors 31, 32, and 33, and cause feedback oscillation. It is a resistance for Terminal 43 is a signal input terminal from the integrating circuit, and terminal 44 is an input terminal for a 12V power supply from Zener diode 7, which supplies power to transistor 32. The base of each transistor is directly connected to the output of the previous transistor. That is, the base of the transistor 31 is connected to the transistor 33.
The output of the transistor 31 is supplied to the base of the transistor 32 through the resistor 36 with a division ratio of collector resistors 34 and 35, and the output of the transistor 31 is supplied to the base of the transistor 32 through the resistors 37 and 3.
The output of the transistor 32 is divided and supplied to the base of the transistor 33 by the resistor 39, including the level shift of the power input to the terminal 44. .

The window comparator described above has input terminal 4
When a certain range of input voltage is applied to transistor 3, transistor 3→transistor 32→transistor 3
A feedback oscillator is configured to which the output of each transistor is supplied in the order of 3→transistor 31.

The range of input voltage V ₁ in which this window comparator can oscillate is as _follows :
When the resistance values of the resistors 34, ₃₅ , 37, 38, and ₃₉ are respectively R ₃₄ , R 35 , R ₃₇ , R ₃₈ , and R 39 , the voltage e ₁ (lower limit) and e are expressed by the following two equations. ₂ (upper limit)
It is between.

e ₁・R ₃₉ / (R ₃₇ + R ₃₈ + R ₃₉ )≒V ₀ …(1) e ₂・R ₃₅ / (R ₃₄ + R ₃₅ )≒V ₀ …(2) Here, between e ₁ and e ₂ is the window of the window comparator.

When the input voltage V ₁ is lower than the lower limit e ₁ , transistor 3 is turned on while transistors 32 and 33 are on.
1 remains off, so it does not oscillate. input voltage
In a range where V ₁ becomes larger than the lower limit e ₁ but does not exceed the upper limit e ₂ , the transistors 32 and 33 are turned off, and therefore the transistor 31 is turned on. When transistor 31 is turned on, transistor 3
2 and 33 are turned off, and the transistor 31 is turned off. When transistor 31 is turned off, transistors 32 and 33 are turned on, so that the window comparator continues to oscillate. Furthermore, when the input voltage V ₁ exceeds the upper limit e ₂ , even if the transistor 33 is turned on, the transistor 31 will not be turned off, so that the oscillation circuit will be unable to oscillate.

As is clear from conditional expressions (1) and (2), the lower limit of the input voltage V ₁ at which the window comparator oscillates.
e ₁ and upper limit e ₂ are resistors 34, 35, 37, 38,
The oscillation start voltage can be freely set by appropriately selecting these resistance values.

The oscillation circuit 5 delays and extends the generation time of the power failure recovery signal (oscillation output) generated as the output signal of the window comparator 3.The oscillation circuit 5 delays and extends the generation time of the power failure recovery signal (oscillation output) generated as the output signal of the window comparator 3. This circuit is designed to ensure that the reset is performed by sending a reset signal (repeated pulses).In the present invention, especially when a failure occurs, no output signal is generated or no output signal is generated. A circuit in which the signal generation time is shortened (a circuit with a configuration in which the recovery signal generation time is shortened due to a failure, or this signal is no longer generated)
Therefore, in the event of a failure, a predetermined power failure recovery signal is never generated, and subsequent devices are not adversely affected. A circuit for extending such a signal is, for example, Japanese Patent Application No. 56-63707 by the same person as the present application, or IEICE, Circuit and System Research Group Material CAS81-31, Waveform Manipulation Using Asymmetric Error Circuit, Page 2, Figure 3. 4, an example of which is described as an ``asymmetric error delay circuit'' or a ``fail-safe delay circuit''.

In the oscillation circuit shown in FIG. 4, a relaxation oscillator 55 is provided on the output side of a relaxation oscillator consisting of a unidirectional transistor 50, resistors 51, 52, 53, and a capacitor 54, and the output side of the capacitor 55 is connected to a DC power source (not shown). This circuit is connected to the positive side through a diode 56 and a terminal 57 and clamped to the power supply voltage (+E). The output side is output terminal 6 as a signal when power is restored.
connected to.

Next, the operation of this signal generator at the time of power recovery will be explained with reference to FIG. 2 (timing chart of each part symbol).

First, if the power failure is restored at time _t1 , the input signal to terminal 1 rises as shown in FIG. 2A. As a result, the output of the integrating circuit 2 rises later than the input signal A as shown in FIG. 2B.
The window comparator 3, which has already received a 12V power supply, emits from t ₂ to t ₃ as shown in Fig. 2C, and its output signal is input to the rectifier circuit 4, which absorbs the large electrostatic current that constitutes the rectifier circuit. The output signal of the capacitor becomes as shown in FIG. 2D, so that the oscillator circuit 5 operates for a period of time T, during which time a repetitive pulse signal (which increases the reliability of the reset) as shown in FIG. 2E is generated. ) is output to terminal 6 as a signal when power is restored.

In this device, if the resistor 10 in the integrating circuit 2 is disconnected or the capacitor 11 is short-circuited, the level of the input signal to the window comparator 3 becomes below the window, and if the resistor is short-circuited or the capacitor 11 is disconnected, the window comparator The level of the input signal to No. 3 exceeds the window, so no signal is output when the power is restored in either case. Further, the window comparator 3 and the extended oscillation circuit 5 do not output any signals if they themselves are made to have an asymmetrical error and fail. And the capacitor 11 in the integrating circuit 2
If the capacitance of decreases over time,
The rise of the waveform in Figure 2B becomes steeper from t ₂ to t ₃
The oscillation time until then becomes shorter, and the generation time T of the return signal becomes shorter. Furthermore, if the capacitance of the large capacitor constituting the rectifier circuit 4 decreases over time, the fall of the waveform shown in FIG. The occurrence time T becomes shorter. Therefore, even in these cases, the signal at the time of power recovery is no longer output in a normal manner, so that the predetermined purpose can be achieved. Further, in the case of a failure in which the rectifier circuit 4 does not output a signal, no signal is generated when the power is restored.

Next, the apparatus shown in FIG. 5 is another embodiment of the present invention, in which a differentiating circuit 20 is used in place of the integrating circuit 2 in FIG. The window of the window comparator 3 in this device is set to such a level that the level of the output signal of the differentiating circuit 20 when the power is restored is within the window, as shown by the symbol V' in FIG. 6B.

In this device as well, when the input signal to the terminal 1 rises at time _t1 as shown in FIG. 6A, the output of the differentiating circuit 20 becomes as shown in FIG. As shown in Figure C, it oscillates between t ₂ and t ₃ , and the output of the rectifier circuit 4 is
The signal shown in is obtained, and as a result, the oscillation circuit 5
It operates for a period of time T' and outputs a pulse signal train as a signal when the power is restored as shown in FIG. 6E.

This device also cannot obtain the differential waveform shown in FIG. 6B even if either the resistor 21 or the capacitor 22 in the differentiating circuit 20 is disconnected or short-circuited. Never happened. Furthermore, as the capacitance of the capacitor 22 decreases due to aging, the time T for generating the return signal becomes shorter.

As described above, the present invention includes a processing circuit that uses the power rise at the time of power recovery as an input signal and differentiates or integrates this input signal, a window comparator that oscillates using the output signal of the processing circuit as input, and a This is a power failure recovery signal generation device comprising a rectifier circuit that rectifies the output, and an oscillation circuit that oscillates with the output of the rectifier circuit to extend the output time and shorten the extension time in the event of a failure. Even if a circuit component fails, no signal is generated when the power is restored other than when the power is restored, and therefore it can be used in a fail-safe signal processing device.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an electric circuit showing an embodiment of the device according to the present invention, Fig. 2 is an explanatory diagram of electrical signals, Fig. 3 is a diagram showing an embodiment of a window comparator, and Fig. 4 is an oscillation circuit. FIG. 5 is a block diagram of an electric circuit showing another embodiment of the apparatus according to the present invention, and FIG. 6 is an explanation of electric signals. 1: Power input terminal, 2: Integrating circuit, 3: Window comparator, 4: Rectifier circuit, 5: Oscillator circuit, 20: Differentiator circuit, 60: Extension oscillation section.

Claims (1)

[Scope of Claims] 1. A device that detects when a power supply returns from a power outage and generates a signal when the power is restored, including a processing circuit that is connected to a DC power source serving as a signal source and that differentiates or integrates an input signal. and a window comparator subsequent to the processing circuit that provides an oscillation output only when there is an input within a predetermined level range, a rectifier circuit that rectifies and outputs the oscillation output of the window comparator, and a rectifier circuit that corresponds to the output of this rectifier circuit. It consists of an extension oscillation section equipped with an oscillation circuit that generates an oscillation output extended for a predetermined time as a signal when the power is restored, and the extension time of the extension oscillation section is shortened or no signal is generated when the circuit fails. A power failure recovery signal generation device having the following configuration.