JPH0352260A - 電子回路装置 - Google Patents

電子回路装置

Info

Publication number
JPH0352260A
JPH0352260A JP1187823A JP18782389A JPH0352260A JP H0352260 A JPH0352260 A JP H0352260A JP 1187823 A JP1187823 A JP 1187823A JP 18782389 A JP18782389 A JP 18782389A JP H0352260 A JPH0352260 A JP H0352260A
Authority
JP
Japan
Prior art keywords
chip
component
semiconductor chip
resin
coating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1187823A
Other languages
English (en)
Inventor
Toru Oki
透 大木
Makoto Kamiya
誠 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1187823A priority Critical patent/JPH0352260A/ja
Publication of JPH0352260A publication Critical patent/JPH0352260A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は混成集積回路装置等の電子回路装置に関するも
のである。
従来の技術 従来、混成集積回路装置における半導体チップとチップ
部品の接続は第２図の様な方法で行われていた。すなわ
ち、アルミナ基板１１上の導体１９上に絶縁性接着用樹
脂ｌ３で、半導体チップ１４を固定し、アルミナ基板１
１上の導体１７．２０と、半導体チップ１４の電極をワ
イヤ１５で接続し、保護コート樹脂１２を施し、次にチ
ップ部品の電極部と導体２０をはんだ１８で接続すると
いうものであった。
発明が解決しようとする課題 この様な従来の方法によれば、ワイヤボンディング部全
体に保護コート樹脂１２を施す都合上、半導体チップ１
４とチップ部品１６の間の間隔を長くとる必要があった
。また、導体１７のボンディングパット部にはんだが付
着してはいけないため保護コート樹脂を大きくする必要
があった。
これらの理由により、半導体チップとチップ部品の間隔
を縮めることは難しく、これが混成集積回路装置の部品
実装の高密度化の障害の一つになっていた。本発明は、
この様な課題を解決することを目的としている。
課題を解決するための手段 この課題を解決するため、本発明は、半導体チップとチ
ップ部品を同時に絶縁性接着樹脂で固定し、それらの電
極部に直接ワイヤボンデイングをし、半導体チップとチ
ップ部品全体を保護コート樹脂で覆うものである。
作用 この方法によれば、チップ部品にはんだを使用しないた
め、導体のボンディングバットにはんだが付着すること
がなく、またチップ部品も含めて保護コート樹脂を施す
ために、半導体チップとチップ部品の間隔を大幅に縮め
ることができ、高密度実装が可能となる。
実施例 第１図は、本発明の一実施例による概略図である。図に
おいて、１はアルミナ基板、７，８はアルミナ基板１の
上に所定のパターンとなるように形成した導体である。
３は半導体チップ４およびチップ部品６を同時に固定す
るための絶縁性接着樹脂である。５はボンディングワイ
ヤで、半導体チップ４及びチップ部品６の電極部と、導
体７，８の端部を接続している。
２は保護コート樹脂で、半導体チップ４、チッブ部品６
及びボンディングワイヤ５の全体を覆っている。
このように本実施例においては導体８を設けた構造であ
るが、半導体チップ４の電極部とチップ部品６の電極部
をワイヤボンディングすることにより、導体８を省略で
き、さらに高密度化できる。
発明の効果 以上述べてきたように本発明によれば、半導体チップと
それに接続されるチップ部品との間隔を大幅に縮めるこ
とができ、混成集積回路装置における部品実装の高密度
化に大きく寄与し、実用的にきわめて有用である。
【図面の簡単な説明】
第１図ａは本発明の一実施例による混成集積回路装置の
平面図、第１図ｂは第１図ａのＡ−Ａ’で切断した断面
図、第２図ａは従来の混戒集積回路装置の平面図、第２
図ｂは第２図ａのＢ−Ｂ’で切断した断面図である。 １・・・・・・アルミナ基板、２・・・・・・保護コー
ト樹脂、３・・・・・・絶縁性接着樹脂、４・・・・・
・半導体チップ、５・・・・・・ボンディングワイヤ、
６・・・・・・チップ部品、７，８・・・・・・導体。

Claims (1)

    【特許請求の範囲】
  1. 少なくともワイヤボンディングを必要とする半導体チッ
    プと面実装用チップ部品を基板上に取付けることにより
    構成され、かつ上記チップ部品を絶縁性装着樹脂で基板
    上に固定し、上記チップ部品の電極部をワイヤボンディ
    ングにより接続し、上記半導体チップ及びチップ部品全
    体を保護コート樹脂で覆ったことを特徴とする電子回路
    装置。
JP1187823A 1989-07-20 1989-07-20 電子回路装置 Pending JPH0352260A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1187823A JPH0352260A (ja) 1989-07-20 1989-07-20 電子回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1187823A JPH0352260A (ja) 1989-07-20 1989-07-20 電子回路装置

Publications (1)

Publication Number Publication Date
JPH0352260A true JPH0352260A (ja) 1991-03-06

Family

ID=16212863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1187823A Pending JPH0352260A (ja) 1989-07-20 1989-07-20 電子回路装置

Country Status (1)

Country Link
JP (1) JPH0352260A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120646A (ja) * 1992-10-08 1994-04-28 Mitsubishi Heavy Ind Ltd 薄膜センサ実装法
EP1187523A3 (en) * 2000-09-07 2005-06-29 Sharp Kabushiki Kaisha High-frequency module and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120646A (ja) * 1992-10-08 1994-04-28 Mitsubishi Heavy Ind Ltd 薄膜センサ実装法
EP1187523A3 (en) * 2000-09-07 2005-06-29 Sharp Kabushiki Kaisha High-frequency module and manufacturing method of the same

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