JPH0351972A - State change detection system for input data - Google Patents

Abstract

PURPOSE:To reduce the load on a CPU and to speed up detection as to whether or not there is a state change by sampling data of plural input ports and detecting whether or not there is the state change through a circuit without the intervention of a CPU. CONSTITUTION:Buffers 41 and 4N receive data D1 and DN from input ports I1 and IN individually and a counter 2 specifies an address signal ADR1 to a common RAM 1; and a control circuit 3 generate a chip select CS and write/ read control signals EB1 and EB2 for the buffers 41 and 4N and common RAM 1, and sample data in data units of the input ports are written in the common RAM 1. A comparing circuit 5 inputs current data DATA1 of sample data of the data D1 and DN from the buffers 41 and 4N and last data DATA2 from the common RAM 1 to detect whether or not there is the state change of data, and sends out an interruption processing request IRQ to a CPU 6 when detecting the state change. Consequently, the load on the CPU is reduced and the detection of the state change of the data of the input ports is speeded up.

Description

[Detailed Description of the Invention] [Summary] A system in which a CPU performs corresponding processing when data from multiple input devices is sampled and a change in the state thereof is detected, in particular detecting a change in the state of data from an input port. The purpose of this method is to reduce the load on the CPU and speed up the detection of state changes by sampling data from multiple input ports and detecting state changes using a circuit that does not involve the CPU. A common RAM that has two access surfaces that are commonly used for writing and reading data through buffers that individually transfer data from input ports, and a common address allocation signal and control circuit for writing and reading the common RAM. A counter that creates a RAM write control signal and a chip select signal that selects sample data for each input port from the buffer, and detects a state change by comparing the previous data from the common RAM and the current data from the buffer. A comparison circuit 5 that uses the detection signal of the comparison circuit as an interrupt processing request signal to perform interrupt processing on the current data and output an address signal for the data, and a CPU that decodes the address signal output from the CPU and outputs an address signal for the data. It is equipped with a decoder that outputs a chip select signal that selects the sending of data from the buffer, and samples the data of a plurality of input ports and detects state changes using a common RAM, a counter, and a comparison circuit that are not controlled by the CPU. takes care to receive and process processing requests only when the state of input data changes.

[Industrial application field]

The present invention relates to a system in which data from a plurality of input devices is polled and sampled to detect changes in the state thereof, and a CPU performs corresponding processing, and particularly relates to a method for detecting changes in the state of data from input ports.

Systems that use a CPU to poll, sample, and process data from a plurality of input ports are required to perform a large number of processes as quickly as possible. Therefore, it is necessary to shorten the sampling period and the time from the occurrence of a state change to the processing by the CPU. Also, since the CPU is involved in the processing during the entire sampling process, there is a need to improve this situation.

[Conventional technology]

In the conventional input data state change detection method, as shown in the block diagram of FIG. 4, one CPU 6A can detect multiple state changes. Data D, , D. of input ports L, Iz~. Buffer 41A. 41,. ~, with one sampling signal of period T, data D of all input ports L, Iz~
+, Dz""'11+21'---'+n
-11+nl, h+2z '-”'+n-IZ
+n2~ are sampled all at once, and when a change in the state of each sample data is detected, the corresponding processing is performed. A plurality of defined input ports I,, I! We continue to detect state changes for all sample data of ~.

Then, CP0 6A is the data h of one input port h
, 2+ '---'i-11+nl is sampled once until it is sampled again, as shown in Fig. 3 Φ).
It took only a few minutes.

[Problem to be solved by the invention]

Therefore, the conventional method has the following problems.

(1) One CPU is used for both sampling and detecting the presence or absence of state changes, so if the number of sample data items to check for state changes increases, the CPU processing time will increase and the state will change. The time from detection to detection becomes longer and processing becomes slower. (2) In most cases, the CPU performs other processing in addition to sampling and detecting the presence or absence of a state change, so even if a change in the state of input port data occurs during another process, the change is immediately detected. cannot be detected.

The present invention reduces the load on the CPU and increases the speed of detecting the presence or absence of a state change by sampling data from multiple input ports and detecting the presence or absence of a state change using a circuit that does not involve the CPU. The challenge is to achieve this goal.

[Means to solve the problem]

This problem consists of a plurality of N input ports i, as shown in FIG.
,,i. A common 12AM l, which has two surfaces commonly used for writing and reading data, and a common RAM 1 Address allocation signal ADR for writing and reading on the second side, O? The control circuit 3 outputs write control signals EB, EB for the common RAM 1 and the buffer 4. ．． 4. Input data from D+, D
A counter 2 that generates chip select signals CS++ and CS+■ for selecting the sending of sample data of H for each input data unit, and the previous data DA from the common RAM 1.
T.A. and the current data DATA . from the buffer 41, 4s. Comparison circuit 5 that detects a state change by comparing
, the detection signal of the comparison circuit is input as an interrupt request signal IRQ to the buffers 41, . Current data DATA from 4N
, and outputs the address signal ADlh of the current data DATA.
4N data D. , o. Chip select signals cs2, , cs . ■A decoder 7 that outputs each data D from a plurality of input ports }It, Is.
,,D. A change in the state of the C
PtI 6 is solved by the present invention, which is configured to receive and process a processing request from comparator circuit 5 only when the state change occurs.

? In the principle diagram of FIG. 1 showing the basic structure of the input data state change detection method of the invention, 1 represents data D, from a plurality of N input ports r,, r,
, DH buffers 41 and 4 used individually for receiving and receiving DH.
This is a common RAM having two surfaces that are commonly used for writing and reading data via N.

2 is an address allocation signal ADR for successive writing on two sides of the common RAM 1, and a control circuit 3 is used to control the common RAM 1.
write control signal EB. , EB2 and the buffer 4I
, 4N to each person's cover data D. , D. A chip select signal CSz, which selects the sending of sample data of
This is a counter used for the discipline of CS,2.

3 is a write control signal EB, EB . and buffer 4+, 4 N
Each input port data D,,D. A chip select signal CS. ,CSlz
This is a control circuit that regulates the

414N is data D from multiple people Kapo H+, Is
1. This is a buffer used individually for DH transfer.

? is the current data DATA . sampled from buffer 4+, 4 s. This is a comparison circuit which inputs the previous data DATA 2 from the common RAM 1 and detects whether there is a change in the state of the data.

6 receives the detection signal from the comparator circuit 5 as an interrupt processing request IRQ, processes the interrupt, and outputs the current data DATA . This is a CPU that processes

7 decodes the address signal ADRz of the current data DATA1 processed by the CPU 6 and sends it to the buffer 4. , 4 N chip select signals cs, , cs. This is a decoder that outputs ■.

? Effect] Buffer 4+. 4 N is a plurality of N input ports ■1.
It individually receives data D, , D N from IN and writes the sample data to common RAM 1. At this time,
Counter 2 sends address signal ADR. to common RAM 1.
, and the control circuit 3 has a common R with the buffers 41 and 4N.
AM 1 chip select CS, write WE and read R
E control signals EB,, EB. , and writes the sample data in data units of each input port to the common RAM 1.

The comparison circuit 5 includes buffers 41, 4 . Input port 1, iN each data D,,D. It inputs the current sample data DATA, and the previous data DATA2 from the common RAM 1, detects whether there is a change in the state of the data, and sends an interrupt processing request IRQ to the CPU 6 when a change in state is detected. do.

The CPU 6 has a plurality of input ports I, . Each data D,,D of IN. Only when a state change occurs in the sample data of
Since the interrupt processing request IRQ is received from the comparator circuit 5 and the current data DATA is processed, the state change processing is quickly performed.

That is, the input data state change detection method of the present invention is as follows:
By sampling data from multiple input ports and detecting the presence or absence of a change in the state of the sample data using the common RAM 1, counter 2, and comparison circuit 5 without going through the CPU, the load on the CPU 6 can be reduced and the input port The problem is solved because it is possible to speed up the detection of changes in the state of data.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the input data state change detection method according to the embodiment of the present invention, and FIG. 3(a) is a sampling period diagram for explaining its operation.

In the block diagram of FIG. 2, a common RAM 1 stores data D1 to D. A RAM having two surfaces (1) and (2) used for writing and reading sample data, and is used individually for temporarily transferring data D1 to DH from a plurality of N people's ports. It is commonly used for writing and reading sample data of each data via each receiving buffer REC 1 of the buffer 414N used.

As shown in FIG. 3(a), the counter 2 is
~■ Consists of a counter COUNT that counts T2 for one person excluding the separate processing α out of one sampling period T1 of each data DI-DN from 8, and writes to two sides (1) and (2) of the common RAMl. Read address allocation signal A
DR. Common to generation and control circuit 3 CONT,?
AM 1 write key, read Rε, chip select CS
control signals EB, EB2 and the buffers 4, . 4
．． Each input port data from D. ,D. Chip select signals CSz, CS that select the sending of sample data of
＋■ Used for etiquette.

The comparison circuit 5 is composed of a comparator COMP, and a buffer '
L, 4 input ports from I, . Each data of IN
、． The current data DATA I of the sample data of each input data unit of 02 and the previous data DATA2 from the common RAM I are input to detect whether there is a change in the state of the data, and when a change in state is detected, the Sends an IRQ request for processing.

The current data DATA, on the first port side of the two-sided RAM of common RAM 1 (
1). In this case, the write address ADR,
is determined by COUNT of counter 4. Also,
Write control signal EB. is activated by CONT+ of the control circuit 3.

The previous data DATAz is determined by the counter COUNT at the data address ADR. After specifying the CON of control circuit 3
T. control signal EB. Common RAM 1 using 2nd
It is read from the port side (2) and sent to COMP of the comparison circuit 5.

CPυ6 stores each data D. of a plurality of input ports 1-1,,IN. , DN only when a change occurs in the state of each sample data, receives an interrupt processing request IRQ from the comparator circuit 5,
Interrupt processing is performed accordingly, and the input port I1. Current data DATA from IN, REC of puffer 8. Start reading operation to. This read operation of the buffer 8 is generated in response to the address signal ADR2 from the CPU 6 to the CONT 2 of the decoder 7, and the read operation of the buffer 8 is
．． This is done by manipulating the chip select signal CS2 supplied to the current data DATA. Processing of the state change will be performed immediately.

In other words, the input data state change detection method of the embodiment shown in FIG.
By using M1, counter 2, and comparison circuit 5, C
There is no problem because it is possible to reduce the load on the PU 6 and at the same time speed up the detection of changes in the data state of the input port.

[Effects of the Invention] As described above, according to the present invention, it is no longer necessary for the CPU to constantly poll all of the data of a plurality of input ports, and the processing time of cpυ is shortened. Furthermore, since it is possible to monitor each data from the input port and perform other processing, there is an effect that the CPU can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the basic structure of the input data state change detection method of the present invention, FIG. 2 is a block diagram showing the structure of the input data state change detection method of the embodiment of the present invention, and FIG. 4 is a sampling period diagram for explaining the operation of the embodiment of the present invention, and FIG. 4 is a block diagram of a conventional input data state change detection method. In the figure, 2 is a common RAM, 2 is a counter, 3 is a control circuit, 414 is a buffer, 5 is a comparison circuit, 6 is a CPU, and 7 is a decoder.

Claims (1)

[Claims] Data (D
Buffer (4_1, D_N) for transferring individually
, 4_N), the RAM (
1), the address allocation signal (ADR_1) for writing and reading two sides of the common RAM and the control circuit (3) for writing and reading the common RAM from the write control signals (EB_1, EB_2) and the buffers (4_1, 4_N). Input data (D_1
, D_N) for each input port to select the transmission of sampled data (CS_1_1, C
S_1_2) and a counter (2) for creating the common R
The previous data (DATA_2) from AM and the buffer (
A comparison circuit (5) detects a state change by comparing the current data (DATA_1) from 4_1, 4_N), and a comparison circuit (5) detects a state change by comparing the current data (DATA_1) from 4_1, 4_N).
DATA_1) interrupt processing and address of the data (A
DR_2), and a CPU (6) that decodes the output (ADR_2) of the CPU and outputs the buffer (4_1, 4_N
Chip select signal (
CS_2_1, CS_2_2)
), sampling of each data (D_1, D_N) from multiple input ports (I_1, I_N) and detection of state changes are performed using a common RAM (1
), counter (2) and comparison circuit (5), and the C
An input data state change detection method characterized in that a PU receives and processes a processing request only when a state change of input data occurs.