JPH0351016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to a state information control method for managing an area of a main storage device in a virtual storage computer system.

In a virtual storage computer system, as is well known, an area extracted from the main storage device is allocated and used as a required storage area of a so-called virtual storage space.

Normally, this allocation is performed in units of blocks, which are the area of the main memory device divided into fixed sizes, and in this case, the status information of each block is used to manage the allocation.

Such status information includes, for example, information indicating whether a block has been referenced or updated by program execution.

For example, the block size is 4096 bytes and
2048 bytes (hereinafter referred to as 4K bytes and 2K bytes) are often used, and there are systems that allow you to select both methods, but recently
There is a trend towards increasing use of 4K bytes.

[Conventional technology]

For example, in a system that is capable of handling both 2K and 4K byte blocks, the reading of block state information has conventionally been performed as follows.

FIG. 2 is an explanatory diagram of a conventional method of state information read control.

Status information includes, for example, a reference bit indicating that a block has been accessed, a change bit indicating that an update has occurred, etc., and is usually stored in the key memory as the status information of a 2K byte block, along with the memory protection key of the block. It is stored in the device 1.

If the byte address of the main memory in this example is, for example, 32 bits from 0th to 31st bits, then the block address of a 2K byte block is 21st bits from 0th to 20th bits.
Bits, addresses of 4K byte blocks are from 0th to
Represented by 19 20 bits.

When an instruction that refers to the status information of a 2K byte block is executed, the upper 21 bits of the storage address specified as the operand of the instruction are input to the address line 2 of the key storage device 1, and the status information is transferred to the key register 3. Read out. This information is, for example, A
It is output to the output register 5 via the register 4.

When an instruction that refers to the status information of a 4K byte block is executed, the block address is determined by the 20 high-order bits from 0 to 19 of the storage address of the operand of the instruction. First, input the 21-bit address with "0" added to the 20th bit to the address line 2, read the status information of the 2K byte block in the first half of the target 4K byte block, and set it to the A register 4 via the key register 3. do.

Next, input the address with the 20th bit set to "1" to the address line 2, read out the status information of the latter 2K byte block, and set it in the B register 6.
A register 4 and B register 6 by gate circuit 7
The logical sum of these is set in the output register 5.

[Problem that the invention seeks to solve]

As is clear from the above explanation, according to the conventional method, in a system that can use 2K byte blocks and 4K byte blocks, it takes about twice as much time to reference the status information of the 4K byte blocks as in the case of 2K byte blocks. There is a problem that.

Improvements to this problem are particularly desired in situations where 4K byte blocks are increasingly used.

[Means for solving problems]

The above problem lies in the first operating mode, which divides the area of the main memory into blocks of a fixed size and manages the state information for each block, and the first operating mode, which divides the area of the main memory into blocks of a fixed size and manages the state information for each block, and the first operating mode, which divides the area of the main memory into blocks of a fixed size and manages the status information for each block. In a computer system having a second operation mode for managing state information, a certain number of state information storage means are provided that hold state information of the small blocks and can be read individually, and When reading the state information, the state information of all the small blocks belonging to the required block is simultaneously read from all the state information storage means, the logical sum of the read state information is output, and the second operation is performed. The main memory status information control of the present invention is configured to read status information of any of the small blocks belonging to the required block from one of the corresponding status information storage means when reading the status information in the mode. Solved by method.

[Effect]

That is, for example, as in the above example, a 4K byte block and this divided into two small blocks.
In a system having an operating mode with 2K byte blocks, a key storage device for state information corresponding to the 2K byte blocks is provided, and the key storage device stores the state information of two 2K byte blocks belonging to one 4K byte block. The configuration is such that simultaneous reading is possible, and the logical sum of both read information is output.

With this configuration, whether it is a 2K byte block or a 4K byte block, it is possible to read the state information in the same time as in the case of a conventional 2K byte block.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The key storage device has 2 keys corresponding to the even and odd block addresses of the 2K byte block.
It consists of a key storage device 10-0 and a key storage device 10-1, which are separated.

The 0th to 19th bits of the address signal for accessing the key storage device 10-0 or 10-1 are
The 20th bit is input to the address line 11 and the control line 12. Further, a signal specifying the 2K/4K operation mode of the block is input to the control line 13.

The signals on both control lines 12 and 13 control the switching circuit 15, and when the control line 13 specifies the 2K operation mode, the 20-bit address signal on the address line 11 is
If the signal on the control line 12 is “0”, the address line 14
-0, and if the signal on the control line 12 is "1", it passes to the address line 14-1.

Further, when the control line 13 specifies the 4K operation mode, the address signal on the address line 11 passes to both address lines 14-0 and 14-1.

As described above, the state information corresponding to the 2K byte block of the specified block address is read out from the key storage device 10-0 or 10-1, or both, into which the address signal is input, and the output OR circuit 16 reads out the state information corresponding to the 2K byte block. The sum is taken and the key register 3
is set and output to the output register 5.

As a result of the above, even in the case of 2K byte blocks, 4K
In the case of byte blocks, status information can be accessed in the same shortest time as in the case of conventional 2K byte blocks.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the speed of accessing the status information of the memory blocks of the main memory device is increased, so that there is a significant industrial effect of improving the performance of the computer system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional structure. In the figure, 1, 10-0, 10-2 are key storage devices, 2, 11 are address lines, 3 is a key register, 5 is an output register, 7, 16 are OR circuits,
12 and 13 are control lines, and 15 is a switching circuit.

Claims (1)

[Claims] 1 A first operation mode in which the area of the main storage device is divided into blocks of a fixed size and status information for each block is managed, and a second operation mode in which the block is divided into a fixed number of small blocks and status information is managed for each block. In a computer system having two operation modes,
A predetermined number of state information storage means for holding and individually reading state information of the small blocks is provided, and when reading the state information in the first operation mode, all of the small blocks belonging to the required block are stored. The state information of the above-mentioned block is simultaneously read out from all of the above-mentioned state information storage means, the logical sum of the read state information is output, and when the state information is read in the above-mentioned second operation mode, one of the required blocks belonging to the above-mentioned block is read out. A main memory status information control system characterized in that the status information of the small block is read out from one of the corresponding status information storage means.