JPH0349314A - Probability control filter - Google Patents

Probability control filter

Info

Publication number
JPH0349314A
JPH0349314A JP1185428A JP18542889A JPH0349314A JP H0349314 A JPH0349314 A JP H0349314A JP 1185428 A JP1185428 A JP 1185428A JP 18542889 A JP18542889 A JP 18542889A JP H0349314 A JPH0349314 A JP H0349314A
Authority
JP
Japan
Prior art keywords
pulse train
pulse
pulses
input
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1185428A
Other languages
Japanese (ja)
Inventor
Takushi Nakano
中野 琢司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1185428A priority Critical patent/JPH0349314A/en
Publication of JPH0349314A publication Critical patent/JPH0349314A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate a noise component from a pulse train signal singly by eliminating n-set of pulses when a pulse number N of an inputted 1st pulse train is larger than a predetermined pulse number (n), outputting a pulse train whose pulse number is '0' when number N is equal to or smaller than the number (n) and adding predetermined m-set of pulses. CONSTITUTION:A pulse train comprising N-set of pulses is inputted to a pulse train input terminal 1a, a single pulse is inputted to a pulse train input timing signal input terminal 1b just before the pulse train is inputted to the pulse train input terminal 1a, the upper limit of a steady-state noise component DELTAN included in the input pulse train is 16 and the succeeding system is responsive even with one pulse output, then when tue number N of the input pulses is larger than 16, 16 pulses are subtracted from the N-set of pulses and one pulse is added to be N-15 pulses in total are outputted from a pulse train output terminal 4 and when the input pulse number N is 16 or less than 16, only one single pulse is outputted from the pulse train output terminal 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は確率制御フィルタに関し、特にディジタル位相
同期回路の位相差信号のようにパルス数が物理量を表わ
すパルス列信号に含まれる雑音成分パルスを除去するた
めの確率制御フィルタ、いわゆるランダムウオークフィ
ルタに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a stochastic control filter, and in particular to a method for removing noise component pulses contained in a pulse train signal in which the number of pulses represents a physical quantity, such as a phase difference signal of a digital phase synchronization circuit. This invention relates to a stochastic control filter, a so-called random walk filter.

〔従来の技術〕[Conventional technology]

ディジタル位相同期回路には確率制御フィルタが組込ま
れており、位相同期回路中において結果的にはパルス列
信号から雑音成分を除去する機能を果している(例えば
、電子通信学会論文誌、56−A(12)(昭48−1
2)P、751−758>。
The digital phase-locked circuit has a built-in stochastic control filter, which ultimately functions to remove noise components from the pulse train signal (for example, Journal of the Institute of Electronics and Communication Engineers, 56-A (12). ) (Sho 48-1
2) P, 751-758>.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上述した従来の確率制御フィルタは位相同期回
路に組込まれた形でのみ動作し、それ単独でパルス列信
号から雑音成分を除去するような使用はできない。
However, the above-mentioned conventional stochastic control filter operates only when incorporated into a phase locked circuit, and cannot be used alone to remove noise components from a pulse train signal.

本発明の目的は、単独でパルス列信号からm fJ酸成
分除去する機能を有する確率制御フィルタを新しく提供
することにある。
An object of the present invention is to provide a new stochastic control filter that has the function of independently removing m fJ acid components from a pulse train signal.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の確率制御フィルタは、入力した第1のパルス列
のパルス数Nがあらかじめ定めたパルス数nより大きい
とき前記第1のパルス列からn個のパルスを除去してパ
ルス数N−nの第2のパルス列を出力し等しいか小さい
ときはパルス数0のパルス列を前記第2のパルス列とし
て出力する第1の手段と、前記第2のパルス列にあらか
じめ定めたm個のパルスを付加してパルス数N−n+m
又はパルス数mの第3のパルス列を出力する第2の手段
とを備えている。
The probability control filter of the present invention removes n pulses from the first pulse train when the number N of pulses of the input first pulse train is larger than a predetermined number n of pulses, and a first means for outputting a pulse train with a pulse number of 0 as the second pulse train when the number of pulses is equal to or smaller than the number of pulses; -n+m
or a second means for outputting a third pulse train of the number m of pulses.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

第1図において、1aはパルス列入力端、1bはパルス
列入力端1aにパルス列の入力が開始されるタイミング
を与える信号の入力端、2はプリセット可能なアップダ
ウンカウンタ2a(例えば日本電気製のμPD4029
B)、単安定マルチバイブレータ2b(例えば米国GE
社製のCD4098B)、ANDゲート2C及び2dを
含みパルス列入力端1aに入力したN個のパルスからな
るパルス列から最初の16個のパルスを除去する回路、
3はORゲート3a、単安定マルチバイブレータ3b(
例えば米国GE社製のCD4098B)を含みANDゲ
ート2dのパルス列出力に1個のパルスを付加する回路
、4はパルス列出力端である。
In FIG. 1, 1a is a pulse train input terminal, 1b is an input terminal for a signal that gives the timing to start inputting a pulse train to the pulse train input terminal 1a, and 2 is a presettable up/down counter 2a (for example, NEC's μPD4029
B), monostable multivibrator 2b (e.g. US GE
CD4098B), a circuit that removes the first 16 pulses from a pulse train consisting of N pulses input to the pulse train input terminal 1a, including AND gates 2C and 2d;
3 is an OR gate 3a, a monostable multivibrator 3b (
For example, the circuit includes a CD4098B (manufactured by GE, USA) and adds one pulse to the pulse train output of the AND gate 2d. 4 is a pulse train output terminal.

次に第1図の実施例の動作を説明する。Next, the operation of the embodiment shown in FIG. 1 will be explained.

第2図は第1図に示す実施例の動作タイムチャートであ
る。
FIG. 2 is an operation time chart of the embodiment shown in FIG.

パルス列入力端1aにはN IINのパルスからなるパ
ルス列が入力され、パルス列入力タイミング信号入力端
1bにはパルス列入力端1aにパルス列が入力される直
前に単パルスが入力されるとする。ただし、入力パルス
列はパルスの個数により量子化された数値入力であり、
パルスの個数によっである物理量を示す、このパルスの
個数には信号成分と雑音成分が含まれる。すなわち、真
の物理量に対応するパルスの個数がNsであるとき、実
際の入力パルス列はN = N s+ΔN個のパルスよ
りなる(Ns:信号成分、ΔN:雑音成分〉。
It is assumed that a pulse train consisting of N IIN pulses is input to the pulse train input terminal 1a, and a single pulse is input to the pulse train input timing signal input terminal 1b immediately before the pulse train is input to the pulse train input terminal 1a. However, the input pulse train is a numerical input quantized by the number of pulses,
The number of pulses indicates a certain physical quantity, and this number of pulses includes a signal component and a noise component. That is, when the number of pulses corresponding to the true physical quantity is Ns, the actual input pulse train consists of N=Ns+ΔN pulses (Ns: signal component, ΔN: noise component).

第1図に示す実施例では入力パルス列に含まれる定常的
な雑音成分ΔNの上限が16であると仮定する。また、
この実施例に後続する系は1個のパルス出力によっても
応答するものとする。
In the embodiment shown in FIG. 1, it is assumed that the upper limit of the stationary noise component ΔN included in the input pulse train is 16. Also,
It is assumed that the system following this example also responds with a single pulse output.

パルス列入力タイミング信号入力端1bにパルス列入力
タイミングの単パルス信号が入力されると、この信号の
立ち上がりエツジにより、単安定マルチバイブレータ2
bから十分に短い単パルスが発生し、アップダウンカウ
ンタ2aのJAM入力を0にセットする。このとき、ア
ップダウンカウンタ2aのco出力はH(High)と
なり、ANDゲート2cが開き、パルス列入力端1aの
パルス列はアップダウンカウンタ2aのCLOCK入力
に入力される。
When a single pulse signal of pulse train input timing is input to the pulse train input timing signal input terminal 1b, the rising edge of this signal causes the monostable multivibrator 2 to
A sufficiently short single pulse is generated from b, and the JAM input of the up/down counter 2a is set to 0. At this time, the co output of the up/down counter 2a becomes H (High), the AND gate 2c opens, and the pulse train at the pulse train input terminal 1a is input to the CLOCK input of the up/down counter 2a.

アップダウンカウンタ2aのカウント値が15に達する
と再びアップダウンカウンタ2aのC0出力はL (L
ow)となり、ANDゲート2cは閉じる。この間、ア
ップダウンカウンタ2aのJAM入力を0にセットする
間に1個のパルスが入力するので、合計16個のパルス
がアップダウンカウンタ2aのCLOCK入力に入力さ
れる。
When the count value of the up/down counter 2a reaches 15, the C0 output of the up/down counter 2a becomes L (L
ow), and the AND gate 2c is closed. During this time, one pulse is input while the JAM input of the up-down counter 2a is set to 0, so a total of 16 pulses are input to the CLOCK input of the up-down counter 2a.

ADNゲート2dはANDゲート2 cと連動し、パル
ス列入力の17個目以降のパルスが通過する。
The ADN gate 2d operates in conjunction with the AND gate 2c, and passes the 17th and subsequent pulses of the pulse train input.

単安定マルチバイブレータ3bはアップダウンカウンタ
2aのJAM入力を0にセットした後、単パルスを1個
生成し、このパルスとANDゲート2dを通過したパル
スの両方がORゲート3aによりパルス列出力端4に出
力される。したがって、パルス列出力端4には、入力パ
ルスの個数Nが16個より多ければN個より16個のパ
ルスを除去し1個のパルスを付加するから、N−16÷
1=N−15個のパルスが出力される。また、入力パル
スの個数Nが16個であるか16個より少なければ単に
1個だけパルスが出力される。
After setting the JAM input of the up/down counter 2a to 0, the monostable multivibrator 3b generates one single pulse, and both this pulse and the pulse that has passed through the AND gate 2d are output to the pulse train output terminal 4 by the OR gate 3a. Output. Therefore, if the number N of input pulses is more than 16, 16 pulses are removed from N and 1 pulse is added to the pulse train output terminal 4, so N-16 ÷
1=N-15 pulses are output. Further, if the number N of input pulses is 16 or less than 16, only one pulse is output.

入力パルス列の性質により、入力パルス列がら除去する
パルスの個数n、付加するパルスの個数mを選択し、同
様の回路が構成される。
A similar circuit is constructed by selecting the number n of pulses to be removed from the input pulse train and the number m of pulses to be added depending on the properties of the input pulse train.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の確率制御フィルタは、N個
の入力パルス列に対しN−n+m個又はm個のパルス列
を出力するため、次の効果がある。
As explained above, the stochastic control filter of the present invention outputs N-n+m or m pulse trains for N input pulse trains, and therefore has the following effects.

入力パルス列Nは信号成分Nsと雑音成分ΔNよりなる
とする。すなわち、 N=N、+ΔN また、入力パルス列は極性をもち、パルス列(そのパル
ス数が物理量を表わす)とともに後続の系に伝達される
とする(例えば、位相同期回路において入力パルス列が
位相差信号であって進み位相/遅れ位相の2つの極性を
持つ場合など)。
It is assumed that the input pulse train N consists of a signal component Ns and a noise component ΔN. That is, N=N, +ΔN Also, assume that the input pulse train has polarity and is transmitted to the subsequent system together with the pulse train (the number of pulses represents a physical quantity) (for example, in a phase locked circuit, the input pulse train is a phase difference signal). (e.g., when there are two polarities: leading phase and lagging phase).

いま、信号成分N、が雑音成分ΔNに比べ小さいとき、
本発明の確率制御フィルタの除去パルスの個数nにΔN
の定常的な値より大きな値を選べば、 N、+ΔNun とできる。このときN5の値に応じてNs+ΔNの極性
の発生確率が変化し、確率制御フィルタはm個のパルス
を出力する。したがって、雑音成分ΔNを後続の系に伝
達せず、極性の発生確率により信号成分Nsが伝達され
る。
Now, when the signal component N is smaller than the noise component ΔN,
The number n of removal pulses of the stochastic control filter of the present invention is ΔN
If you choose a value larger than the steady value of , you can get N, +ΔNun. At this time, the probability of occurrence of the polarity Ns+ΔN changes depending on the value of N5, and the probability control filter outputs m pulses. Therefore, the noise component ΔN is not transmitted to the subsequent system, and the signal component Ns is transmitted according to the probability of occurrence of polarity.

次に、信号成分N5が雑音成分ΔNに比べ十分大きいと
き N=N−n+m したがって、後続の系に対して信号成分NSが伝達され
る。
Next, when the signal component N5 is sufficiently larger than the noise component ΔN, N=N-n+m. Therefore, the signal component NS is transmitted to the subsequent system.

すなわち、入力パルス列から雑音成分を除去するフィル
タ効果がある。
That is, there is a filter effect of removing noise components from the input pulse train.

ただし、信号成分N5と雑音成分ΔNとの値にあまり相
違のないときは、本発明の確率制御フィルタの入出力間
の線型性は直線的でなくなる。
However, when there is not much difference between the values of the signal component N5 and the noise component ΔN, the linearity between the input and output of the stochastic control filter of the present invention is no longer linear.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は第1
図に示す実施例の動作タイムチャートである。 1a・・・パルス列入力端、1b・・・パルス列入力タ
イミング信号入力端、2・・・パルス除去回路、2a・
・・アップダウンカウンタ、2b、3b・・・単安定マ
ルチバイブレータ、2c、2d・・・ANDゲート、3
・・・パルス付加回路、3a・・・ORゲート、4・・
・パルス列出力端。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is an operation time chart of the embodiment shown in the figure. 1a... Pulse train input terminal, 1b... Pulse train input timing signal input terminal, 2... Pulse removal circuit, 2a...
...up-down counter, 2b, 3b...monostable multivibrator, 2c, 2d...AND gate, 3
...Pulse addition circuit, 3a...OR gate, 4...
・Pulse train output terminal.

Claims (1)

【特許請求の範囲】[Claims] 入力した第1のパルス列のパルス数Nがあらかじめ定め
たパルス数nより大きいとき前記第1のパルス列からn
個のパルスを除去してパルス数N−nの第2のパルス列
を出力し等しいか小さいときはパルス数0のパルス列を
前記第2のパルス列として出力する第1の手段と、前記
第2のパルス列にあらかじめ定めたm個のパルスを付加
してパルス数N−n+m又はパルス数mの第3のパルス
列を出力する第2の手段とを備えたことを特徴とする確
率制御フィルタ。
When the number N of pulses of the input first pulse train is larger than the predetermined number n of pulses, n from the first pulse train
a first means for outputting a second pulse train with a number of pulses N-n by removing the pulses, and outputting a pulse train with a number of pulses of 0 as the second pulse train when the number of pulses is equal to or smaller than the second pulse train; and second means for adding a predetermined m number of pulses to the output to output a third pulse train having the number of pulses N-n+m or the number of pulses m.
JP1185428A 1989-07-17 1989-07-17 Probability control filter Pending JPH0349314A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1185428A JPH0349314A (en) 1989-07-17 1989-07-17 Probability control filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1185428A JPH0349314A (en) 1989-07-17 1989-07-17 Probability control filter

Publications (1)

Publication Number Publication Date
JPH0349314A true JPH0349314A (en) 1991-03-04

Family

ID=16170614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1185428A Pending JPH0349314A (en) 1989-07-17 1989-07-17 Probability control filter

Country Status (1)

Country Link
JP (1) JPH0349314A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008136203A1 (en) * 2007-05-01 2010-07-29 日立建機株式会社 Construction machinery

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2008136203A1 (en) * 2007-05-01 2010-07-29 日立建機株式会社 Construction machinery

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