JPH06338773A - Bipolar clock disturbance detection circuit - Google Patents

Bipolar clock disturbance detection circuit

Info

Publication number
JPH06338773A
JPH06338773A JP14709393A JP14709393A JPH06338773A JP H06338773 A JPH06338773 A JP H06338773A JP 14709393 A JP14709393 A JP 14709393A JP 14709393 A JP14709393 A JP 14709393A JP H06338773 A JPH06338773 A JP H06338773A
Authority
JP
Japan
Prior art keywords
pulse
detection circuit
bipolar
polarity pulse
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14709393A
Other languages
Japanese (ja)
Other versions
JP2947003B2 (en
Inventor
康紀 ▲高▼橋
Yasunori Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5147093A priority Critical patent/JP2947003B2/en
Publication of JPH06338773A publication Critical patent/JPH06338773A/en
Application granted granted Critical
Publication of JP2947003B2 publication Critical patent/JP2947003B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522Test of Sequential circuits
    • G01R31/318527Test of counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To detect the disturbance of a bipolar clock without using a phase locked oscillation circuit and to switch a reference clock before the influence of disturbance is applied to a following circuit, etc. CONSTITUTION:A positive polarity pulse detection circuit 1 outputs a signal S1 in which only the positive polarity pulse of an input bipolar clock is sampled, and a negative polarity pulse detection circuit 2 outputs a signal S2 in which only the negative polarity pulse of the input bipolar clock is sampled. A counter 3 counts up by clocking the output signal S1 of the positive polarity pulse detection circuit 1, and a counter 4 counts up by clocking the output signal S2 of the negative polarity pulse detection circuit 2. A comparator 5 issues an alarm when either the count results of the counters 3, 4 exceeds a threshold value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はバイポーラクロック擾乱
検出回路に関し、特にバイポーラクロックの余剰パルス
やパルス欠落による擾乱の検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar clock disturbance detection circuit, and more particularly to a disturbance detection circuit for excessive pulses or missing pulses of a bipolar clock.

【0002】[0002]

【従来の技術】一般に、バイポーラクロックは、図2に
示すように、主クロックに装置内の基準位相を示すた
め、主クロックの偶数分周となる副クロックをバイポー
ラバイオレーションによって重畳している。
2. Description of the Related Art Generally, in a bipolar clock, as shown in FIG. 2, since a main clock indicates a reference phase in the apparatus, a sub clock, which is an even division of the main clock, is superimposed by bipolar violation.

【0003】従来、この種のバイポーラクロック擾乱検
出回路は、図3に示すように、バイポーラクロックから
正極性パルスのみを検出し、バイポーラ/ユニポーラ変
換して出力する正極性パルス検出回路1と、バイポーラ
クロックから負極性パルスのみを検出し、バイポーラ/
ユニポーラ変換して出力する負極性パルス検出回路2と
を有している。
Conventionally, a bipolar clock disturbance detection circuit of this type, as shown in FIG. 3, detects only a positive pulse from a bipolar clock, outputs a bipolar / unipolar converted positive polarity pulse detection circuit 1, and a bipolar pulse detection circuit 1. Only negative polarity pulse is detected from the clock, and bipolar /
It has a negative polarity pulse detection circuit 2 that outputs by unipolar conversion.

【0004】また、このバイポーラクロック擾乱検出回
路は正極性パルス検出回路1及び負極性パルス検出回路
2の出力を入力して基準位相指示信号を抽出するバイポ
ーラバイオレーション検出回路6と、この基準位相指示
信号に位相同期して同期はずれの警報を発出する位相同
期発振回路7とを有している。
Further, the bipolar clock disturbance detection circuit receives the outputs of the positive polarity pulse detection circuit 1 and the negative polarity pulse detection circuit 2 and extracts a reference phase instruction signal, and a bipolar violation detection circuit 6 and the reference phase instruction circuit. It has a phase-locked oscillation circuit 7 which issues phase-out alarm in synchronization with the signal.

【0005】正極性パルス検出回路1はバイポーラクロ
ックを入力して正極性パルスのみの信号S1 を出力し、
負極性パルス検出回路2はバイポーラクロックを入力し
て負極性パルスのみの信号S2 を出力する。
The positive polarity pulse detection circuit 1 inputs a bipolar clock and outputs a signal S1 of only positive polarity pulses,
The negative polarity pulse detection circuit 2 inputs a bipolar clock and outputs a signal S2 of only negative polarity pulses.

【0006】バイポーラバイオレーション検出回路6は
正極性パルス検出回路1からの正極性パルスのみの信号
S1 と負極性パルス検出回路2からの負極性パルスのみ
の信号S2 とを入力し、これらの信号S1 ,S2 からバ
イポーラバイオレーションを検出することによって基準
位相指示信号を出力する。位相同期発振回路7はこの基
準位相指示信号を入力し、位相同期を確立し、位相同期
がはずれた場合には警報を発出する。
The bipolar violation detection circuit 6 inputs the signal S1 of only the positive pulse from the positive pulse detection circuit 1 and the signal S2 of only the negative pulse from the negative pulse detection circuit 2, and these signals S1 , S2 detects the bipolar violation to output the reference phase indicating signal. The phase-locked oscillator circuit 7 receives this reference phase instruction signal, establishes the phase lock, and issues an alarm when the phase lock is lost.

【0007】[0007]

【発明が解決しようとする課題】上述した従来のバイポ
ーラクロック擾乱検出回路では、バイポーラクロックの
擾乱を位相同期発振回路を用いて検出しているので、回
路規模が大きくなるとともに、バイポーラクロックの擾
乱に対して位相同期がとれてしまう場合には警報が発出
されないという問題がある。
In the above-mentioned conventional bipolar clock disturbance detection circuit, since the disturbance of the bipolar clock is detected by using the phase-locked oscillation circuit, the circuit scale becomes large and the disturbance of the bipolar clock becomes large. On the other hand, there is a problem that the alarm is not issued when the phase synchronization is achieved.

【0008】そこで、本発明の目的は上記問題点を解消
し、位相同期発振回路を用いることなくバイポーラクロ
ックの擾乱を検出することができ、該擾乱の影響が後段
の回路に及ぶ前に基準クロックの切替え等を行うことが
できるバイポーラクロック擾乱検出回路を提供すること
にある。
Therefore, an object of the present invention is to solve the above problems and to detect a disturbance of a bipolar clock without using a phase-locked oscillator circuit. Before the influence of the disturbance reaches a circuit in a subsequent stage, the reference clock can be detected. It is an object of the present invention to provide a bipolar clock disturbance detection circuit capable of switching between the two.

【0009】[0009]

【課題を解決するための手段】本発明によるバイポーラ
クロック擾乱検出回路は、バイポーラ信号から正極性パ
ルスを検出する正極性パルス検出手段と、前記バイポー
ラ信号から負極性パルスを検出する負極性パルス検出手
段と、前記正極性パルス検出手段で検出された前記正極
性パルスを計数する正極性パルス計数手段と、前記負極
性パルス検出手段で検出された前記負極性パルスを計数
する負極性パルス計数手段と、前記正極性パルス計数手
段の計数値と前記負極性パルス計数手段の計数値との差
が予め設定された閾値以上となったか否かを判定する判
定手段と、前記判定手段で前記正極性パルス計数手段の
計数値と前記負極性パルス計数手段の計数値との差が前
記閾値以上と判定されたときに位相同期はずれの警報を
発出する手段とを備えている。
A bipolar clock disturbance detecting circuit according to the present invention comprises a positive pulse detecting means for detecting a positive pulse from a bipolar signal and a negative pulse detecting means for detecting a negative pulse from the bipolar signal. A positive pulse counting means for counting the positive pulse detected by the positive pulse detecting means, and a negative pulse counting means for counting the negative pulse detected by the negative pulse detecting means, Determination means for determining whether or not the difference between the count value of the positive polarity pulse counting means and the count value of the negative polarity pulse counting means is equal to or greater than a preset threshold value, and the positive polarity pulse counting by the determination means Means for issuing a warning of loss of phase synchronization when it is determined that the difference between the count value of the means and the count value of the negative polarity pulse counting means is equal to or more than the threshold value. Eteiru.

【0010】[0010]

【実施例】次に、本発明の一実施例について図面を参照
して説明する。
An embodiment of the present invention will be described with reference to the drawings.

【0011】図1は本発明の一実施例の構成を示すブロ
ック図である。図において、バイポーラクロック擾乱検
出回路は、バイポーラ信号から正極性パルスのみを検出
する正極性パルス検出回路1と、バイポーラ信号から負
極性パルスのみを検出する負極性パルス検出回路2と、
正極性パルス検出回路1の出力信号S1 をカウントする
カウンタ3と、負極性パルス検出回路2の出力信号S2
をカウントするカウンタ4と、カウンタ3,4の差が予
め定めた閾値を越えると警報を発出する比較回路5と、
正極性パルス検出回路1の出力信号S1 と負極性パルス
検出回路2の出力信号S2 とを入力して基準位相指示信
号を抽出するバイポーラバイオレーション検出回路6と
を有している。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a bipolar clock disturbance detection circuit includes a positive polarity pulse detection circuit 1 that detects only positive polarity pulses from a bipolar signal, a negative polarity pulse detection circuit 2 that detects only negative polarity pulses from a bipolar signal,
A counter 3 for counting the output signal S1 of the positive pulse detection circuit 1 and an output signal S2 of the negative pulse detection circuit 2
A counter 4 that counts a counter, and a comparator circuit 5 that issues an alarm when the difference between the counters 3 and 4 exceeds a predetermined threshold value.
It has a bipolar violation detection circuit 6 which receives the output signal S1 of the positive polarity pulse detection circuit 1 and the output signal S2 of the negative polarity pulse detection circuit 2 and extracts a reference phase instruction signal.

【0012】この図1を用いて本発明の一実施例の動作
について説明する。正極性パルス検出回路1は入力バイ
ポーラクロックの正極性パルスのみを抽出した信号S1
を出力し、負極性パルス検出回路2は入力バイポーラク
ロックの負極性パルスのみを抽出した信号S2 を出力す
る。
The operation of the embodiment of the present invention will be described with reference to FIG. The positive pulse detection circuit 1 is a signal S1 obtained by extracting only the positive pulse of the input bipolar clock.
And the negative pulse detection circuit 2 outputs a signal S2 obtained by extracting only the negative pulse of the input bipolar clock.

【0013】カウンタ3は正極性パルス検出回路1の出
力信号S1 をクロックとしてカウントアップし、カウン
タ4は負極性パルス検出回路2の出力信号S2 をクロッ
クとしてカウントアップする。これらカウンタ3,4は
所定のタイミングで同時にリセットされる。
The counter 3 counts up with the output signal S1 of the positive polarity pulse detection circuit 1 as a clock, and the counter 4 counts up with the output signal S2 of the negative polarity pulse detection circuit 2 as a clock. These counters 3 and 4 are simultaneously reset at a predetermined timing.

【0014】比較回路5はカウンタ3,4の計数結果を
入力し、これらの計数結果を比較する。カウンタ3,4
は交互にカウントアップするため、通常、カウンタ3,
4の計数結果はバイポーラバイオレーションによるずれ
以上にずれることはない。
The comparison circuit 5 inputs the counting results of the counters 3 and 4 and compares these counting results. Counters 3 and 4
Are counted up alternately, the counter 3,
The counting result of 4 does not shift more than the shift due to the bipolar violation.

【0015】しかしながら、入力バイポーラクロックに
擾乱が生じ、正極性パルスに余剰パルスの混入が発生し
た場合、カウンタ3は一定時間内に正常時よりも余剰パ
ルス分多くカウントするので、比較回路5においてカウ
ンタ4の計数結果とのずれが検出される。
However, when a disturbance occurs in the input bipolar clock and a surplus pulse is mixed in the positive polarity pulse, the counter 3 counts more surplus pulses than in a normal time within a fixed time. The deviation from the counting result of 4 is detected.

【0016】比較回路5に正常時のバイポーラバイオレ
ーションによるカウンタ3,4のずれを含んだ閾値を予
め定めておけば、上のような場合の計数結果のずれが閾
値を越えるため、比較回路5から警報が発出される。
If the threshold value including the deviation of the counters 3 and 4 due to the bipolar violation in the normal state is set in advance in the comparison circuit 5, the deviation of the counting result in the above case exceeds the threshold value. Gives an alarm.

【0017】また、負極性パルスに余剰パルスの混入が
発生した場合も、カウンタ4が一定時間内に正常時より
も余剰パルス分多くカウントするので、比較回路5から
警報が発出される。
Further, even when a surplus pulse is mixed in the negative polarity pulse, the counter 4 counts more surplus pulses than in a normal time within a fixed time, so that the comparison circuit 5 issues an alarm.

【0018】同様に、入力バイポーラクロックの擾乱に
よって正極性パルスまたは負極性パルスにパルスの欠落
を招いた場合にも、カウンタ3あるいはカウンタ4が正
常時よりも少なくカウントするので、比較回路5から警
報が発出される。
Similarly, when the positive polarity pulse or the negative polarity pulse is missing due to the disturbance of the input bipolar clock, the counter 3 or the counter 4 counts less than the normal time, and the comparator circuit 5 issues an alarm. Is issued.

【0019】このように、バイポーラクロックの正極性
パルス及び負極性パルスをカウンタ3,4で個別にカウ
ントし、これらカウンタ3,4の計数結果のずれが予め
定めた閾値を越えたときに比較回路5から警報を発出す
ることによって、位相同期発振回路を用いることなくバ
イポーラクロックの擾乱を検出することができ、該擾乱
の影響が後段の回路に及ぶ前に基準クロックの切替え等
を行うことができる。
In this way, the positive polarity pulse and the negative polarity pulse of the bipolar clock are individually counted by the counters 3 and 4, and when the deviation of the counting results of these counters 3 and 4 exceeds a predetermined threshold value, the comparison circuit. By issuing an alarm from 5, the disturbance of the bipolar clock can be detected without using the phase-locked oscillation circuit, and the reference clock can be switched before the influence of the disturbance reaches the circuit in the subsequent stage. .

【0020】また、カウンタ3,4及び比較回路5を用
いてバイポーラクロックの擾乱を検出するので、従来の
位相同期発振回路を用いた検出回路よりも回路規模を小
さくすることができる。
Further, since the disturbance of the bipolar clock is detected by using the counters 3 and 4 and the comparison circuit 5, the circuit scale can be made smaller than that of the conventional detection circuit using the phase-locked oscillation circuit.

【0021】[0021]

【発明の効果】以上説明したように本発明によれば、バ
イポーラ信号の正極性パルス及び負極性パルスを個別に
計数し、これら計数値の差が予め設定された閾値以上と
なったときに位相同期はずれの警報を発出することによ
って、位相同期発振回路を用いることなくバイポーラク
ロックの擾乱を検出することができ、該擾乱の影響が後
段の回路に及ぶ前に基準クロックの切替え等を行うこと
ができるという効果がある。
As described above, according to the present invention, the positive polarity pulse and the negative polarity pulse of the bipolar signal are individually counted, and when the difference between these count values exceeds a preset threshold value, the phase By issuing an out-of-synchronization alarm, the disturbance of the bipolar clock can be detected without using a phase-locked oscillator circuit, and the reference clock can be switched before the influence of the disturbance reaches the circuit in the subsequent stage. The effect is that you can do it.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示すブロック図であ
る。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【図2】バイポーラクロックと正極性パルスのみの信号
と負極性パルスのみの信号との波形例を示す図である。
FIG. 2 is a diagram showing waveform examples of a bipolar clock, a signal having only positive polarity pulses, and a signal having only negative polarity pulses.

【図3】従来例の構成を示すブロック図である。FIG. 3 is a block diagram showing a configuration of a conventional example.

【符号の説明】[Explanation of symbols]

1 正極性パルス検出回路 2 負極性パルス検出回路 3,4 カウンタ 5 比較回路 1 Positive pulse detection circuit 2 Negative pulse detection circuit 3, 4 Counter 5 Comparison circuit

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年12月17日[Submission date] December 17, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【特許請求の範囲】[Claims]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 バイポーラ信号から正極性パルスを検出
する正極性パルス検出手段と、前記バイポーラ信号から
負極性パルスを検出する負極性パルス検出手段と、前記
正極性パルス検出手段で検出された前記正極性パルスを
計数する正極性パルス計数手段と、前記負極性パルス検
出手段で検出された前記負極性パルスを計数する負極性
パルス計数手段と、前記正極性パルス計数手段の計数値
と前記負極性パルス計数手段の計数値との差が予め設定
された閾値以上となったか否かを判定する判定手段と、
前記判定手段で前記正極性パルス計数手段の計数値と前
記負極性パルス計数手段の計数値との差が前記閾値以上
と判定されたときに位相同期はずれの警報を発出する手
段とを有することを特徴とするバイポーラクロック擾乱
検出回路。
1. A positive polarity pulse detection means for detecting a positive polarity pulse from a bipolar signal, a negative polarity pulse detection means for detecting a negative polarity pulse from the bipolar signal, and the positive polarity detected by the positive polarity pulse detection means. Positive pulse counting means for counting the positive pulse, negative pulse counting means for counting the negative pulse detected by the negative pulse detecting means, count value of the positive pulse counting means and the negative pulse Determination means for determining whether or not the difference between the count value of the counting means and the preset threshold value or more,
And a means for issuing an alarm of out-of-phase synchronization when the difference between the count value of the positive polarity pulse counting means and the count value of the negative polarity pulse counting means is determined to be the threshold value or more by the determination means. Characteristic bipolar clock disturbance detection circuit.
JP5147093A 1993-05-26 1993-05-26 Bipolar clock disturbance detection circuit Expired - Lifetime JP2947003B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5147093A JP2947003B2 (en) 1993-05-26 1993-05-26 Bipolar clock disturbance detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5147093A JP2947003B2 (en) 1993-05-26 1993-05-26 Bipolar clock disturbance detection circuit

Publications (2)

Publication Number Publication Date
JPH06338773A true JPH06338773A (en) 1994-12-06
JP2947003B2 JP2947003B2 (en) 1999-09-13

Family

ID=15422323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5147093A Expired - Lifetime JP2947003B2 (en) 1993-05-26 1993-05-26 Bipolar clock disturbance detection circuit

Country Status (1)

Country Link
JP (1) JP2947003B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724207A2 (en) * 1995-01-27 1996-07-31 Nec Corporation Clock disturbance detection based on ratio of main clock and subclock periods
EP0797099A1 (en) * 1995-10-11 1997-09-24 The Nippon Signal Co. Ltd. Counter and a revolution stop detection apparatus using the counter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213350A (en) * 1986-03-13 1987-09-19 Nec Corp Signal transmission method in ping-pong transmission system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62213350A (en) * 1986-03-13 1987-09-19 Nec Corp Signal transmission method in ping-pong transmission system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724207A2 (en) * 1995-01-27 1996-07-31 Nec Corporation Clock disturbance detection based on ratio of main clock and subclock periods
EP0724207A3 (en) * 1995-01-27 1999-11-24 Nec Corporation Clock disturbance detection based on ratio of main clock and subclock periods
EP0797099A1 (en) * 1995-10-11 1997-09-24 The Nippon Signal Co. Ltd. Counter and a revolution stop detection apparatus using the counter
EP0797099A4 (en) * 1995-10-11 1998-12-30 Nippon Signal Co Ltd Counter and a revolution stop detection apparatus using the counter
US6148055A (en) * 1995-10-11 2000-11-14 The Nippon Signal Co., Ltd. Counter and a revolution stop detection apparatus using the counter
US6292524B1 (en) 1995-10-11 2001-09-18 The Nippon Signal Co., Ltd. Counting apparatus and rotation stopped detection apparatus which uses a counting apparatus

Also Published As

Publication number Publication date
JP2947003B2 (en) 1999-09-13

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