JPS6048684A - Television signal discriminating system - Google Patents

Television signal discriminating system

Info

Publication number
JPS6048684A
JPS6048684A JP58157393A JP15739383A JPS6048684A JP S6048684 A JPS6048684 A JP S6048684A JP 58157393 A JP58157393 A JP 58157393A JP 15739383 A JP15739383 A JP 15739383A JP S6048684 A JPS6048684 A JP S6048684A
Authority
JP
Japan
Prior art keywords
frequency
signal
horizontal synchronizing
circuit
synchronizing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58157393A
Other languages
Japanese (ja)
Other versions
JPH0226913B2 (en
Inventor
Toshio Hanabatake
花畑 利男
Nobuyuki Wada
和田 宜之
Toshiyuki Yamauchi
山内 利之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58157393A priority Critical patent/JPS6048684A/en
Publication of JPS6048684A publication Critical patent/JPS6048684A/en
Publication of JPH0226913B2 publication Critical patent/JPH0226913B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To attain picture transmission with good quality by providing a discriminating means using a horizontal synchronism or a subcarrier frequency as a reference and a means detecting and discriminating the missing or excess of a horizontal synchronizing signal so as to discriminate the signal based on an OR of both means. CONSTITUTION:Since the horizontal synchronizing signal 1 is inputted at a prescribed period of interval, a monostable multivibrator circuit MS continues the normal operation. If a pulse marked * in the horizontal synchronizing signal is missing because of some cause, the circuit MS is restored, an OR gate G generates an output signal 2, which informs a fault. Further, an oscillator OSC has a frequency smaller than the frequency of the horizontal synchronizing signal and its output resets always a counter circuit COUNTER. A pulse shown in dotted lines in the horizontal synchronizing signal is inserted because of some cause, the OR gate G generates an output signal 3 to inform the fault.

Description

【発明の詳細な説明】 (a)3発明の技術分野 本発明はテレビ信号判定方式に係り、特に画像符号化伝
送装置に於ける制御の方法を決定する為のテレビ信号判
定方式に関するものである。
Detailed Description of the Invention (a) 3 Technical Field of the Invention The present invention relates to a television signal determination method, and more particularly to a television signal determination method for determining a control method in an image coding and transmission device. .

(b)、従来技術の問題点 従来技術に依ると画像符号化伝送装置に於けるテレビ信
号判定回路としては、入力信号である水平同期信号又は
ザブ・キャリアの周波数に同期したクロックを作成し、
作成されたクロック周波数が成る規格内に有るか否かに
よって制御の方法を決定していた。
(b) Problems with the Prior Art According to the prior art, the television signal determination circuit in the image coding and transmission device creates a clock synchronized with the frequency of the horizontal synchronization signal or subcarrier, which is the input signal.
The control method was determined depending on whether the created clock frequency was within the specified specifications.

第1図は従来のテレビ信号判定回路の一実施例を示す。FIG. 1 shows an embodiment of a conventional television signal determination circuit.

図中、F−DIVIは1/2分周器、P −COMPは
位相比較器、L P Fは低域濾波器、VCOは電圧制
御発振器、F−D I V 2は1/n分周器、F−D
 ETは周波数検出回路である。
In the figure, F-DIVI is a 1/2 frequency divider, P-COMP is a phase comparator, LPF is a low-pass filter, VCO is a voltage controlled oscillator, and F-DIV 2 is a 1/n frequency divider. ,F-D
ET is a frequency detection circuit.

第1図に於いて、水平同期信号が1/2分周器F−DI
V1に入力され、位相比較器P−COMPに於いて1/
n分周器F−DIV2の出力信号との位相差を取り、低
域濾波器LPFにより其の内の直流成分のみを取り出し
て電圧制御発振器VCOの制御電圧とする。此の電圧制
御発振器VCOの出力周波数ばi/n分周器F−D I
 V 2により1/nに分周され、位相比較器P−CO
MPに入力される。
In Figure 1, the horizontal synchronizing signal is connected to the 1/2 frequency divider F-DI.
V1, and the phase comparator P-COMP outputs 1/
The phase difference with the output signal of the n frequency divider F-DIV2 is taken, and only the DC component is taken out by the low-pass filter LPF and used as the control voltage of the voltage controlled oscillator VCO. The output frequency of this voltage controlled oscillator VCO is the i/n frequency divider F-DI
The frequency is divided by 1/n by V2, and the phase comparator P-CO
Input to MP.

此の様な周知の位相同期回路により、入力の水平同期信
号又はサブ・キャリアの周波数に同期したクロックを発
生し、此のクロック周波数を周波数検出回路F−DET
に於いて計数し、其の周波数が規定の範囲内にあるか否
かにより伝送制御を変えていた。
A well-known phase synchronization circuit like this one generates a clock synchronized with the input horizontal synchronization signal or subcarrier frequency, and this clock frequency is sent to the frequency detection circuit F-DET.
The frequency was counted, and transmission control was changed depending on whether the frequency was within a specified range.

即ちクロックが良好であれば、此のクロックでアナログ
信号をA −D変換し、此のクロックを使用して伝送〔
ロック形〕すれば、良好な画像を伝送出来る。
In other words, if the clock is good, the analog signal is A-D converted using this clock, and then transmitted using this clock.
lock type], good images can be transmitted.

然し此のクロックが規定に合致しない時は次善の策とし
て伝送装置のライン・クロックを使用してアナログ信号
をA −D変換し、伝送〔ノン・ロック形〕する。勿論
此の場合の画質は〔ロック形〕で良好なりロックを使用
する場合よりは画質が悪いがロック形で規定範囲外のク
ロックを使用する場合よりは良好である。
However, if this clock does not meet the regulations, the next best option is to use the line clock of the transmission device to A-to-D convert the analog signal and transmit it (non-lock type). Of course, the image quality in this case is good with the lock type, which is worse than when the lock is used, but it is better than when the lock type is used with a clock outside the specified range.

此の様な判定基準により制御の方法を変えると、クロッ
クが規定の周波数範囲内にあっても水平同期信号パルス
の一つが抜けたり、水平同期信号に異常パルスが挿入さ
れた時は、従来の方式では位相同期回路によりクロック
を作り出している為に、クロックが揺れてしまい精度の
良い信号源とはならず、此の為符号化する場合精度が良
いと見なして処理するロック形では逆にノン・ロック形
より画質が悪くなると云う欠点があった。
If the control method is changed using such judgment criteria, even if the clock is within the specified frequency range, if one of the horizontal synchronization signal pulses is missing or an abnormal pulse is inserted in the horizontal synchronization signal, the conventional In this method, the clock is generated by a phase synchronization circuit, so the clock fluctuates and is not a highly accurate signal source.For this reason, in the lock type, which is processed assuming high precision when encoding, conversely, it is non-conforming. -The drawback was that the image quality was worse than the lock type.

(C)3発明の目的 本発明の目的は従来技術の有する」二記の欠点を除去し
、良質の画像伝送を行うことを可能にするテレビ信号判
定回路を提供することである。
(C)3 Objects of the Invention An object of the present invention is to provide a television signal determination circuit that eliminates the two drawbacks of the prior art and enables high-quality image transmission.

(d)8発明の構成 上記の目的は本発明によれば、テレビ信号の精度を検出
し、検出された前記精度により異なる制御を行う画像符
号化伝送装置に於いて、前記精度のパラメータとして水
平同期信号又はザブ・キャリアの周波数を基準とする4
1J定手段と前記水平同期信号の欠落又は過剰を検出す
る判定手段を備え、前記両判定手段の論理和で判定を行
うことを特徴とするテレビ信号判定方式を提供すること
により達成される。
(d) 8 Structure of the Invention According to the present invention, the above object is to detect the precision of a television signal, and to provide a horizontal 4 based on the frequency of the synchronization signal or subcarrier
This is achieved by providing a television signal determination method characterized in that it comprises a 1J determining means and a determining means for detecting the absence or excess of the horizontal synchronizing signal, and the determination is made by the logical sum of both the determining means.

(e)0発明の実施例 第2図の(alは本発明の一実施例を示すブロック図で
あり、(blは本発明の詳細な説明する図である。
(e) 0 Embodiment of the Invention In FIG. 2, (al) is a block diagram showing an embodiment of the present invention, and (bl) is a diagram explaining the present invention in detail.

図中、MSはモノ・ステーブル・マルチハイブレーク回
路、OSCは発振器、C0UNTERば計数回路、Gば
オア・ゲートであり、其の他の記号数字は第1図の場合
と同一である。
In the figure, MS is a mono stable multi-high break circuit, OSC is an oscillator, C0UNTER is a counting circuit, G is an OR gate, and other symbols and numbers are the same as in FIG.

思下図に従って本発明の詳細な説明する。The present invention will be described in detail with reference to the schematic drawings.

第2図の(blに於いて、■は入力である水平同期信号
を示す。前述した様に従来は此の水平同期信号が位相同
期回路に印加されて水平同期信号に同期したクロックを
作り出し、其のクロックの周波数を周波数検出回路F−
DETで検査し、規定の周波数範囲外であれば、出力信
号を出し伝送制御を変更する。
In Figure 2 (bl), ■ indicates the input horizontal synchronization signal.As mentioned above, conventionally, this horizontal synchronization signal is applied to a phase synchronization circuit to generate a clock synchronized with the horizontal synchronization signal. The frequency of that clock is detected by a frequency detection circuit F-
It is inspected by DET, and if the frequency is outside the specified frequency range, an output signal is output and transmission control is changed.

本発明によると水平同期信号によりモノ・ステーブル・
マルチハイブレーク回路MSを起動し、其の動作時間は
水平同期信号パルスの間隔より幾分長く設定しである。
According to the present invention, mono, stable,
The multi-high break circuit MS is activated, and its operating time is set to be somewhat longer than the interval of horizontal synchronizing signal pulses.

此の水平同期信号は常に一定周期間隔で入力するので、
モノ・ステーブル・マルチバイブレータ回路MSは常時
動作を継続するが、此の水平同期信号の内、*印のパル
スが何等かの原因で欠落すると本発明ではモノ・ステー
ブル・マルチバイブレーク回路MSが復旧し、オア・ゲ
ー)Gは■に示す様に出力信号を発生して異常を知らせ
る。
This horizontal synchronization signal is always input at regular intervals, so
The mono-stable multi-vibrator circuit MS continues to operate at all times, but if the pulse marked with * is missing for some reason in this horizontal synchronization signal, the mono-stable multi-vibrator circuit MS is activated in the present invention. After recovery, G generates an output signal as shown in ■ to notify the abnormality.

尚位相同期回路は*印のパルスが欠落しても異常なく動
作を継続し、其の出力クロックの周波数は規定の規格内
に在ればテレビ信号は正常と判定する。
Note that the phase synchronization circuit continues to operate without any abnormality even if the pulse marked with * is missing, and if the frequency of its output clock is within the specified standard, the television signal is determined to be normal.

又発振器OSCは水平同期信号の周波数約15KHzよ
り少し小さい周波数を持ち、其の出力により計数回路C
0UNTERを常時リセットしている。
Also, the oscillator OSC has a frequency slightly lower than the frequency of the horizontal synchronizing signal, approximately 15 KHz, and its output causes the counting circuit C to
0UNTER is constantly reset.

又此の水平同期信号は此の計数回路C0IJNTERに
よりカウントされる。従って水平同期信号が正常に入力
されると、計数回路C0UNTERば発振器oSCによ
りリセットされ、水平同期信号パルスを1回計数して再
び発振器O3Cによりリセットされる動作を繰り返す。
Also, this horizontal synchronizing signal is counted by this counting circuit C0IJNTER. Therefore, when the horizontal synchronizing signal is normally input, the counting circuit C0UNTER is reset by the oscillator oSC, the horizontal synchronizing signal pulse is counted once, and the operation of being reset by the oscillator O3C is repeated.

此の為■の点線で示すパルスが何等かの原因で挿入され
た時は計数回路COU N T E Rの計数値は2以
トとなり、オア・ゲートGは■に示ず様に出力信号を発
生して異常を知らせる。
For this reason, when the pulse shown by the dotted line in ■ is inserted for some reason, the count value of the counting circuit COUNTER becomes 2 or more, and the OR gate G outputs the output signal as shown in ■. Occurs and reports an abnormality.

此の様に従来の周波数検出回路F−DETの出力信号に
よるだけでな(、本発明に依るモノ・ステーブル・マル
チハイブレーク回路MS、及び計数回路C0UNTER
の出力信号の何れが出ても制御モードを変更することに
より、より確度の高い判定を行うことが出来る。
In this way, not only the output signal of the conventional frequency detection circuit F-DET (mono stable multi-high break circuit MS and counting circuit C0UNTER according to the present invention)
By changing the control mode no matter which of the output signals is output, a more accurate determination can be made.

(f)1発明の効果 以上詳細に説明した様に本発明によれば、良質の画像伝
送を行うことを可能にするテレビ信号判定回路を実現出
来ると云う大きい効果がある。
(f) 1. Effects of the Invention As described in detail above, the present invention has the great effect of realizing a television signal determination circuit that enables high-quality image transmission.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のテレビ信号判定回路の一実施例を示す。 第2図の(alは本発明の一実施例を示す図、(blは
本発明の詳細な説明する図である。 図中、F−D I V 1ば1/2分周器、p−c。 MPは位相比較器、L P Fは低域濾波器、VC○は
電圧制御発振器、F−D I V 2は1/n分周器、
F−DETは周波数検出回路、MSはモノ・ステーブル
・マルチハイブレーク回路、OS C+−,L Q I
hy器、C0UNTERは計数回路、Gしまメ”−]′
・ケートである。
FIG. 1 shows an embodiment of a conventional television signal determination circuit. In FIG. 2, (al is a diagram showing one embodiment of the present invention, (bl is a diagram explaining the present invention in detail. In the figure, F-D IV 1/2 frequency divider, p- c. MP is a phase comparator, LPF is a low-pass filter, VC○ is a voltage controlled oscillator, F-D I V 2 is a 1/n frequency divider,
F-DET is a frequency detection circuit, MS is a mono/stable/multi-high break circuit, OS C+-, L Q I
hy device, C0UNTER is a counting circuit, G-shimame”-]’
・It is Kate.

Claims (1)

【特許請求の範囲】[Claims] テレビ信号の精度を検出し1.検出された前記精度によ
り異なる制御を行う画像符号化伝送装置に於いて、前記
精度のパラメータとして水平同期信号又はザブ・キャリ
アの周波数を基準とする判定手段と前記水平同期信号の
欠落又は過剰を検出する判定手段を備え、前記再判定手
段の論理和で判定を行うことを特徴とするテレビ信号判
定方式。
Detecting the accuracy of the television signal 1. In an image coding and transmission device that performs different control depending on the detected accuracy, a determination means uses a frequency of a horizontal synchronization signal or a subcarrier as a reference for the accuracy parameter, and detects omission or excess of the horizontal synchronization signal. 1. A television signal determination method, comprising a determination means for determining the re-determination means, and performing determination by a logical sum of the re-determination means.
JP58157393A 1983-08-29 1983-08-29 Television signal discriminating system Granted JPS6048684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58157393A JPS6048684A (en) 1983-08-29 1983-08-29 Television signal discriminating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58157393A JPS6048684A (en) 1983-08-29 1983-08-29 Television signal discriminating system

Publications (2)

Publication Number Publication Date
JPS6048684A true JPS6048684A (en) 1985-03-16
JPH0226913B2 JPH0226913B2 (en) 1990-06-13

Family

ID=15648647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58157393A Granted JPS6048684A (en) 1983-08-29 1983-08-29 Television signal discriminating system

Country Status (1)

Country Link
JP (1) JPS6048684A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62258571A (en) * 1986-02-06 1987-11-11 ドイチエ・トムソン−ブラント・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Circuit devicegenerating clock signal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778169U (en) * 1980-10-30 1982-05-14
JPS57200972U (en) * 1981-06-15 1982-12-21

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778169U (en) * 1980-10-30 1982-05-14
JPS57200972U (en) * 1981-06-15 1982-12-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62258571A (en) * 1986-02-06 1987-11-11 ドイチエ・トムソン−ブラント・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Circuit devicegenerating clock signal
JPH0553434B2 (en) * 1986-02-06 1993-08-10 Thomson Brandt Gmbh

Also Published As

Publication number Publication date
JPH0226913B2 (en) 1990-06-13

Similar Documents

Publication Publication Date Title
TW306111B (en)
US5025496A (en) Odd/even field detector for video signals
JPS6272279A (en) Vertical synchronizing signal detection circuit
KR970025148A (en) Error Detection Circuit of System Time Clock for MPEG System Decoder
GB2074810A (en) Colour framing signal generators
JPS6048684A (en) Television signal discriminating system
EP0756799B1 (en) Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device
US4631587A (en) Field responsive vertical pulse generator
JPS6170861A (en) Horizontal synchronization detecting circuit
JP2947003B2 (en) Bipolar clock disturbance detection circuit
JP2574896B2 (en) Field discriminator
JPS62175073A (en) Frame detecting circuit for television signal
JPS61261973A (en) Frame synchronizing separator circuit
JP2594904B2 (en) Video signal processing device
JPH0550188B2 (en)
KR920010322B1 (en) Frame pulse detecting circuit of hdtv
JP3054498B2 (en) Image display device and input signal determination circuit
JPH04324764A (en) Synchronization discrimination device
JPH0335675A (en) Pll circuit for video signal
JPS6347192B2 (en)
JPS60241393A (en) Deciding device of television signal field
JPH03214867A (en) Synchronizing signal detection circuit
JPH0522744A (en) Pll circuit
GB2274370A (en) Colour television signal subcarrier to horizontal sync (SCH) phase error correction
JPS6087573A (en) Field discrimination circuit