JPH0348433A - Semiconductor manufacturing device - Google Patents
Semiconductor manufacturing deviceInfo
- Publication number
- JPH0348433A JPH0348433A JP7068390A JP7068390A JPH0348433A JP H0348433 A JPH0348433 A JP H0348433A JP 7068390 A JP7068390 A JP 7068390A JP 7068390 A JP7068390 A JP 7068390A JP H0348433 A JPH0348433 A JP H0348433A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cushion member
- suction port
- semiconductor manufacturing
- negative pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000001179 sorption measurement Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 11
- 238000004891 communication Methods 0.000 abstract description 9
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000006260 foam Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 20
- 239000000428 dust Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005453 pelletization Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 241000219321 Caryophyllaceae Species 0.000 description 1
- 235000002845 Dianthus plumarius Nutrition 0.000 description 1
- GXCLVBGFBYZDAG-UHFFFAOYSA-N N-[2-(1H-indol-3-yl)ethyl]-N-methylprop-2-en-1-amine Chemical compound CN(CCC1=CNC2=C1C=CC=C2)CC=C GXCLVBGFBYZDAG-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 210000005226 corpus cavernosum Anatomy 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体製造装置に関し、
ピンクアップ時におけるＩＣチップ表面の損傷やチップ
の角の欠損を回避することを目的とし、ウェハから切り
出されたＩＣチップを負圧により吸引する吸引口を備え
た半導体製造装置において、前記吸引口に、前記ｒｃヂ
ソブ表面に付着したＳｔ片が透過できるような大きさを
有する透孔および柔軟性を有するクッション部材を設け
、該クソション部材を介してＩＣチップを吸引するよう
に構威したことを特徴とし、
または、前記クッション部材の少なくとも一部表面を非
切断加工面と゛し、該非切断加工面をＩＣチップ吸着面
として使用することを特徴とし、または、前記クッショ
ン部材の透孔をオープンセル構造としたことを特徴とす
る。[Detailed Description of the Invention] [Summary] Regarding semiconductor manufacturing equipment, an IC chip cut out from a wafer is suctioned by negative pressure for the purpose of avoiding damage to the surface of the IC chip and chipping of the corners of the chip during pink-up. In a semiconductor manufacturing apparatus equipped with a suction port, the suction port is provided with a through hole having a size such that the St piece attached to the surface of the RC disobject can pass through, and a flexible cushion member, and the suction member is or, at least a part of the surface of the cushion member is a non-cut surface, and the non-cut surface is used as an IC chip suction surface. Alternatively, the through hole of the cushion member has an open cell structure.
本発明は、ＩＣの組立時に使用される半導体製造装置に
関する．
一ａに、ＩＣチップをパフケージソグするためのプロセ
スすなわち組立は、大きく分けてウェハを１個づつのＩ
Ｃチップに分割するペレタイズ（あるいはダイシング）
工程、パンケージ上にＩＣチノプを搭載するボンディン
グ工程、パフケージの封止工程および仕上げ処理工程の
４工程からなる。The present invention relates to semiconductor manufacturing equipment used when assembling ICs. First, the process for puff cage sogging of IC chips, that is, assembly, can be broadly divided into
Pelletizing (or dicing) to divide into C chips
It consists of four steps: a bonding step for mounting the IC tinop on the pan cage, a puff cage sealing step, and a finishing treatment step.
第１０図は、ペレタイズ工程の細部工程を示す図である
。FIG. 10 is a diagram showing detailed steps of the pelletizing process.
ペレタイズ工程は、粘着テープによりウェハを保持し（
第１０図（ａ））、カツタブレードを使用してウェハを
切断し（第１０図（ｂ））、スピンスプレーによる洗浄
乾燥（第ｌＯ図（Ｃ））を行った後、突き上げピンによ
って押し上げられたＩＣチップをピンクアンプしてボン
ディング工程へと搬送する（第ｌＯ図（ｄ））もので、
上記ピックアップには、負圧吸引を行うコレフトが用い
られる。During the pelletizing process, the wafer is held with adhesive tape (
After cutting the wafer using a cutter blade (Fig. 10 (b)), cleaning and drying it by spin spray (Fig. 10 (C)), the wafer is pushed up by a push-up pin. The IC chip is pink-amplified and transported to the bonding process (Figure 1O (d)).
The pickup uses a core that performs negative pressure suction.
従来のこの種のコレフトとしては、平面コレソトおよび
角錐コレフトの２タイプが知られている。Two types of conventional corefts of this type are known: a flat coreft and a pyramidal coreft.
王Ｅ口Ｌｋ１ユー
第１１図において、コレフト１には、負圧用の連通路１
ａと、この連通路１ａを外部に開放する吸引口１ｂを有
する水平端面１ｃとが設けられている。吸引口ｔｂに負
圧を作用させることにより、この吸引口１ｂでＩＣチッ
プ表面を吸着しピンクアップする。In Fig. 11, the right 1 has a communication path 1 for negative pressure.
a, and a horizontal end surface 1c having a suction port 1b that opens the communication path 1a to the outside. By applying negative pressure to the suction port tb, the suction port 1b attracts the surface of the IC chip and pinks it up.
角ＩＬＬヒヱ』一
第１２図において、コレフト２には、負圧用の連通路２
ａと、この連通路２ａを外部に開放する角錐型の吸引口
２ｂとが設けられている。吸引口２ｂに負圧を作用させ
ることにより、この吸引口２ｂでＩＣヂフプの角を保持
しピソクアップする。In Fig. 12, the right 2 has a communication path 2 for negative pressure.
a, and a pyramid-shaped suction port 2b that opens the communication path 2a to the outside. By applying negative pressure to the suction port 2b, the suction port 2b holds the corner of the IC zipper and lifts it up.
しかしながら、このような従来の平面コレフトおよび角
錐コレントについては、それぞれ以下に述べるような不
具合があった。However, such conventional planar collefts and pyramidal corrents each have the following disadvantages.
王ＥヒＬｋｌ』−
ＩＣチップ表面にゴミ （硬目の異物で例えば、ダイシ
ング時に発生するＳｔ片）が残留していた場合、このゴ
ミがＩＣチップ表面に強く押し付けられる結果、ＩＣチ
ップ表面の保ａｒｔｓ ＜例えばＰＳＯ膜）を損傷させ
ることがあった．
なお、コレフトｌの材質を弾性的なものにすれば、上記
ゴミの押し付け力が弱められるので、チップ表面の損傷
を抑えることも可能と思われる．しかし、実際にはコレ
ット１の水平端面１ｃにゴミが付着しやすくなってしま
うために、ピックアップを繰り返していくと、水平端面
１ｃの残留ゴ稟量が増え、やはりＩＣチップ表面への損
傷は避けられない。- If dust (hard foreign particles, such as St pieces generated during dicing) remains on the IC chip surface, this dust will be strongly pressed against the IC chip surface, resulting in damage to the IC chip surface. arts <for example, the PSO film). It should be noted that if the material of the core left L is made of an elastic material, the pressing force of the above-mentioned dust will be weakened, so it may be possible to suppress damage to the chip surface. However, in reality, dirt tends to adhere to the horizontal end face 1c of the collet 1, so as the pickup is repeated, the amount of dirt remaining on the horizontal end face 1c increases, and damage to the IC chip surface is avoided. I can't.
互立２ｙＬ上
一方、このタイプのコレットにあっては、コレッ１・と
！Ｃチップが面接触しないので、上記平面コレソトの如
き不具合、すなわちゴミによるＩＣチップ表面の損傷は
発生しないものの、ＩＣチップの角を保持するために、
この角を欠損させる恐れがあった。On the other hand, for this type of collet, Collet 1! Since the C chip does not make surface contact, problems such as the above-mentioned flat surface, that is, damage to the IC chip surface due to dust, do not occur, but in order to hold the corners of the IC chip,
There was a risk that this corner would be lost.
本発明は、このような問題点に鑑みてなされたもので、
ピンクアンプ時におけるゴ暑によるチソプ表面の損傷や
チップの角の欠損を回避することを目的としている。The present invention was made in view of these problems, and
The purpose is to avoid damage to the chip surface and chipping of the tip corners due to heat during pink amplifier.
本発明は、上記目的を達威するためその原理措威を第１
図に示すように、ウェハから切り出されたＩＣチップを
負圧により吸引する吸引口を備えた半導体製造装置にお
いて、前記吸引口に、前記ＩＣチップ表面に付着したＳ
ｉ片が透過できるような大きさを有する透孔および柔軟
性を有するクソション部材を設け、該クッション部材を
介してＩＣチップを吸引するように構成している。In order to achieve the above-mentioned object, the present invention has the following principle and features as its first priority.
As shown in the figure, in a semiconductor manufacturing apparatus equipped with a suction port that suctions IC chips cut out from a wafer by negative pressure, S.
A through hole having a size that allows the i-piece to pass therethrough and a flexible cushion member are provided, and the IC chip is sucked through the cushion member.
また、好ましくは、前記クッシシン部材の少なくとも一
部表面を非切断加工面とし、該非切断加工面をＩＣチッ
プ吸着面として使用する。Preferably, at least a portion of the surface of the cushioning member is a non-cut surface, and the non-cut surface is used as an IC chip adsorption surface.
さらに、より好ましくは、前記クッション部材をオープ
ンセル構造とする。Furthermore, more preferably, the cushion member has an open cell structure.
本発明では、ＩＣチソブと吸引口との間に微小粒子（例
えば、Ｉｃチップ表面のＳｉ片）に対して透過性かつ柔
軟性を有するクッション部材が介装される。In the present invention, a cushion member that is permeable to microparticles (for example, Si pieces on the surface of the IC chip) and flexible is interposed between the IC chip and the suction port.
したがって、負圧吸引時にＩＣチップが弾性的に面保持
されるとともに、吸引力によってＩＣチソプ表面のゴミ
（異物であり例えばＳｉ片）がクッション部材を難なく
通過させられる結果、このゴミに起因するＩＣチップ表
面の損傷が回避される。Therefore, when the IC chip is suctioned by negative pressure, the IC chip is elastically held flat, and the suction force allows dust (foreign matter, such as Si pieces) on the surface of the IC chips to pass through the cushion member without difficulty. Damage to the chip surface is avoided.
これは、第２図に示すように、ＩＣチップ表面に例えば
Ｓｉ片等の異物があった場合、このＳｔ片が負圧吸引に
よってクソション部材を通り抜けることができる（第３
図参照）からで、これにより、ＩＣヂソプ表面からＳｉ
片等の微小粒子の異物を取り除くことができるからであ
る。This is because, as shown in Fig. 2, if there is a foreign object such as a Si piece on the IC chip surface, this St piece can pass through the suction member by negative pressure suction (the third
(see figure), and as a result, Si is removed from the IC disop surface.
This is because foreign matter such as particles and other fine particles can be removed.
なお、好ましい構成によると、前記クッション部材のＩ
Ｃチップ吸着面がトゲのない平滑面となってＩＣヂップ
表面へのダメージがより確実に回避され、また、オープ
ンセル構造の透孔を介してゴミの負圧吸引がスムーズに
なされる。In addition, according to a preferable configuration, the I of the cushion member
The C-chip suction surface becomes a smooth surface without thorns, thereby more reliably avoiding damage to the IC chip surface, and vacuum suction of dust is smoothly achieved through the through holes of the open cell structure.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第４図は本発明に係る半導体製造装置の第１実施例を示
す図である。FIG. 4 is a diagram showing a first embodiment of the semiconductor manufacturing apparatus according to the present invention.
第４図において、４はコレントであり、コレソト４は負
圧用の連通路５ａを形成した円筒体５を有している。こ
の連通路５ａの一端は吸引口５ｂを形威し、吸引口５ｂ
の周囲にはホルダ一部５Ｃが形威されている。そして、
ホルダ一部５Ｃにはクッション部材６が取り付けられて
いる。In FIG. 4, reference numeral 4 indicates a collet, and the collet 4 has a cylindrical body 5 in which a communication passage 5a for negative pressure is formed. One end of this communication path 5a forms a suction port 5b, and the suction port 5b
A holder portion 5C is formed around the holder. and,
A cushion member 6 is attached to the holder portion 5C.
ここで、クッション部材６には、例えば、海綿体、スポ
ンジ若しくは軟質ウレタンフォームを用いるのが好まし
い。要は、柔軟性を有するもので、かつ、内部に多数の
コア（気泡若しくは空洞）が形威され、コア間が一部で
連通しているとともに、少なくともコアの大きさあるい
は連通部の開口が異物の大きさに相当する大きさく例え
ば異物をＳｉ片とすると５００μφ程度）であればよい
。Here, for the cushion member 6, it is preferable to use, for example, corpus cavernosum, sponge, or soft urethane foam. In short, it is flexible, has many cores (bubbles or cavities) inside, and communicates between the cores in some areas, and at least the size of the cores or the opening of the communication part is It is sufficient if the size corresponds to the size of the foreign object (for example, if the foreign object is a piece of Si, about 500 μφ).
したがって、これらの条件に合致したクッション部ｔオ
６は、ｔＣチップ表面に付着したＳｉ片が透過できるよ
うな大きさの透孔を有するとともに、かつ柔軟性を有す
るものである。Therefore, the cushion part 6 that meets these conditions has a through hole large enough to allow the Si pieces attached to the surface of the tC chip to pass therethrough, and has flexibility.
このような構成によれば、クッション部材６を介してＩ
Ｃチップを吸引するので吸引時の衝撃を緩和できる。ま
た、ＩＣチップを面保持できるので、ＩＣチップの角を
欠損することはない。さらに、ＩＣチップの表面に異物
が存在していた場合には、この異物がクッション部材６
を通り抜けて負圧吸引されるので、異物によるチップ表
面の損傷を回避できるといった諸効果が得られる。According to such a configuration, the I
Since the C-tip is suctioned, the shock during suction can be alleviated. Furthermore, since the IC chip can be held face-to-face, the corners of the IC chip will not be damaged. Furthermore, if there is any foreign matter on the surface of the IC chip, this foreign matter may cause damage to the cushion member 6.
Since negative pressure is sucked through the chip, various effects can be obtained such as being able to avoid damage to the chip surface due to foreign matter.
なお、本発明は、従来の平面コレソトおよび角錐コレソ
トに適用することもできる。It should be noted that the present invention can also be applied to conventional flat surfaces and pyramidal surfaces.
第５図は本発明に係る半導体製造装置の第２実施例を示
す角錐コレソ１へへの適用例であり、（角錐〉コレソト
２の吸引口２ｂに第ｌ実施例と同様な材料からなるクソ
ション部材１０を取り付けたものである。また、第６図
は本発明に係る半導体製造装置の第３実施例を示す平面
コレフトへの適用例であり、（平面）コレソト１の吸引
口１ｂに第１実施例と同様な材料からなるクッション部
材２０を取り付けたものである。これら第２、第３実施
例によれば、従来の角錐および平面コレソトにクッショ
ン部材１０、２０を取り付けるだけの簡単な改修でよく
、コス！・の面や既存設備の再利用の面で好ましい。FIG. 5 shows an example of application to a pyramid core 1 showing a second embodiment of the semiconductor manufacturing apparatus according to the present invention. The member 10 is attached.Furthermore, FIG. 6 shows an example of application to a flat core showing the third embodiment of the semiconductor manufacturing apparatus according to the present invention. A cushion member 20 made of the same material as in the embodiment is attached.According to these second and third embodiments, a simple modification can be made by simply attaching the cushion members 10 and 20 to the conventional pyramidal and flat surfaces. It is preferable in terms of cost and reuse of existing equipment.
なお、本発明に係るコレソトは、ダイシング装置に設け
られたものを指すことは勿論のことであるが、この他に
も、ＩＣチップを手動によりピックアップする例えば注
射針状の専用二一ドルをコレソトにも適用できる。要は
、ＩＣチップを負圧力によって吸引保持するものであれ
ば全てに適用でき、例えば、グイボンディング工程のピ
ンクアンプコレフトにも適用できる。It should be noted that the term "choresoto" according to the present invention naturally refers to the one provided in the dicing device, but it also refers to the colesoto for manually picking up IC chips. It can also be applied to In short, it can be applied to anything that suctions and holds an IC chip with negative pressure, and for example, it can also be applied to a pink amplifier core left in a bonding process.
第７〜９図は、本発明に係る半導体製造装置の第４〜６
実施例をそれぞれ示す図であり、第７図は、前記第１実
施例のクンション部材６に開口６ａを形威したもの、第
８図は前記第２実施例のクッション部材１０に開口１０
ａを形成したもの、第９図は前記第３実施例のクソショ
ン部材２０に開口２０ａを形成したものであり、これら
の第４〜６実施例によれば、コアに比して充分に大きな
開口６ａ、ｌＱａ、２０ａを形成したので、チップ表面
のゴご例えばＳｉ片等をより効果的に吸引できるととも
に、比較的に大きなゴミを吸引することもできる．ここ
で、前記の各クッション部材６、１０、２０の少なくと
も一部表面を非切断加工面とし、該非切断加工面をＩＣ
チップ吸着面として使用すると好ましい。すなわち、型
枠内に発泡性材料を流し込んで製造する例えばスポンジ
は、その形状がコレソ１・先端に比べて充分に大きいの
で、所望の形状にするにはカッター等による切断加工を
要する。7 to 9 show the fourth to sixth parts of the semiconductor manufacturing apparatus according to the present invention.
FIG. 7 shows the cushion member 6 of the first embodiment with an opening 6a, and FIG. 8 shows the cushion member 10 of the second embodiment with the opening 10.
FIG. 9 shows an opening 20a formed in the suspension member 20 of the third embodiment, and according to these fourth to sixth embodiments, the opening 20a is sufficiently large compared to the core. 6a, lQa, and 20a, it is possible to more effectively suck up dirt such as Si pieces on the chip surface, and it is also possible to suck up relatively large dirt. Here, at least a part of the surface of each of the cushion members 6, 10, and 20 is an uncut surface, and the uncut surface is an IC.
It is preferable to use it as a chip adsorption surface. That is, for example, a sponge manufactured by pouring a foaming material into a mold is sufficiently larger than the tip of Coreso 1, so cutting with a cutter or the like is required to obtain the desired shape.
しかし、切断加工されたスポンジの切断面は平滑ではな
く、トゲ状の凹凸を生じるから、このトゲによるＩＣチ
ップ表面のダメージが心配となる．型枠に接していた面
（非切断加工面）をそのままチップ吸着面に使用すれば
上記心配を解消できる。However, the cut surface of the cut sponge is not smooth and has thorn-like unevenness, and there is concern that the thorns may damage the IC chip surface. The above concerns can be resolved by using the surface that was in contact with the formwork (uncut surface) as the chip suction surface.
また、クソション部材６、１０、２０を以下に述べるオ
ープンセル構造にすると、ゴミの負圧吸引がスムーズに
行われるので好ましい。すなわち、例えば、スポンジに
は、■多数のセル同士を薄膜で仕切ったクローズドセル
構造のもの（一般的なスポンジ）と、■セル間の薄膜を
一部だけにしたオープンセル構造のもの（例えばイノア
ソク社製のモルトフィルター）とがある。■をクッショ
ン部材に用いた場合には、初期のゴミ吸引を支障なく行
えるものの、残留ゴミの増加にともなって吸引効率が低
下する欠点がある。これに対し、■をクッション部材に
用いた場合には、残留ゴミが生しない（あるいは生じて
も僅かな量である）から、吸引効率を長時間に亘って良
好に維持できる効果がある。Further, it is preferable that the suction members 6, 10, and 20 have an open cell structure as described below, since the negative pressure suction of dust can be performed smoothly. For example, there are two types of sponges: ■ One with a closed cell structure in which many cells are separated by a thin film (general sponge), and ■ The one with an open cell structure in which only a portion of the thin film is separated between cells (for example, Inoaso sponge). There is a malt filter made by the company. When (2) is used for the cushion member, although the initial dust suction can be performed without any problem, there is a drawback that the suction efficiency decreases as the amount of residual dust increases. On the other hand, when (2) is used in the cushion member, no residual dust is generated (or even if it is, only a small amount is generated), so that the suction efficiency can be maintained satisfactorily over a long period of time.
本発明によれば、クッション部材を介してＩＣチップを
負圧吸引するようにしたので、ピ・７クアソプ時におけ
るゴミによるチップ表面のｔ貝傷やチップの角の欠損を
回避することができる．According to the present invention, since the IC chip is suctioned under negative pressure through the cushion member, it is possible to avoid scratches on the surface of the chip and damage to the corners of the chip due to dust during piping/seven cleaning.
第１〜３図は本発明の原理を説明する図であり、第ｌ図
はその原理構成図、
第２図はそのＩＣチップ上の異物を示す図、第３図はそ
のクッション部材を通り抜けた異物を示す図である。
第４図は本発明に係る半導体製造装置の第１実施例を示
すその構成図である。
第５図は本発明に係る半導体製造装置の第２実施例を示
すその構成図である。
第６図は本発明に係る半導体製造装置の第３実施例を示
すその構成図である。
第７図は本発明に係る半導体製造装置の第４実施例を示
すその構威図である。
第８図は本発明に係る半導体製造装置の第５実施例を示
すその構或図である。
第９図は本発明に係る半導体製造装置の第６実施例を示
すその構成図である。
第１０−１２図は従来例を示す図であり、第１０図はそ
のグイシング工程を示す工程図、第１１図はその平面コ
レットの構成図、第１２図はその角錐コレットの購或図
である。
４・・・・・・コレソト、
５ｂ・・・・・・吸引口、
６、１０、２０・・・・・・クッション部材。
命、７７負圧
本発明の原理構成図
第
エ
図
ＩＣチップ上の異物を示す図
第
２
図
クッション部材を通り抜けた異物を示す図第
３
図
５ｂ：吸引口
第ｌ実施例の構戒図
第
４
図
第２実施例の構成図
第５図
第３実施例の構戒図
第６図
第６実施例の構威図
第
９
図
従来のグイソング工程を示す工程図
第
１０
図Figures 1 to 3 are diagrams explaining the principle of the present invention, Figure 1 is a diagram showing its principle configuration, Figure 2 is a diagram showing foreign matter on the IC chip, and Figure 3 is a diagram showing foreign matter passing through the cushion member. It is a figure showing a foreign object. FIG. 4 is a block diagram showing a first embodiment of a semiconductor manufacturing apparatus according to the present invention. FIG. 5 is a configuration diagram showing a second embodiment of the semiconductor manufacturing apparatus according to the present invention. FIG. 6 is a configuration diagram showing a third embodiment of the semiconductor manufacturing apparatus according to the present invention. FIG. 7 is a structural diagram showing a fourth embodiment of the semiconductor manufacturing apparatus according to the present invention. FIG. 8 is a diagram showing the structure of a fifth embodiment of the semiconductor manufacturing apparatus according to the present invention. FIG. 9 is a block diagram showing a sixth embodiment of the semiconductor manufacturing apparatus according to the present invention. Figures 10-12 are diagrams showing a conventional example, Figure 10 is a process diagram showing the guising process, Figure 11 is a configuration diagram of the flat collet, and Figure 12 is a purchasing diagram of the pyramidal collet. . 4...Cole soto, 5b...Suction port, 6, 10, 20...Cushion member. Life, 77 Negative Pressure Principle of the present invention Fig. E Fig. 2 showing a foreign object on the IC chip Fig. 3 showing a foreign object passing through the cushion member 4 Figure 5. Structure diagram of the second embodiment Figure 5. Structure diagram of the third embodiment Figure 6. Structure diagram of the sixth embodiment Figure 9 Process diagram showing the conventional Guisong process Figure 10
Claims (3)
吸引する吸引口を備えた半導体製造装置において、 前記吸引口に、前記ＩＣチップ表面に付着したＳｉ片が
透過できるような大きさを有する透孔および柔軟性を有
するクッション部材を設け、該クッション部材を介して
ＩＣチップを吸引するようにしたことを特徴とする半導
体製造装置。(1) In a semiconductor manufacturing device equipped with a suction port that suctions IC chips cut out from a wafer by negative pressure, the suction port is provided with a transparent hole having a size that allows Si pieces attached to the surface of the IC chip to pass through. 1. A semiconductor manufacturing apparatus, comprising: a cushion member having a hole and flexibility; and an IC chip is sucked through the cushion member.
断加工面とし、該非切断加工面をＩＣチップ吸着面とし
て使用することを特徴とする請求項１記載の半導体製造
装置。(2) The semiconductor manufacturing apparatus according to claim 1, wherein at least a portion of the surface of the cushion member is a non-cutting processed surface, and the non-cutting processed surface is used as an IC chip adsorption surface.
したことを特徴とする請求項１または２記載の半導体製
造装置。(3) The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the through hole of the cushion member has an open cell structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7068390A JP2510024B2 (en) | 1989-04-05 | 1990-03-20 | Semiconductor manufacturing equipment |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-86357 | 1989-04-05 | ||
| JP8635789 | 1989-04-05 | ||
| JP7068390A JP2510024B2 (en) | 1989-04-05 | 1990-03-20 | Semiconductor manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0348433A true JPH0348433A (en) | 1991-03-01 |
| JP2510024B2 JP2510024B2 (en) | 1996-06-26 |
Family
ID=26411816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7068390A Expired - Fee Related JP2510024B2 (en) | 1989-04-05 | 1990-03-20 | Semiconductor manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2510024B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040018958A (en) * | 2002-08-26 | 2004-03-04 | 닛토덴코 가부시키가이샤 | Collet and method of picking up chip components using same |
| WO2006011319A1 (en) * | 2004-07-29 | 2006-02-02 | Japan Science And Technology Agency | Die bonder for laser crystal |
| JP2008085354A (en) * | 2007-10-22 | 2008-04-10 | Toshiba Corp | Semiconductor manufacturing device |
-
1990
- 1990-03-20 JP JP7068390A patent/JP2510024B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040018958A (en) * | 2002-08-26 | 2004-03-04 | 닛토덴코 가부시키가이샤 | Collet and method of picking up chip components using same |
| JP2004087677A (en) * | 2002-08-26 | 2004-03-18 | Nitto Denko Corp | Collet and method for picking up chip part using the same |
| WO2006011319A1 (en) * | 2004-07-29 | 2006-02-02 | Japan Science And Technology Agency | Die bonder for laser crystal |
| JP2008085354A (en) * | 2007-10-22 | 2008-04-10 | Toshiba Corp | Semiconductor manufacturing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2510024B2 (en) | 1996-06-26 |
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