JPS62181869A - Polishing of semiconductor wafer - Google Patents

Polishing of semiconductor wafer

Info

Publication number
JPS62181869A
JPS62181869A JP61020970A JP2097086A JPS62181869A JP S62181869 A JPS62181869 A JP S62181869A JP 61020970 A JP61020970 A JP 61020970A JP 2097086 A JP2097086 A JP 2097086A JP S62181869 A JPS62181869 A JP S62181869A
Authority
JP
Japan
Prior art keywords
wafer
polishing
plate
vacuum
wax
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61020970A
Other languages
Japanese (ja)
Inventor
Takayuki Nishiura
隆幸 西浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP61020970A priority Critical patent/JPS62181869A/en
Publication of JPS62181869A publication Critical patent/JPS62181869A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To permit the polishing free from the dispersion of thickness of a wafer by a shortened process by carrying out the surface grinding and polishing for the wafer in the vacuum adsorbed state and press-attaching said wafer onto a polishing plate. CONSTITUTION:A wafer 2 having the minute unevenness on the surface is fixed firmly and in separable ways by the vacuum attraction through a number of vacuum attraction holes 3, onto the surface plate 1 of a surface grinder. In this state, a rotary grindstone 4 is shifted horizontally along the diameter of the wafer 2, and after the back surface of the wafer 2 is ground a buffing surface plate 5 for polishing is attached, and the back surface of the wafer 2 is polished flat. Then, the coating of wax 6 is carried out, and a polishing plate 7 is pressing-attached, and then a vacuum chuck is released to separate the wafer 2 from the surface plate 1 of the surface grinder. Thus, the wafer free from the dispersion of thickness can be polished flat by the shortened process.

Description

【発明の詳細な説明】 (ト)技術分野 この発明は半導体ウェハの研磨方法に関する。[Detailed description of the invention] (g) Technical field The present invention relates to a method for polishing semiconductor wafers.

半導体ウェハは、GaAs 、 GaP 、  InP
 、 Si 1Geなどの単結晶インゴットを切断して
、薄い円板状としたものである。ウェハプロセスを精度
良く行なうために、ウェハ表面は鏡面に研磨しなければ
ならない。
Semiconductor wafers include GaAs, GaP, InP
, Si 1Ge, etc., is cut into a thin disk shape. In order to perform wafer processing with high precision, the wafer surface must be polished to a mirror surface.

ピ)従来技術 ステンレス、セラミックなどで作られた平坦度のよい研
磨プレートを加熱し、ワックスを溶融し、ここへウェハ
を置いて上から押圧することにヨリ、ウェハを研磨プレ
ートに貼付ける。この後、ウェハ面をラッピングし、或
はポリッシングする。
B) Conventional technology A polishing plate with good flatness made of stainless steel, ceramic, etc. is heated to melt the wax, and the wafer is placed on it and pressed from above to attach the wafer to the polishing plate. After this, the wafer surface is lapped or polished.

この方法であると、ウェハが面内で彎曲したりすること
がある。ワックスの厚みが一様にならないからである。
With this method, the wafer may be curved within the plane. This is because the thickness of the wax is not uniform.

特開昭56−164585 (昭和56年12月17日
公開)は、ワックスの厚みの非一様性の問題を解決する
ために、ウェハをまず真空チャックし、これを加熱し、
回転しながらワックスを塗布し、ワックスの上から研磨
プレートを置いて、ウェハに貼り付ける方法を提案して
いる。ウェハは真空チャックの平面によって、平坦とな
り、この上にワックスを回転塗布するから、ワックス厚
みが一様になる。このため、ワックス、ウェハが研磨プ
レートの上に平面度良く固着されることになる。
Japanese Patent Application Laid-Open No. 56-164585 (published on December 17, 1981) discloses that in order to solve the problem of non-uniformity in wax thickness, a wafer is first vacuum chucked, then heated,
The company proposes a method in which wax is applied while rotating, a polishing plate is placed on top of the wax, and the polishing plate is attached to the wafer. The wafer is flattened by the plane of the vacuum chuck, and the wax is spin-coated on top of it, so that the wax has a uniform thickness. Therefore, the wax and wafer are fixed on the polishing plate with good flatness.

いずれにしても、ウェハの片面だけをラップするもので
ある。
In either case, only one side of the wafer is lapped.

この種の片面ラップ方法では、研磨プレートに、1枚ず
つウェハを貼り付けるため、ウェハの厚みバラツキが1
0μm以上あれば、片面ラップでの精度がでない。この
ため前段階として、平面研削または両面ラップ工程が必
要であった。
In this type of single-sided lapping method, the wafers are attached one by one to the polishing plate, so the variation in wafer thickness is reduced by 1.
If it is 0 μm or more, the accuracy of single-sided lapping will be poor. Therefore, a surface grinding or double-sided lapping process was required as a preliminary step.

また、ウェハの平面研削を行なう場合、ウェハを研削し
た後、このウェハは定盤から外され、再び定盤に吸着さ
れ貼付けられるため、ウェハの定盤&m接する面の凹凸
が大きいと、ウェハに8μm程度の凹凸、或はデーパが
生じた。
In addition, when performing surface grinding of a wafer, after the wafer is ground, the wafer is removed from the surface plate, and is adsorbed and attached to the surface plate again. An unevenness or taper of about 8 μm was generated.

これらの方法は、ウェハの厚みのバラツキや凹凸が残る
か、或は工程が複雑である、という難点がある。
These methods have disadvantages in that variations in wafer thickness and unevenness remain, or the process is complicated.

(つ)   目     的 厚みのバラツキのないウェハ研磨方法を提供する事が本
発明の第1の目的である。
(1) Purpose The first object of the present invention is to provide a method for polishing a wafer without variations in thickness.

短縮された工程によってウェハを平坦に研磨できる研磨
方法を提供することが本発明の第2の目的である。
A second object of the present invention is to provide a polishing method that can flatten a wafer through a shortened process.

に)本発明の方法 本発明は、これらの目的を達成するため、ウェハを真空
吸着したまま平面研削、及びポリッシュを行ない、その
まま研磨プレートに貼付けることとした。
B) Method of the Invention In order to achieve these objects, the present invention involves surface grinding and polishing the wafer while it is vacuum-adsorbed, and then attaching the wafer as it is to a polishing plate.

平面研削盤で、ウェハを真空吸着する方式のものが既に
市販されてはいる。この方式では、ウェハを平面研削し
加工後ウェハの吸着を解除し洗浄を行なう。
Surface grinders that vacuum-suction wafers are already on the market. In this method, the wafer is surface ground, and after processing, the wafer is released from suction and cleaned.

しかし、この方法は、■ウェハを薄くはできるが、削っ
た面にダメージが残る■ダメージが残ったまま貼付ける
とウェハの精度が悪くなる■吸着を1度解除し、再び貼
付けるため、貼付精度が悪くなるといった欠点がある。
However, with this method, the wafer can be made thinner, but damage remains on the shaved surface; wafer accuracy deteriorates if pasted with damage remaining; It has the disadvantage of poor accuracy.

以下、図面によって本発明の詳細な説明すも第1図〜第
6図は本発明の工程を示す縦断面図である。
Hereinafter, the present invention will be described in detail with reference to the drawings, and FIGS. 1 to 6 are longitudinal cross-sectional views showing the steps of the present invention.

第1図に於て、平面研削定盤1に凹凸のあるウェハ2が
真空チャックによって固定されている。
In FIG. 1, a wafer 2 having projections and depressions is fixed to a surface grinding surface plate 1 by a vacuum chuck.

このため、平面研削定盤1のウェハ2が接する部分には
、充分な数の真空吸着穴3が穿孔され、この穴3は真空
に吸引される。ウエノ12の表面が平面研削定盤1に接
触する。
For this reason, a sufficient number of vacuum suction holes 3 are bored in the portion of the surface grinding surface plate 1 in contact with the wafer 2, and these holes 3 are vacuum-sucked. The surface of the wafer 12 comes into contact with the surface grinding plate 1.

ウェハの裏面が外部に露呈している。ウェハ2の表面に
は微少な凹凸が存在するが、空隙は僅かであり、充分な
数の真空吸着穴3があるから、ウェハ2は強固に固定さ
れる。従来法のようにワックスで固定するのではない。
The back side of the wafer is exposed to the outside. Although there are minute irregularities on the surface of the wafer 2, there are only a few voids and there are a sufficient number of vacuum suction holes 3, so the wafer 2 is firmly fixed. It is not fixed with wax like the traditional method.

従って、離脱工程が極めて簡単である。真空ポンプを止
めれば良いだけである。
Therefore, the detachment process is extremely simple. All you have to do is stop the vacuum pump.

もちろん、ワックスを介しているのではないから、機械
的な摩擦や強い接触によってウェハ表面の凸部に傷がつ
くこともあるが、表面は後にポリッシュするので差支え
ない。
Of course, since wax is not used, the protrusions on the wafer surface may be scratched due to mechanical friction or strong contact, but this is not a problem as the surface will be polished later.

真空チャックした状態で、第2図に示すように、平面研
削する。回転する研削砥石4をウェハ2の直径に沿って
水平に移動させウェハ裏面を研削する。これはウェハの
厚みを揃えるという意味もある。また、大きい凸部を除
くという作用がある。
In the vacuum chucked state, the surface is ground as shown in FIG. A rotating grinding wheel 4 is moved horizontally along the diameter of the wafer 2 to grind the back surface of the wafer. This also means making the wafers even in thickness. It also has the effect of removing large convex portions.

次に第3図に示すように、真空チャックしたまま、ポリ
ッシュ用パフ定盤5をウェハ2の裏面に当てて、これを
ポリッシュする。こうして、ウェハの裏面が平坦になる
。裏面が平坦であるという事は無意味な事ではない。
Next, as shown in FIG. 3, while vacuum chucked, a polishing puff surface plate 5 is applied to the back surface of the wafer 2 to polish it. In this way, the back side of the wafer becomes flat. The fact that the back side is flat is not meaningless.

ウェハ裏面に凹凸があると、この影響により、凹凸は従
った彎曲状態で研磨プレートにウェハが固定されるため
、表面ポリッシング後、ウェハを取外した時、表面に凹
凸が現われる。
If there are irregularities on the back surface of the wafer, the wafer is fixed to the polishing plate in a curved state according to the irregularities, so that when the wafer is removed after surface polishing, the irregularities appear on the surface.

またウェハ裏面が平坦であると、後にワックスを付けた
場合、ワックス厚みが均一になるという長所がある。
Further, if the back surface of the wafer is flat, there is an advantage that when wax is applied later, the wax thickness becomes uniform.

次に第4図に示すように、ウェハ2のポリッシュされた
裏面にワックス6を塗布する。ウェハ2は真空チャック
されたままである。
Next, as shown in FIG. 4, wax 6 is applied to the polished back surface of wafer 2. Wafer 2 remains vacuum chucked.

さらに、第5図に示すように、ワックス6の塗布された
ウェハ裏面に研磨プレート7を押しつける。こうして、
ウェハ裏面と研磨プレート7が貼付けられる。
Furthermore, as shown in FIG. 5, a polishing plate 7 is pressed against the back surface of the wafer coated with wax 6. thus,
The back surface of the wafer and the polishing plate 7 are attached.

真空チャックを解除する。ウェハ2の表面は平面研削定
盤1から離脱する。第6図はこのような状態を示す。こ
こで裏面は平坦であって、フックス6も平坦である。ウ
エノ・の厚みも揃っている。
Release the vacuum chuck. The surface of the wafer 2 is separated from the surface grinding surface plate 1. FIG. 6 shows such a situation. Here, the back surface is flat, and the hooks 6 are also flat. The thickness of Ueno is also the same.

次に、公知の手段に従って、ウェハ2の表面が研磨され
る。
Next, the surface of the wafer 2 is polished according to known means.

(イ)  効   果 (1)  ウェハは平面研削定盤に吸着された状態で、
平行に加工(平面研削、ポリッシュ)され、吸着された
ままプレートに貼付けられる。
(b) Effects (1) The wafer is attracted to the surface grinding plate,
It is processed in parallel (surface grinding and polishing) and attached to the plate while being adsorbed.

このため、ウェハの厚みのバラつきが10μm以上あっ
ても、厚みの揃った鏡面ウェハに問題なく加工できる。
Therefore, even if the wafer thickness varies by 10 μm or more, mirror-finished wafers with uniform thickness can be processed without any problem.

(2)予め裏面を平坦に加工するため、ワックス厚のバ
ラつきはプレートの平坦度による。プレートは充分平坦
であるから、ワックス厚のバラつきを1〜2μmとする
ことができる。
(2) Since the back surface is processed to be flat in advance, variations in wax thickness depend on the flatness of the plate. Since the plate is sufficiently flat, the variation in wax thickness can be reduced to 1 to 2 μm.

このため薄いウェハ、例えば厚みが500μm以下のウ
ェハてあっても、ウェハ面の凹凸ヤテーパが3μm程度
以下に収まる。
Therefore, even when a thin wafer is used, for example, a wafer having a thickness of 500 μm or less, the unevenness and taper of the wafer surface are kept to about 3 μm or less.

(3)裏面の加工、およびプレートへの貼付けを、真空
チャックの状態で行なう。これらの工程は、同一の場所
で実行されるから、搬送の手数がない。搬送しなくてよ
いので、処理時間が短縮され、またウェハが汚染され、
破損される惧れも少なくなる。
(3) Processing of the back surface and pasting to the plate are performed in a vacuum chuck state. These steps are performed at the same location, so there is no need for transportation. Since there is no need to transport the wafer, processing time is shortened and the wafer is not contaminated.
There is also less risk of damage.

(4)  同一の定盤に真空チャックして行なう工程は
容易に自動化する事ができる。自動化することにより、
厚みの精度、平坦度を上げることが容易になる。
(4) The process of vacuum chucking on the same surface plate can be easily automated. By automating
It becomes easy to improve thickness accuracy and flatness.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はウェハ表面が平面研削定盤に真空チャックされ
た状態を示す縦断面図。 第2図はウェハ裏面が平面研削されている状態を示す断
面図。 第3図はウェハ裏面がポリッシュされている状態を示す
縦断面図。 第4図はウェハ裏面にワックスを塗布した状態を示す縦
断面図。 第5図はワックスを塗布したウェハ裏面に研磨プレート
を押付けた状態を示す縦断面図。 第6図は真空チャックを解除し、平面研削定盤から離脱
した状態のウェハ、研磨プレートの縦断面図。 1 ・・・・平面研削定盤 2  −e・・  ウ    エ   ハ3・・・・真
空吸着穴 4・・・・研削砥石 5 ・・・・ ポリッシュ用パフ定盤 6  ・・・・  ワ  ッ  り  スフ ・・・・
研磨プレート 発  明  者         西  浦  隆  
幸特許出願人    住友電気工業株式会社・ト
FIG. 1 is a longitudinal cross-sectional view showing the state in which the wafer surface is vacuum chucked on a surface grinding plate. FIG. 2 is a sectional view showing a state in which the back surface of the wafer is surface ground. FIG. 3 is a longitudinal cross-sectional view showing a state in which the back surface of the wafer is polished. FIG. 4 is a longitudinal sectional view showing a state in which wax is applied to the back surface of the wafer. FIG. 5 is a longitudinal sectional view showing a state in which a polishing plate is pressed against the back surface of a wafer coated with wax. FIG. 6 is a vertical cross-sectional view of the wafer and polishing plate in a state where the vacuum chuck has been released and the wafer has been removed from the surface grinding surface plate. 1... Surface grinding surface plate 2 -e... Wafer 3... Vacuum suction hole 4... Grinding wheel 5... Puff surface plate for polishing 6... Wafer Sufu...
Polishing plate inventor Takashi Nishiura
Happy Patent Applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハの表面を真空チャックにより研磨定盤に固
定し、ウェハ裏面を研削し、さらにポリッシュした後、
ウェハ裏面にワックスを塗布し、研磨プレートをワック
スの塗布されたウェハ裏面に押し当て、真空チャックを
解除して研削定盤からウェハ及び研磨プレートを離脱す
ることを特徴とする半導体ウェハの研磨方法。
After fixing the front side of the semiconductor wafer to a polishing surface plate using a vacuum chuck, and grinding and polishing the back side of the wafer,
A method for polishing a semiconductor wafer, which comprises applying wax to the back surface of the wafer, pressing a polishing plate to the wax-coated back surface of the wafer, releasing the vacuum chuck, and removing the wafer and polishing plate from the grinding surface plate.
JP61020970A 1986-01-31 1986-01-31 Polishing of semiconductor wafer Pending JPS62181869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61020970A JPS62181869A (en) 1986-01-31 1986-01-31 Polishing of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61020970A JPS62181869A (en) 1986-01-31 1986-01-31 Polishing of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS62181869A true JPS62181869A (en) 1987-08-10

Family

ID=12042026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61020970A Pending JPS62181869A (en) 1986-01-31 1986-01-31 Polishing of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS62181869A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0460437A2 (en) * 1990-05-18 1991-12-11 Fujitsu Limited Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device composed of the substrate
US5213993A (en) * 1989-09-13 1993-05-25 Kabushiki Kaisha Tobisha Method of manufacturing semiconductor substrate dielectric isolating structure
EP0588055A2 (en) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Method for manufacturing wafer
JPH08167584A (en) * 1994-12-09 1996-06-25 Shin Etsu Handotai Co Ltd Manufacture of epitaxial wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213993A (en) * 1989-09-13 1993-05-25 Kabushiki Kaisha Tobisha Method of manufacturing semiconductor substrate dielectric isolating structure
EP0460437A2 (en) * 1990-05-18 1991-12-11 Fujitsu Limited Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device composed of the substrate
EP0588055A2 (en) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Method for manufacturing wafer
EP0588055A3 (en) * 1992-09-18 1994-08-10 Mitsubishi Materials Corp Method for manufacturing wafer
US5429711A (en) * 1992-09-18 1995-07-04 Mitsubishi Materials Corporation Method for manufacturing wafer
KR100299008B1 (en) * 1992-09-18 2001-11-30 후지무라 마사지카, 아키모토 유미 Wafer Manufacturing Method
JPH08167584A (en) * 1994-12-09 1996-06-25 Shin Etsu Handotai Co Ltd Manufacture of epitaxial wafer

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