JPH0319336A - Polishing of semiconductor wafer - Google Patents

Polishing of semiconductor wafer

Info

Publication number
JPH0319336A
JPH0319336A JP1153748A JP15374889A JPH0319336A JP H0319336 A JPH0319336 A JP H0319336A JP 1153748 A JP1153748 A JP 1153748A JP 15374889 A JP15374889 A JP 15374889A JP H0319336 A JPH0319336 A JP H0319336A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor wafer
wafer
thickness
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1153748A
Other languages
Japanese (ja)
Inventor
Yasuaki Nakazato
中里 泰章
Hiroo Ogawara
小河原 弘男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Nagano Electronics Industrial Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Nagano Electronics Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd, Nagano Electronics Industrial Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP1153748A priority Critical patent/JPH0319336A/en
Priority to DE69013065T priority patent/DE69013065T2/en
Priority to EP90306519A priority patent/EP0403287B1/en
Publication of JPH0319336A publication Critical patent/JPH0319336A/en
Priority to US07/781,644 priority patent/US5191738A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/005Control means for lapping machines or devices
    • B24B37/013Devices or means for detecting lapping completion

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

PURPOSE:To perform rapidly a polishing of a semiconductor wafer, to facilitate the control of the amount of polishing and to inhibit small the irregularity of the thickness within the surface of the wafer by a method wherein the wafer which inclines to polish is bonded on the central part of the lower surface of a plate and thickness regulating members, whose surface layers consisting of a material of a polishing speed slower than that of the wafer, are arranged on the lower surface of the plate. CONSTITUTION:A semiconductor wafer 12 which inclines to polish is bonded on the central part of the lower surface of a glass plate 11 and at the same time, dummy wafers 15, whose surface layers consist of a material of a polishing speed slower than that of the wafer 12, are arranged on the periphery of the wafer 12 in the lower surface of the plate 11. For example, speaking in respect to the dummy wafers 15, whose parent materials consist of silicon and which have a thermal oxide film formed on their surface layers, the polishing speed of the wafers 15 is 1/200 or less of that of silicon according to the condition of polishing.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体ウェーハの研磨方法に関するもので、
特に、研磨面の平坦性が強く要請され.る半導体ウェー
ハの研磨に適用して有効む技術に関するものである. [従来の技術] 半導体シリコンウェーハの加工の最終工程にポリッシン
グの工程がある.このポリッシングの工程は鏡面形成の
ための工程であり、この工程では、一般に,研磨剤の要
素と、化学反応による要素とを複合して行うメカノケミ
カル法が用いられている。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for polishing semiconductor wafers,
In particular, flatness of the polished surface is strongly required. This paper relates to a technique that is effective when applied to the polishing of semiconductor wafers. [Conventional technology] The final step in processing semiconductor silicon wafers is a polishing step. This polishing process is a process for forming a mirror surface, and generally a mechanochemical method is used in which an abrasive element and a chemical reaction element are combined.

第4図には片面ポリッシングに用いられるポリッシング
装置の要部が示されている。
FIG. 4 shows the main parts of a polishing device used for single-sided polishing.

同図において符号1はガラスプレートを示しており、こ
のガラスプレート1の下面には,ラッピング、グライン
ディング,ベベリング及びエッチング等の終了した半導
体ウェーハ2が、第5図に示すように、ワックスを介し
て着脱可能に複数枚接着されている。一方,ガラスプレ
ート1の下方に位置するターンテーブル3の上面には研
磨布3aが設けられている。そして、この装置にあって
は、ガラスプレート1によって半導体ウェーハ2を研磨
布3aに圧接させるとともに,ターンテーブル3の回転
によって半導体ウェーハ2を支持するガラスプレート1
をも回転させて研磨布3aに半導体ウェーハ2を摺接さ
せることによって,ガラスプレート1の下面に接着され
ている半導体ウェーハ1の主面を研磨するようになって
いる。その際,研磨布3aに対しては,スラリーとして
、弱アルカリ性のコロイダルシリ力等の研磨剤を含む水
溶液が供給される。
In the figure, reference numeral 1 indicates a glass plate, and a semiconductor wafer 2 that has been subjected to lapping, grinding, beveling, etching, etc. is placed on the bottom surface of the glass plate 1 with wax interposed therebetween, as shown in FIG. Multiple pieces are glued together so that they can be attached and removed. On the other hand, a polishing cloth 3a is provided on the upper surface of the turntable 3 located below the glass plate 1. In this apparatus, the semiconductor wafer 2 is brought into pressure contact with the polishing cloth 3a by the glass plate 1, and the glass plate 1 supports the semiconductor wafer 2 by the rotation of the turntable 3.
By also rotating the polishing cloth 3a and bringing the semiconductor wafer 2 into sliding contact with the polishing cloth 3a, the main surface of the semiconductor wafer 1 bonded to the lower surface of the glass plate 1 is polished. At this time, an aqueous solution containing a weakly alkaline abrasive such as colloidal silica is supplied as a slurry to the polishing cloth 3a.

[発明が解決しようとする課M] ところで、近年におけるように、半導体集積回路の微細
化及び小型化に起因して半導体ウェーハの研磨面の平坦
性が強く要請されてくると、上記のような研磨方法では
,下記のような問題が生じてきた. つまり、上記ポリッシング装置を利用しての研磨にあっ
ては、研磨布自身の経時変化、半導体ウ工一ハ2の研磨
布3aへの圧接に起因するガラスプレート1の弾性変形
,ターンテーブル1の半径方向各位置での周速の違いが
生じており、近年におけるデバイス開発においては、そ
れらによる研磨面内の厚さバラツキは無視できないもの
となっている。活性化領域の厚さが極端に薄いSO工構
造のデバイスにおいては尚更である。
[Problem M to be solved by the invention] In recent years, as semiconductor integrated circuits have become finer and smaller, there has been a strong demand for flatness of the polished surface of semiconductor wafers. The following problems have arisen with polishing methods. In other words, in polishing using the polishing apparatus described above, changes in the polishing cloth itself over time, elastic deformation of the glass plate 1 due to pressure contact of the semiconductor substrate 2 to the polishing cloth 3a, and There are differences in the circumferential speed at each position in the radial direction, and in recent device development, the thickness variations within the polished surface due to these differences cannot be ignored. This is especially true in devices with an SO-structured structure in which the thickness of the active region is extremely thin.

また,研磨速度は、半導体ウェーハ2の研磨布3aへの
圧接力が大きいほど速くなるが、研磨速度が速い場合に
は、その研磨量のコントロールが困難である。一方、研
磨速度が遅い場合には,研磨量のコントロールは容易で
はあるが、ポリノシングに長時間要してしまうという問
題があった。
Further, the polishing rate increases as the pressure force of the semiconductor wafer 2 against the polishing cloth 3a increases, but when the polishing rate is high, it is difficult to control the amount of polishing. On the other hand, when the polishing speed is slow, although it is easy to control the amount of polishing, there is a problem in that polynosing takes a long time.

本発明は、かかる点に鑑みなされたもので、半導体ウェ
ーハの研磨が迅速に行なえかつ研磨量のコントロールが
容易で,しかも面内の摩さバラツキを小さく押さえるこ
とができる半導体ウェーハの研磨方法を提供することを
目的としている。
The present invention has been made in view of the above points, and provides a method for polishing semiconductor wafers that can quickly polish semiconductor wafers, easily control the amount of polishing, and suppress in-plane polishing variation to a small level. It is intended to.

この発明のそのほかの目的と新規な特徴については、水
明m書の記述および添lrfm面から明らかになるであ
ろう。
Other objects and novel features of this invention will become clear from the description in the Suimei Book and the attached IRFM page.

[’AMを解決するための手段] 上記目的を達或するため,本発明は、プレートに接着さ
れた半導体ウェーハを,回転するターンテーブル側へ押
し付けることによって,所定の厚さまで研磨するにあた
り、上記プレートに研磨しようとする半導体ウェーハを
接着するとともに、上記プレート面に、少なくともその
表層が上記半導体ウェーハよりも研磨速度の遅い材料か
らなる厚さ規制部材を配し、この厚さ規制部材によって
上記半導体ウェーハの厚さ制御を行なうようにしたもの
である. [作用〕 本発明によれば、プレートに研磨しようとする半導体ウ
ェーハを接着するとともに、上記プレート面に、上記半
導体ウェーハよりも研磨速度の遅い材料からなる厚さ規
制部材を配し,この厚さ規制部材をストツパとして上記
半導体ウェーハを研磨するようにしたので,半導体ウェ
ーハのターンテーブル側への圧接力を大きくして研磨速
度を速めた場合であっても、研磨の終了間際には上記圧
接力の一部は上記厚さ規制部材によってサポートされる
ことになる結果,その分,研磨速度が遅くなり,上記半
導体ウェーハの研磨量のコントロール、ひいては半導体
ウェーハの厚さWilI御が容易となる。また、その研
磨而も美麗となる6また、半導体ウェーハの周りに配さ
れる厚さ規制部材がストツパとして機能し、当該厚さ規
制部材のターンテーブル側の面と酩面一となるように研
磨されるので、面内の厚さバラッキも小さくむる。
[Means for Solving 'AM] In order to achieve the above object, the present invention provides a method for polishing a semiconductor wafer bonded to a plate to a predetermined thickness by pressing it against a rotating turntable. A semiconductor wafer to be polished is bonded to the plate, and a thickness regulating member, at least the surface layer of which is made of a material whose polishing speed is slower than that of the semiconductor wafer, is disposed on the plate surface, and the thickness regulating member is used to polish the semiconductor wafer. This is designed to control the thickness of the wafer. [Function] According to the present invention, a semiconductor wafer to be polished is bonded to a plate, and a thickness regulating member made of a material whose polishing rate is slower than that of the semiconductor wafer is disposed on the plate surface, and the thickness of the semiconductor wafer is Since the semiconductor wafer is polished using the regulating member as a stopper, even if the pressing force of the semiconductor wafer to the turntable side is increased to increase the polishing speed, the pressing force will be reduced just before the end of polishing. As a result, a portion of the semiconductor wafer is supported by the thickness regulating member, and as a result, the polishing speed is reduced accordingly, making it easier to control the polishing amount of the semiconductor wafer and, by extension, the thickness of the semiconductor wafer. In addition, the polishing process becomes beautiful.6 Also, the thickness regulating member placed around the semiconductor wafer functions as a stopper, and polishing is done so that it is flush with the surface of the thickness regulating member on the turntable side. Therefore, the in-plane thickness variation is also reduced.

故に、信頼性の高い半遣体ウェーハを得ることができる
, [実施例] 以下、本発明に係る半導体ウェーハの研磨方法の実施例
を説明する。
Therefore, a half-finished wafer with high reliability can be obtained. [Example] Hereinafter, an example of the semiconductor wafer polishing method according to the present invention will be described.

第工図には片面ポリッシングに用いられるポリッシング
装置の要部が示されている。
The first drawing shows the main parts of a polishing device used for single-sided polishing.

同図において符号11はガラスプレートを示しており,
このガラスプレート11の下面中央部には、第2図に示
すように,ラッピング、グラインディング及びベベリン
グ、エッチング等の終了した半導体ウェーハ12がワッ
クスを介して1枚接着されている。また、ガラスプレー
ト11の下面には,上記半導体ウェーハ12を取り囲む
ようにして、厚さ規制部材たるダミーウェーハ15が計
8枚配されている。半導体ウェーハl2及びダミーウェ
ーハ15のガラスプレートl1上へのワックス接着に際
しては,その厚さのバラツキは要求によっては0.1μ
m以下の制度で制御するのが好ましい。かかる制御は、
溶融ワックスをスプレーでウェーハ接着面に均一に噴霧
したのち接着するか、あるいはウェーハ12または15
をプレート11上に接着したのち加熱し、周縁よりワッ
クスを侵入させ、次いで加圧することによって可能とな
る。
In the figure, numeral 11 indicates a glass plate,
As shown in FIG. 2, a single semiconductor wafer 12 that has been subjected to lapping, grinding, beveling, etching, etc. is adhered to the center of the lower surface of the glass plate 11 via wax. Further, a total of eight dummy wafers 15 serving as thickness regulating members are arranged on the lower surface of the glass plate 11 so as to surround the semiconductor wafer 12. When wax bonding semiconductor wafer l2 and dummy wafer 15 onto glass plate l1, the variation in thickness may be 0.1 μm depending on requirements.
It is preferable to control with a precision of m or less. Such control is
Either spray molten wax uniformly onto the wafer bonding surface and then bond the wafer 12 or 15.
This can be achieved by adhering the material onto the plate 11, heating it, allowing the wax to penetrate from the periphery, and then applying pressure.

このダミーウェーハ15はその全体が上記半導体ウェー
ハ12よりも研磨されにくい材料で構成されるか,若し
くは,少なくともその表層が上記半導体ウェーハ12よ
りも研磨されにくい材料で構成される。例えば,その母
材がシリコンで構或され、その表層にシリコン酸化膜が
形成された構造となっている。このときのシリコン酸化
膜は熱酸化膜であっても良いし、CVD酸化膜であって
も良いが、好ましくは、メカノケミカル法による研磨速
度のより遅い熱酸化膜とするのが良い。なお,このダミ
ーウェーハ15は、上記半導体ウェーハ↓2と同様にワ
ックスで着脱可能にガラスプレート11に接着されるか
、若しくはエボキシ樹脂等によって強固に(半永久的に
)ガラスプレート1lに接着される。ダミーウェーハ1
5が′J!.導体ウェーハ12に比較して極めて研磨さ
れにくい場合には後者とするのが便利である。なお,ダ
ミーウェーハ15の母材をシリコンで構成すれば、極め
て高度の厚さ制御が可能である。
The entire dummy wafer 15 is made of a material that is more difficult to polish than the semiconductor wafer 12, or at least its surface layer is made of a material that is more difficult to polish than the semiconductor wafer 12. For example, it has a structure in which the base material is made of silicon and a silicon oxide film is formed on its surface layer. The silicon oxide film at this time may be a thermal oxide film or a CVD oxide film, but preferably a thermal oxide film whose polishing rate is slower by a mechanochemical method. The dummy wafer 15 is removably bonded to the glass plate 11 with wax, similar to the semiconductor wafer ↓2, or is firmly (semi-permanently) bonded to the glass plate 11 with epoxy resin or the like. Dummy wafer 1
5 is 'J! .. The latter is convenient when it is extremely difficult to polish compared to the conductor wafer 12. Note that if the base material of the dummy wafer 15 is made of silicon, extremely high degree of thickness control is possible.

一方、ガラスプレート11の下方に配されるターンテー
ブル13の上面には研磨布13aが貼付されている。
On the other hand, a polishing cloth 13a is attached to the upper surface of the turntable 13 arranged below the glass plate 11.

そして、この装置を用いてのポリッシングにあっては、
ガラスプレートl1によって半導体ウェ一ハ12を研磨
布13aに圧接させるとともに、ターンテーブル13の
回転によって半導体ウェーハ12を支持するガラスプレ
ートエ1をも回転させて研磨布13aに半導体ウェーハ
l2を摺接させることによって、ガラスプレート11の
下面に接着されている半導体ウェーハ11の主面を研磨
するようにしている。例えば、その際の研磨剤としては
,コロイダルシリ力を研磨材としてこれを水溶液中に分
散させ、化学反応としては、Na○I−L NH,OH
などで弱アルカリ性にPH調節されたものが用いられる
In polishing using this device,
The semiconductor wafer 12 is brought into pressure contact with the polishing cloth 13a by the glass plate 11, and the glass plate 1 supporting the semiconductor wafer 12 is also rotated by the rotation of the turntable 13, so that the semiconductor wafer 12 is brought into sliding contact with the polishing cloth 13a. By this, the main surface of the semiconductor wafer 11 bonded to the lower surface of the glass plate 11 is polished. For example, as an abrasive at that time, colloidal silica is used as an abrasive and it is dispersed in an aqueous solution, and as a chemical reaction, Na○I-L NH,OH
Those whose pH has been adjusted to be slightly alkaline are used.

上記のような方法によって半導体ウェーハl1を研磨す
るようにすれば下記のような効果を得ることができる。
If the semiconductor wafer l1 is polished by the method described above, the following effects can be obtained.

即ち、上記実施例の研磨方広によれば、ガラスプレート
11の下面中央部に研磨しようとする半導体ウェーハ1
2を接着するとともに、上記ガラスプレート11におけ
る上記半導体ウェーハ12の周りに、上記半導体ウェー
ハ12よりも研磨速度の遅い材料からなるダミーウェー
ハ↓5を配している。例えば、母材がシリコンからなり
その表層に熱酸化膜を形或したダミーウェーハt5につ
いて言えば、研磨条件によっては研磨速度はシリコンに
対して↓/200以下である。
That is, according to the polishing method of the above embodiment, the semiconductor wafer 1 to be polished is
At the same time, a dummy wafer ↓ 5 made of a material whose polishing rate is slower than that of the semiconductor wafer 12 is placed around the semiconductor wafer 12 on the glass plate 11 . For example, regarding the dummy wafer t5 whose base material is silicon and has a thermal oxide film formed on its surface layer, the polishing rate is ↓/200 or less compared to silicon depending on the polishing conditions.

このようなダミーウェーハ15をストッパとして上記半
導体ウェーハ王2を研磨するようにしたので、半導体ウ
ェーハ12のターンテーブル丁↓側への圧接力を大きく
して研磨速度を速めた場合であっても、研磨の終了間際
には上記圧接力の一部はダミーウェーハ15によってサ
ポートされることになる結果、その分、研磨速度が遅く
なり,上記半導体ウェーハ12の研磨量のコントロール
,ひいては半導体ウェーハL2の厚さ制御が容易となる
。また、その研磨面も美麗となる。
Since the semiconductor wafer king 2 is polished using such a dummy wafer 15 as a stopper, even when the polishing speed is increased by increasing the pressing force of the semiconductor wafer 12 toward the turntable ↓ side, Near the end of polishing, a part of the pressure contact force is supported by the dummy wafer 15, and as a result, the polishing speed is slowed down, which makes it easier to control the amount of polishing of the semiconductor wafer 12 and, ultimately, the thickness of the semiconductor wafer L2. control becomes easy. Moreover, the polished surface becomes beautiful.

また、半虜体ウェーハ12の周りに配されるダミーウェ
ーハ15がストツパとして機能し,当該ダミーウェーハ
15のターンテーブルl1側の面と酩面一となるように
研磨されるので、面内の厚さバラツキも小さくなる。
In addition, the dummy wafer 15 placed around the half-captive wafer 12 functions as a stopper, and is polished so that it is flush with the surface of the dummy wafer 15 on the turntable l1 side. The variation is also reduced.

故に,信頼性の高い半導体ウェーハ12を得ることがで
きる。
Therefore, a highly reliable semiconductor wafer 12 can be obtained.

このうち面内の厚さバラツキが小さくなるという効果を
追認するため、下記のような実験を行った。
In order to confirm the effect of reducing in-plane thickness variation, the following experiment was conducted.

この実験では、17枚の150mmφの半導体ウェーハ
を用い,一方,厚さ規制部材としては、母材がシリコン
からなりその表層に熱酸化によってシリコン酸化膜が形
成されたダミーウェーハを用いた. この際の厚さ測定ポジションは,第3図に示すような9
点である. この実験によれば,高精度に厚さコントロールができた
。ちなみに,この実験では、約20μm平均研磨したと
きに厚さのずれが±0.3μm内に収まったウェーハの
割合は実に75.8%であった.また、0.1μm以内
に収まったウェーハの割合は50%であった。
In this experiment, 17 semiconductor wafers with a diameter of 150 mm were used, and a dummy wafer whose base material was silicon and had a silicon oxide film formed on its surface by thermal oxidation was used as the thickness regulating member. The thickness measurement position at this time is 9 as shown in Figure 3.
It is a point. According to this experiment, the thickness could be controlled with high precision. Incidentally, in this experiment, the percentage of wafers whose thickness deviation was within ±0.3 μm when polished by an average of about 20 μm was 75.8%. Furthermore, the percentage of wafers whose diameter was within 0.1 μm was 50%.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが,本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない. 例えば,上記実施例では,厚さ規制部材として,シリコ
ンを基材とし表層にシリコン酸化膜を形成したダミーウ
ェーハ15を用いたが、シリコンを基材とし表層にナイ
トライド膜を形成したダミーウェーハを用いても良い。
Above, the invention made by the present inventor has been specifically explained based on examples, but it should be noted that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Of course. For example, in the above embodiment, the dummy wafer 15 made of silicon and with a silicon oxide film formed on the surface layer was used as the thickness regulating member. May be used.

また、厚さ規制部材として石英、プラスチック若しくは
サファイア、又はコンタミネーションを考慮しないので
あればメタルにてダミーウェーハを構成しても良い。さ
らには、その形状も、ウェーハと同様な形状としなくて
も良く、半導体ウェーハ12を取り囲むようにリング状
に形成しても良い。要は、圧接力の一部をサポートでき
、研磨の際のストツパとして機能するものであれば良い
ものである。
Furthermore, the dummy wafer may be made of quartz, plastic, or sapphire as the thickness regulating member, or may be made of metal if contamination is not considered. Further, the shape thereof does not have to be the same as that of the wafer, and may be formed in a ring shape so as to surround the semiconductor wafer 12. In short, any material that can support part of the pressure contact force and function as a stopper during polishing is sufficient.

[発明の効果] 本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
. 本発明は,プレートに接着された半導体ウェーハを、回
転するターンテーブル側へ押し付けることによって、所
定の厚さまで研磨するにあたり、上記プレートに研磨し
ようとする半導体ウェーハを接着するとともに、上記プ
レート面に、少なくともその表層が上記半導体ウェーハ
よりも研磨速度の遅い材料からなる厚さ規制部材を配し
、この厚さ規制部材によって上記半導体ウェーハの厚さ
制御を行なうようにしたので、研磨速度を速めた場合で
あっても、上記半導体ウェーハの研磨量のコントロール
が容易となる。また、軸振れ等が生じた場合、厚さ規制
部材によって押圧力がサポートされ、その厚さ規制部材
の厚み以上には、上記半導体ウェーハが研磨されること
はないので,面内厚さのパラツキが少なくなる。故に、
信頼性の高い半導体ウエー八を得ることができる。
[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. In the present invention, when polishing a semiconductor wafer bonded to a plate to a predetermined thickness by pressing it against a rotating turntable, the semiconductor wafer to be polished is bonded to the plate, and the semiconductor wafer to be polished is bonded to the plate surface. A thickness regulating member, at least the surface layer of which is made of a material whose polishing rate is slower than that of the semiconductor wafer, is arranged, and the thickness of the semiconductor wafer is controlled by this thickness regulating member, so that when the polishing rate is increased. Even in this case, the amount of polishing of the semiconductor wafer can be easily controlled. In addition, when shaft runout occurs, the pressing force is supported by the thickness regulating member, and the semiconductor wafer is not polished beyond the thickness of the thickness regulating member, so variations in the in-plane thickness can be prevented. becomes less. Therefore,
A highly reliable semiconductor wafer can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本実施例の研磨方法の実施に使用されるポリソ
シング装置の一部を示す縦断面図、第2図は半導体ウェ
ーハ及びダミーウェーハ(厚さ規制部材)のプレートへ
の接着状態を示すプレートの平面図, 第3図は実験における半導体ウェーハの測定ポジション
を示す半導体ウェーハの平面図,第4図は従来の研磨方
法の実施に使用されるポリッシング装置の一部を示す縦
断面図、第5図は半導体ウェーハのプレートへの接着状
態を示すプレートの平面図である。 11・・・・ガラスプレート、12・・・・半導体ウェ
ーハ、13・・・・ターンテーブル,15・・・・ダミ
ーウェーハ(厚さ規制部材)。 第 1 図 第2図 5 第3 図
FIG. 1 is a vertical cross-sectional view showing a part of the polishing apparatus used to carry out the polishing method of this example, and FIG. 2 shows the state of adhesion of a semiconductor wafer and a dummy wafer (thickness regulating member) to a plate. FIG. 3 is a plan view of the semiconductor wafer showing the measurement position of the semiconductor wafer in the experiment; FIG. FIG. 5 is a plan view of the plate showing the state of adhesion of the semiconductor wafer to the plate. 11...Glass plate, 12...Semiconductor wafer, 13...Turntable, 15...Dummy wafer (thickness regulating member). Figure 1 Figure 2 Figure 5 Figure 3

Claims (1)

【特許請求の範囲】 1、プレートに接着された半導体ウェーハを、回転する
ターンテーブル側へ押し付けることによって、所定の厚
さまで研磨するにあたり、上記プレートに研磨しようと
する半導体ウェーハを接着するとともに、上記プレート
面に、少なくともその表層が上記半導体ウェーハよりも
研磨速度の遅い材料からなる厚さ規制部材を配し、この
厚さ規制部材によって上記半導体ウェーハの厚さ制御を
行なうようにしたことを特徴とする半導体ウェーハの研
磨方法。 2、上記の厚さ規制部材はその母材がシリコンからなり
、その厚さ規制部材のターンテーブル側の表層にはシリ
コン酸化膜が形成されていることを特徴とする請求項1
記載の半導体ウェーハの研磨方法。
[Claims] 1. When polishing a semiconductor wafer adhered to a plate to a predetermined thickness by pressing it against a rotating turntable, the semiconductor wafer to be polished is adhered to the plate, and the A thickness regulating member, at least the surface layer of which is made of a material whose polishing rate is slower than that of the semiconductor wafer, is disposed on the plate surface, and the thickness of the semiconductor wafer is controlled by the thickness regulating member. A method for polishing semiconductor wafers. 2. Claim 1, wherein the base material of the thickness regulating member is made of silicon, and a silicon oxide film is formed on the surface layer of the thickness regulating member on the turntable side.
The method for polishing a semiconductor wafer as described.
JP1153748A 1989-06-16 1989-06-16 Polishing of semiconductor wafer Pending JPH0319336A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1153748A JPH0319336A (en) 1989-06-16 1989-06-16 Polishing of semiconductor wafer
DE69013065T DE69013065T2 (en) 1989-06-16 1990-06-14 Process for polishing semiconductor wafers.
EP90306519A EP0403287B1 (en) 1989-06-16 1990-06-14 Method of polishing semiconductor wafer
US07/781,644 US5191738A (en) 1989-06-16 1991-10-25 Method of polishing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1153748A JPH0319336A (en) 1989-06-16 1989-06-16 Polishing of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH0319336A true JPH0319336A (en) 1991-01-28

Family

ID=15569254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1153748A Pending JPH0319336A (en) 1989-06-16 1989-06-16 Polishing of semiconductor wafer

Country Status (3)

Country Link
EP (1) EP0403287B1 (en)
JP (1) JPH0319336A (en)
DE (1) DE69013065T2 (en)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
US6102780A (en) * 1998-04-09 2000-08-15 Oki Electric Industry Co., Ltd. Substrate polishing apparatus and method for polishing semiconductor substrate
US6346997B1 (en) 1993-12-24 2002-02-12 Canon Kabushiki Kaisha Illumination device, image reading apparatus having the device and information processing system having the apparatus

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Publication number Priority date Publication date Assignee Title
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
GB2275129B (en) * 1992-05-26 1997-01-08 Toshiba Kk Method for planarizing a layer on a semiconductor wafer
US5445996A (en) * 1992-05-26 1995-08-29 Kabushiki Kaisha Toshiba Method for planarizing a semiconductor device having a amorphous layer
CN105199610B (en) * 2015-10-16 2017-12-19 郑州磨料磨具磨削研究所有限公司 A kind of sapphire polishing composition and preparation method thereof

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DE1110544B (en) * 1957-11-29 1961-07-06 Siemens Ag Single disc lapping machine for semiconductor wafers
US3559346A (en) * 1969-02-04 1971-02-02 Bell Telephone Labor Inc Wafer polishing apparatus and method
US4165584A (en) * 1977-01-27 1979-08-28 International Telephone And Telegraph Corporation Apparatus for lapping or polishing materials
FR2521895A1 (en) * 1982-02-23 1983-08-26 Ansermoz Raymond Multiple work holder for lapidary grinding - uses suction to hold work in place with adjustable stops governing finished work thickness
JPS6451268A (en) * 1987-08-19 1989-02-27 Sanyo Electric Co Mechanical polishing method
JP3351687B2 (en) * 1996-08-05 2002-12-03 株式会社東芝 Filter operation device and filter operation method used for noise cancellation

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JPS6471663A (en) * 1987-09-08 1989-03-16 Hitachi Cable Lapping method for gaas wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346997B1 (en) 1993-12-24 2002-02-12 Canon Kabushiki Kaisha Illumination device, image reading apparatus having the device and information processing system having the apparatus
US6102780A (en) * 1998-04-09 2000-08-15 Oki Electric Industry Co., Ltd. Substrate polishing apparatus and method for polishing semiconductor substrate

Also Published As

Publication number Publication date
EP0403287A3 (en) 1991-10-23
DE69013065T2 (en) 1995-01-26
DE69013065D1 (en) 1994-11-10
EP0403287A2 (en) 1990-12-19
EP0403287B1 (en) 1994-10-05

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