JPS62181418A - Manufacture of bonded type semiconductor substrate - Google Patents
Manufacture of bonded type semiconductor substrateInfo
- Publication number
- JPS62181418A JPS62181418A JP2207086A JP2207086A JPS62181418A JP S62181418 A JPS62181418 A JP S62181418A JP 2207086 A JP2207086 A JP 2207086A JP 2207086 A JP2207086 A JP 2207086A JP S62181418 A JPS62181418 A JP S62181418A
- Authority
- JP
- Japan
- Prior art keywords
- bonded
- semiconductor substrates
- semiconductor substrate
- mirror
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000227 grinding Methods 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 17
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 238000005520 cutting process Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 8
- 238000007665 sagging Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、２枚の半導体基板を直接接着することによ
って製造される接着型半導体基板の製造方法に関し、特
に被接着面の鏡面が改良された製造方法に関するもので
ある。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a bonded semiconductor substrate manufactured by directly bonding two semiconductor substrates, and in particular, a method for manufacturing a bonded semiconductor substrate, in which the mirror surface of the surface to be bonded is improved. This relates to a manufacturing method.
［発明の技術的費目］
２枚の半導体基板を接着してｊｑられる接着型半導体基
板は例えば電力用のスイッチングデバイスの出発材料と
して使用される。 例示したスイッチングデバイスのプ
ロヒスでは、半導体基板にまずＮ−／Ｎ＋構造を形成す
る必要があるが、Ｎ“基板上にＮ一層をエピタキシャル
成長によってかなりの日数をかけて形成していたものを
、Ｎ＋半導体ウェハとＮ−半導体ウェハどを接着した接
着型半導体基板を出発材料とすれば、素子形成時間は非
常に短時間になるという利点が生ずる。[Technical Expenses of the Invention] A bonded semiconductor substrate, which is formed by bonding two semiconductor substrates together, is used, for example, as a starting material for a power switching device. In the switching device shown in the example, it is necessary to first form an N-/N+ structure on a semiconductor substrate. If a bonded semiconductor substrate in which a wafer and an N-semiconductor wafer are bonded together is used as a starting material, the advantage is that the device formation time is extremely short.
接着型半導体基板の構成材料となる２枚の半導体基板は
、素子形成面の平ＩＵ１度が６μｍ以下という比較的厳
しいＭＯ８用半導体ウェハの精度と同等の精度でメカノ
ケミカルポリッシングされた後、清浄な雰囲気中で相互
に接着し、次いでＮ一層について素子形成のための所定
の厚さになるまでグラインダ・ラップがされている。The two semiconductor substrates that are the constituent materials of the adhesive type semiconductor substrate are mechanochemically polished with a precision equivalent to that of relatively strict MO8 semiconductor wafers, with a flat IU of 6 μm or less on the element forming surface. They are bonded together in an atmosphere and then grinder lapped with a single layer of N until a predetermined thickness for device formation is achieved.
［前頭技術の問題点］
しかしながら、上記従来方法では、メカノケミカルポリ
ッシングによって周縁部を除いた素子形成面の平１０度
（粗度）を前記のレベル（６μｍ以下）にづることはで
きるが、周縁部２〜５ｍｍの範囲にブレを生じることが
避りられず、従って、周縁部に縁ダレのある２枚の半導
体基板を接着すると、縁ダレのある部分は接着されない
ので外周部には環状に未接着部分が生ずる。 このよう
な未接着部が存在すると前記グラインダ・ラップなど素
子形成工程中に欠けや割れが発生するばかりでイよく、
それが発端となってウェハ表面にスクラッチを起こして
歩留りを悪化させるという問題点があった。[Problems with the frontal technology] However, in the conventional method described above, although it is possible to bring the flatness of the element forming surface excluding the periphery to the above-mentioned level (6 μm or less) by mechanochemical polishing, the periphery Therefore, when two semiconductor substrates with sagging edges are bonded together, the area with sagging edges will not be bonded, so there will be an annular shape on the outer periphery. There will be some unbonded parts. If such an unbonded part exists, chipping or cracking will occur during the element forming process such as grinding and lapping, which is a problem.
This caused a problem in that it caused scratches on the wafer surface and deteriorated the yield.
そのため、従来は、４インチ（１００ｍｍ程度）直径の
半導体基板の接着加工終了後に未接着部（９６〜９０ｍ
ｍの直径まで）を削り落す必要があったが、ウェハの工
程標準を合わせるためにも直径が３インチ（７６，２＋
ｎｍ稈度）になるまで外周部を削り落としてから索子形
成工程に移行していた。Therefore, conventionally, after completing the bonding process of a 4-inch (approximately 100 mm) diameter semiconductor substrate, the unbonded area (96 to 90 m) was removed.
However, in order to meet wafer process standards, the diameter was reduced to 3 inches (76,2+ m).
After scraping off the outer periphery until it reached a culm size of nm (nm culm degree), the process of forming a cord was started.
従って、材料ロスが多大であるとともに最初のウェハを
基準どした歩留りは非常に低いものとなっており、接着
型半導体基板のコスト高の重要な要因となっている。Therefore, there is a large amount of material loss, and the yield based on the initial wafer is extremely low, which is an important factor in the high cost of bonded semiconductor substrates.
［発明の目的］
この発明の目的は、接着前の半導体ウェハと同一直径の
接着型半導体基板を製造することのできる、改良された
製造方法を提供することであり、また、従来よりもコス
トの安ｆｌＩな接着型半導体基板を製造する方法を１是
供することである。[Objective of the Invention] An object of the present invention is to provide an improved manufacturing method capable of manufacturing a bonded semiconductor substrate having the same diameter as a semiconductor wafer before bonding, and at a lower cost than before. An object of the present invention is to provide a method for manufacturing a cheap adhesive type semiconductor substrate.
［発明の概要］
この発明による方法では、接着前の２枚の半導体基板の
それぞれの被接着面を先ず平面研削した後、橿く軽度に
メカノケミカルポリッシング（以下ＭＣＰと記載）を行
って鏡面に仕上げることを特徴とする。 この方法では
互いに接着さるべき２枚の半導体基板の被接着面を機械
加工である研削加工で研削加工代の殆どを加工するので
、縁ダレは殆ど生ぜず、従って、従来方法のように外周
部の削り落としをしなくても被接着面の全面が互いに接
着された接着型半導体基板が得られる。[Summary of the Invention] In the method according to the present invention, the surfaces of two semiconductor substrates to be bonded before being bonded are first ground to a surface, and then lightly mechanochemically polished (hereinafter referred to as MCP) to a mirror surface. It is characterized by finishing. In this method, the surfaces of two semiconductor substrates to be bonded to each other are processed by grinding, which is a mechanical process, to cover most of the grinding allowance. It is possible to obtain an adhesive type semiconductor substrate in which the entire surfaces to be adhered are adhered to each other without removing the parts.
［発明の実施例］
第１図の（ａ ）は被接合面の加工がまだなされていな
い状態の２枚の半導体基板１及び２を示す。[Embodiment of the Invention] FIG. 1(a) shows two semiconductor substrates 1 and 2 whose surfaces to be bonded have not yet been processed.
この半導体基板１及び２の研削前における平行度は５μ
ｍ以内のものを選択した。The parallelism of these semiconductor substrates 1 and 2 before grinding is 5μ
Selected those within m.
次に、該半導体基板１及び２のそれぞれの接着すべき面
を＃１７００のレジンボンド砥石装着の平面研削盤で５
〜１０μｍ研削して（ｂ ）の状態にする。Next, the surfaces to be bonded of each of the semiconductor substrates 1 and 2 are polished using a surface grinder equipped with a #1700 resin bond grindstone.
Grind by ~10 μm to obtain the state shown in (b).
そのような研削は仕上げ研削に相当し、その結果、（ｂ
）の状態にＪ３ける研削面１ａ及び２ａの表面粗さは
ほぼ１．０μｍ、外周縁部における周縁ダレは砥石の切
込みストローク１ ｍ ｍ以内でダレ量は数７１ ｍで
あった。Such grinding corresponds to finish grinding and results in (b
) The surface roughness of the ground surfaces 1a and 2a in J3 was approximately 1.0 μm, and the peripheral edge sag at the outer peripheral edge was within 1 mm of the cutting stroke of the grindstone, and the amount of sag was several 71 m.
次いで、研削面１ａ、２ａに対してＭＣＰ加工を行い、
はぼ鏡面の面１ｂ、２ｂを（ｑる。 この場合の加工代
は撞く少ないものとする。 そのよ。Next, MCP processing is performed on the ground surfaces 1a and 2a,
The mirror-like surfaces 1b and 2b are (q). The machining allowance in this case will be quite small.
うにＭＣＰ加工をすると、而１ｂ及び２ｂの面内凹凸は
ほぼＯであり、表面粗さは５０Ｘ以内であり、周縁ダレ
は平面研削時の値と変らないものが得られた。When the sea urchin was subjected to MCP processing, the in-plane unevenness of 1b and 2b was approximately O, the surface roughness was within 50X, and the peripheral edge sagging was the same as that obtained when surface grinding was performed.
以上のように２枚の半導体基板１及び２のそれぞれの被
接着面を加工した後、而１ｂ及び２ｂを洗浄して清浄な
鏡面にし、該鏡面どうしを清浄な雰囲気内にあるウェハ
接着装置で（ｄ ）のように圧接させる。 そして、熱
処理を行うことによって半導体基板１と２との装着を強
化させる。After processing the bonded surfaces of the two semiconductor substrates 1 and 2 as described above, 1b and 2b are cleaned to make them clean mirror surfaces, and the mirror surfaces are bonded together using a wafer bonding device in a clean atmosphere. Press them together as shown in (d). Then, by performing heat treatment, the attachment between the semiconductor substrates 1 and 2 is strengthened.
このように直接接着させて得られた接着型半導体基板３
の一方の而（半導体基板１の而）をグラインダ・ラップ
・ＭＣＰ等で所定洛加工して面１Ｃとし、これをデバイ
ス工程に供したが、素子形成工程中に該基板の周縁部に
欠け、割れ、スクラッチ等の欠陥は全く発生ぜず、また
、完成後の素子の電気的特性も良好であった。Adhesive type semiconductor substrate 3 obtained by direct adhesion in this way
One side (of the semiconductor substrate 1) was subjected to a predetermined roughening process using a grinder, lap, MCP, etc. to form a surface 1C, which was then subjected to a device process. No defects such as cracks or scratches occurred, and the electrical characteristics of the completed device were also good.
［発明の効果］
本発明の方法では被接着面の加工の殆どを研削で行って
いるので縁ダレが発生けず、また軽度なＭＣＰを組み合
わせた鏡面加工をしている。 従って、被接着半導体基
板の直径と等しい直径で、周縁ダレのない、接着型半導
体基板が得られる。[Effects of the Invention] In the method of the present invention, most of the processing of the surface to be adhered is performed by grinding, so no edge sagging occurs, and a mirror finish is achieved by combining mild MCP. Therefore, a bonded semiconductor substrate having a diameter equal to the diameter of the semiconductor substrate to be bonded and having no peripheral sag can be obtained.
このため、材料ロスがなくなる上、外径削溝とし工程が
不要となって工程が短縮し、その結果、従来方法よりも
安価なロスｌ〜で接着型半導体基板を製造づることかで
きるようになった。This eliminates material loss, eliminates the need for the process of cutting the outer diameter grooves, and shortens the process.As a result, it is possible to manufacture bonded semiconductor substrates with less loss than conventional methods. became.
４゜図面の閣１３Ｊな説明
第１図は本発明方法の工程を説明づ−るための図である
。4.DRAWINGS 13J Description FIG. 1 is a diagram for explaining the steps of the method of the present invention.
１．２・・・半導体基板、 ３・・・接合型半導体基板
。1.2... Semiconductor substrate, 3... Junction type semiconductor substrate.
第１図Figure 1
Claims (1)
直接接着することによって製造される接着型半導体基板
の製造方法において、 互いに接着さるべき２枚の半導体基板の各々の被接着面
を、平面研削した後、軽度にメカノケミカルポリッシン
グを施して鏡面とすることを特徴とする接着型半導体基
板の製造方法。 ２ 互いに接着さるべき２枚の半導体基板の各々の被接
着面の平面研削を＃１７００の研削砥石によって研削す
る特許請求の範囲第１項記載の接着型半導体基板の製造
方法。[Claims] 1. In a method for manufacturing an adhesive semiconductor substrate, which is manufactured by directly bonding the mirror surfaces of two semiconductor substrates together in a clean atmosphere, each of the two semiconductor substrates to be bonded to each other has the following steps: A method for manufacturing an adhesive type semiconductor substrate, which comprises flattening a surface to be adhered and then applying light mechanochemical polishing to make it a mirror surface. 2. The method of manufacturing a bonded semiconductor substrate according to claim 1, wherein the surface of each of the two semiconductor substrates to be bonded to each other is ground by using a #1700 grinding wheel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207086A JPS62181418A (en) | 1986-02-05 | 1986-02-05 | Manufacture of bonded type semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2207086A JPS62181418A (en) | 1986-02-05 | 1986-02-05 | Manufacture of bonded type semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62181418A true JPS62181418A (en) | 1987-08-08 |
Family
ID=12072627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2207086A Pending JPS62181418A (en) | 1986-02-05 | 1986-02-05 | Manufacture of bonded type semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62181418A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145873A (en) * | 1987-12-02 | 1989-06-07 | Yokogawa Electric Corp | Manufacture of semiconductor pressure sensor |
| JPH025472A (en) * | 1988-06-23 | 1990-01-10 | Fujitsu Ltd | Solid state image sensor and manufacture thereof |
-
1986
- 1986-02-05 JP JP2207086A patent/JPS62181418A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145873A (en) * | 1987-12-02 | 1989-06-07 | Yokogawa Electric Corp | Manufacture of semiconductor pressure sensor |
| JPH025472A (en) * | 1988-06-23 | 1990-01-10 | Fujitsu Ltd | Solid state image sensor and manufacture thereof |
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