CN116072533B - Wafer and wafer thinning process thereof - Google Patents

Wafer and wafer thinning process thereof Download PDF

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Publication number
CN116072533B
CN116072533B CN202310310908.1A CN202310310908A CN116072533B CN 116072533 B CN116072533 B CN 116072533B CN 202310310908 A CN202310310908 A CN 202310310908A CN 116072533 B CN116072533 B CN 116072533B
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wafer
thinning
thickness
bonding
carrying
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CN116072533A (en
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唐义洲
王中健
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Chengdu Gongcheng Semiconductor Co ltd
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Chengdu Gongcheng Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention discloses a wafer and a wafer thinning process processing technology thereof, and belongs to the technical field of semiconductor processing. The wafer thinning process provided by the invention comprises the following steps: performing a trimming process on the wafer; carrying out laser grooving on the slide glass, and forming a deep groove on the front surface of the slide glass; coating bonding glue on the wafer and washing edges; performing a temporary bonding process on the wafer and the carrier; carrying out first thinning treatment on the wafer; the wafer and the slide glass after thinning are subjected to a de-bonding process; carrying out bonding adhesive coating and edge washing on the thinned wafer; performing a temporary bonding process on the thinned wafer and the slide glass; and carrying out second thinning treatment on the thinned wafer. The processing technology of the wafer thinning process provided by the invention adopts the modes of laser grooving, multiple temporary bonding and thinning combination, prevents fragments and severe thinning of a bonding adhesive layer of a wafer in the thinning process, and ensures the stability and repeatability of the process.

Description

Wafer and wafer thinning process thereof
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a wafer and a wafer thinning process processing technology thereof.
Background
With the update and iteration of semiconductor power devices, silicon Carbide (SiC) materials, which are represented by the third generation of semiconductors, are increasingly being widely used in the field of power devices due to their wide forbidden band, high electron mobility and high thermal conductivity. In the field of power device fabrication, a wafer backside process is often performed. However, the conventional back side process of the monolithic wafer often has a certain influence on the front side of the wafer, so that the wafer needs to be bonded before the back side process, thereby protecting the front side of the wafer.
The traditional silicon carbide wafer thinning process adopts a mode of adding a UV film or a thermal induction film to the wafer for single-chip thinning. By adopting the mode, the silicon carbide wafer is subjected to larger warping due to the generation of internal stress after thinning. Therefore, a back side process method of wafer bonding thinning is developed. In the conventional wafer temporary bonding thinning process, the bonding adhesive layer is thinned due to the existence of the thinning pressing stress, so that deviation of the thinning thickness is finally caused, and the stability of the manufacturing process is affected.
Disclosure of Invention
The invention aims to provide a wafer and a wafer thinning process thereof, which are used for solving the problems that in the traditional wafer temporary bonding thinning process, bonding adhesive layers are thinned due to the existence of thinning pressing stress, and finally the thinning thickness is deviated, so that the stability of the process is affected.
The technical scheme for solving the technical problems is as follows:
the invention provides a wafer thinning process processing technology, which comprises the following steps:
performing a trimming process on the wafer;
carrying out laser grooving on the slide glass, and forming a deep groove on the front surface of the slide glass;
coating bonding glue on the wafer and washing edges;
performing a temporary bonding process on the wafer and the carrier;
carrying out first thinning treatment on the wafer;
the wafer and the slide glass after thinning are subjected to a de-bonding process;
carrying out bonding adhesive coating and edge washing on the thinned wafer;
performing a temporary bonding process on the thinned wafer and the slide glass;
and carrying out second thinning treatment on the thinned wafer.
Further, in the wafer thinning process, the wafer is trimmed in a multiple step manner, and the total trimming depth is greater than or equal to the total thinning depth.
Further, in the wafer thinning process, the wafer is subjected to a first thinning treatment, and the thinning thickness is 85-95% of the total thinning thickness.
Further, in the wafer thinning process, the first thinning treatment is performed by adopting a multi-process mode, and the steps include:
performing primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the primary thinning thickness;
thinning the wafer again, wherein the thickness of the thinned wafer is 15-20% of that of the first thinning;
and polishing the wafer.
Further, in the wafer thinning process, the wafer is subjected to a low temperature annealing treatment between the first thinning treatment and the debonding treatment.
Further, in the wafer thinning process, the temperature of the low-temperature annealing treatment is lower than the melting temperature of the bonding glue.
Further, in the wafer thinning process, the wafer is subjected to a second thinning treatment, and the thinning thickness is 5-15% of the total thinning thickness.
Further, in the wafer thinning process, the second thinning treatment is performed by adopting a multi-process mode, and the steps include:
carrying out primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the secondary thinning thickness;
thinning the wafer again, wherein the thickness of the re-thinned wafer is 15-20% of that of the second thinning;
and polishing the wafer.
Further, in the wafer thinning process, the wafer is cleaned between the debonding process and the edge cleaning process.
The invention also provides a wafer prepared by the wafer thinning process.
The invention has the following beneficial effects:
1. the processing technology of the wafer thinning process provided by the invention adopts the modes of laser grooving, multiple temporary bonding and thinning combination, prevents fragments and severe thinning of a bonding adhesive layer of a wafer in the thinning process, and ensures the stability and repeatability of the process.
2. Because the traditional grinding wheel slotting can cause uneven coating, bubbles and other phenomena in the process of bonding adhesive coating, the wafer thinning process provided by the invention adopts a laser slotting mode to replace the traditional grinding wheel slotting before bonding, and has the advantages that: compared with the grooving of the grinding wheel, the wafer grooved by the laser has smaller groove depth and groove width, so that the coating quality can be ensured during the coating of the bonding adhesive, the occurrence of bubbles and uneven phenomena can be reduced, and the reworking probability can be reduced; a series of narrow deep grooves are formed on the front surface of the carrier sheet so as to increase the contact area between the bonding layer and the bonding solution during bonding, improve the bonding degree of the wafer and the carrier sheet, reduce the requirement on the bonding layer and reduce the bonding time during bonding.
3. In the single thinning process, the thinning process is divided into a plurality of times by adopting a mode of combining multiple bonding and thinning, so that the time of each thinning process is effectively reduced. In addition, after each thinning, the influence of thinning of the bonding adhesive layer is reduced by adopting a bonding-removing and bonding-cleaning mode, so that the influence of severe thinning of the bonding adhesive layer on the repeatability of the manufacturing process is prevented.
4. According to the wafer thinning process provided by the invention, the wafer is trimmed for multiple times, so that the breaking risk in the trimming process due to the fact that the hardness of the wafer is high is reduced; and processing the edge of the wafer into a step shape, so that the risk of breaking the wafer in the subsequent thinning process is reduced.
5. The wafer thinning process provided by the invention is used for carrying out low-temperature annealing on the bonding sheet, so that the internal stress generated in the bonding sheet due to the first thinning is eliminated.
6. The wafer thinning process provided by the invention adopts a multi-process mode for the first thinning treatment or the second thinning treatment, and reduces the risks of edge breaking and burning of bonding sheets in the thinning process by combining proper thinning thickness through different numbers of rotating wheels, rotating numbers of the rotating wheels and steering of the rotating wheels.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a process flow diagram of example 1 of the present invention;
FIG. 2 is a schematic view of the process of step S1 in example 1 of the present invention;
FIG. 3 is a schematic view of the process of step S2 in embodiment 1 of the present invention;
FIG. 4 is a schematic view of the process of step S3 in embodiment 1 of the present invention;
FIG. 5 is a schematic view of the process of step S4 in embodiment 1 of the present invention;
FIG. 6 is a schematic view of the process of step S6 in embodiment 1 of the present invention;
FIG. 7 is a schematic view of the process of step S10 in embodiment 1 of the present invention;
FIG. 8 is a schematic view of the process of step S11 in embodiment 1 of the present invention;
fig. 9 is a schematic diagram of the process of step S13 in embodiment 1 of the present invention.
In the drawings, the reference numerals and corresponding part names:
1. a SiC wafer; 2. a Si slide; 3. and (5) bonding the adhesive layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a processing technology of a wafer thinning process, which comprises the following steps:
s1, performing an edging process on a wafer, wherein the wafer is a SiC wafer.
The wafer trimming is performed in a multi-step trimming mode, and the total trimming depth is greater than or equal to the total thinning depth. In the embodiment of the invention, the trimming process comprises the following specific steps:
step S101, performing primary trimming on a wafer, wherein the trimming width is 2mm, and the depth is 50-100 um;
and S102, performing secondary trimming on the wafer, wherein the trimming width is 3mm, and the depth is the residual thickness required to be thinned.
The wafer is trimmed for multiple times, so that the risk of breakage in the trimming process due to the fact that the hardness of the wafer is high is reduced; and processing the edge of the wafer into a step shape, so that the risk of breaking the wafer in the subsequent thinning process is reduced.
S2, carrying out laser grooving on the slide, wherein in the embodiment of the invention, the slide adopts a Si slide or a glass slide, preferably a Si slide, and the slide is low in cost and easy to control in the process of manufacturing.
A series of narrow deep grooves are formed on the front surface of the carrier sheet so as to increase the contact area between the bonding layer and the bonding solution in the subsequent bonding process and improve the bonding degree of the wafer and the carrier sheet. In the embodiment of the invention, the laser grooving width is 20um and the depth is 50um.
And S3, coating bonding glue on the wafer and washing edges, so that the bonding glue is prevented from overflowing and polluting equipment in the subsequent bonding process. In the embodiment of the invention, the bonding adhesive thickness is 15-20um, and the edge washing width is 5mm.
S4, performing a temporary bonding process on the wafer and the carrier, and bonding the wafer and the carrier into a bonding sheet.
S5, measuring the thickness of the wafer before thinning to determine the thickness of the bonding sheet before bonding.
S6, thinning the bonding sheet for the first time, and thinning the bonding sheet to a certain thickness. When the wafer is thinned for the first time, the thinning thickness is 85-95% of the total thinning thickness.
The first thinning treatment is carried out by adopting a multi-process mode, and comprises the following steps:
s601: performing primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the primary thinning thickness;
s602: thinning the wafer again, wherein the thickness of the thinned wafer is 15-20% of that of the first thinning;
s603: and polishing the wafer.
In the embodiment of the invention, the first thinning thickness is 150-180 um, and the specific steps are as follows:
step S601, primarily thinning the SiC wafer, wherein the number of grinding wheels is 2500 meshes, the rotation number of the grinding wheels is 2400-2500min/R, the direction is anticlockwise rotated, and the thinning thickness is 80% of the first thinning thickness;
step S602, thinning the SiC wafer again, wherein the number of grinding wheels is 2000 meshes, the number of revolutions of the grinding wheels is 2400-2500min/R, the direction is clockwise rotation, and the thinning thickness is 20% of the first thinning thickness;
in step S603, the SiC wafer is subjected to CMP polishing for 2 minutes.
The first thinning treatment is carried out in a multi-process mode, and the risks of edge chipping and burning of the bonding sheet in the thinning process are reduced by combining proper thinning thickness through different numbers of rotating wheels, rotating wheel revolutions and rotating wheels.
And S7, carrying out low-temperature annealing on the bonding sheet to eliminate the internal stress generated in the bonding sheet due to the first thinning. The low temperature annealing temperature is not higher than the bond gum dissolution temperature, typically not higher than 280 ℃.
S8, performing a bonding-removing process on the wafer. In the embodiment of the invention, the bonding process is performed by a soaking method, and the bonding sheet mode is performed in a bonding solution, preferably the solution is limonene.
And S9, cleaning the wafer and the carrier to remove the bonding layer on the wafer and the carrier.
S10, bonding adhesive coating is carried out on the wafer again, and edge washing is carried out. In the embodiment of the invention, the bonding adhesive thickness is 15-20um, and the edge washing width is 5mm.
S11, performing a temporary bonding process on the wafer and the carrier.
S12, measuring the thickness of the bonding sheet before thinning to determine the thickness of the bonding sheet before thinning for the second time.
S13, thinning the bonding sheet for the second time. The thickness reduction is 5-5% of the total thickness reduction.
The second thinning treatment is carried out by adopting a multi-process mode, and comprises the following steps:
carrying out primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the secondary thinning thickness;
thinning the wafer again, wherein the thickness of the re-thinned wafer is 15-20% of that of the second thinning;
and polishing the wafer.
In the embodiment of the invention, the second thinning thickness is the thickness of the residual thickness to be thinned minus the thickness of the twice polishing loss by 1-3um, and the specific steps are as follows:
step S131, primarily thinning the SiC wafer, wherein the number of grinding wheels is 2500 meshes, the rotation number of the grinding wheels is 2400-2500min/R, the direction is anticlockwise rotated, and the thinning thickness is 80% of the first thinning thickness;
step S132, thinning the SiC wafer again, wherein the number of grinding wheels is 2000 meshes, the number of the grinding wheels is 2400-2500min/R, the direction is clockwise rotation, and the thinning thickness is 20% of the first thinning thickness;
and step S133, performing CMP polishing treatment on the SiC wafer, wherein the polishing time is 2min.
The second thinning treatment is carried out in a multi-process mode, and the risks of edge chipping and burning of the bonding sheet in the thinning process are reduced by combining proper thinning thickness through different numbers of rotating wheels, rotating wheel revolutions and rotating wheels.
The processing technology of the wafer thinning process adopts the modes of laser grooving, multiple temporary bonding and thinning combination, prevents fragments and severe thinning of bonding adhesive layers of wafers in the thinning process, and ensures the stability and repeatability of the process.
Because the traditional grinding wheel slotting can cause uneven coating, bubbles and other phenomena in the process of bonding adhesive coating, the wafer thinning process processing technology of the embodiment of the invention adopts a laser slotting mode to replace the traditional grinding wheel slotting before bonding, and has the advantages that: compared with the grooving of the grinding wheel, the wafer grooved by the laser has smaller groove depth and groove width, so that the coating quality can be ensured during the coating of the bonding adhesive, the occurrence of bubbles and uneven phenomena can be reduced, and the reworking probability can be reduced; a series of narrow deep grooves are formed on the front surface of the carrier sheet so as to increase the contact area between the bonding layer and the bonding solution during bonding, improve the bonding degree of the wafer and the carrier sheet, reduce the requirement on the bonding layer and reduce the bonding time during bonding.
In the single thinning process, the thinning process is divided into a plurality of times by adopting a mode of combining multiple bonding and thinning, so that the time of each thinning process is effectively reduced. In addition, after each thinning, the influence of thinning of the bonding adhesive layer is reduced by adopting a bonding-removing and bonding-cleaning mode, so that the influence of severe thinning of the bonding adhesive layer on the repeatability of the manufacturing process is prevented.
According to the wafer thinning process processing technology, the wafer is trimmed for multiple times, so that the breaking risk in the trimming process due to the fact that the hardness of the wafer is high is reduced; and processing the edge of the wafer into a step shape, so that the risk of breaking the wafer in the subsequent thinning process is reduced.
Examples
Referring to fig. 1, the following processing process of the wafer thinning process according to the present invention includes the following steps:
s1, trimming the SiC wafer, wherein the molding result is shown in FIG. 2. The wafer trimming is carried out in a multi-step trimming mode, and the trimming process specifically comprises the following steps:
step S101, trimming the SiC wafer for the first time, wherein the trimming width is 2mm, and the depth is 100um;
and S102, trimming the SiC wafer for the second time, wherein the trimming width is 3mm, and the depth is the residual thickness required to be thinned.
S2, carrying out laser grooving on the Si slide, forming a series of narrow deep grooves on the front surface of the slide, wherein the laser grooving width is 20um, the laser grooving depth is 50um, and the molding result is shown in figure 3.
S3, coating bonding glue on the SiC wafer and washing edges, wherein the bonding glue is 15-20um in thickness and 5mm in edge washing width, and the molding result is shown in FIG. 4.
S4, performing a temporary bonding process on the SiC wafer and the Si slide, and bonding the wafer and the slide into a bonding sheet, wherein the molding result is shown in FIG. 5.
S5, measuring the thickness of the SiC wafer before thinning to determine the thickness of the bonding sheet before bonding.
S6, thinning the bonding sheet for the first time, thinning the bonding sheet to a certain thickness, and forming the result shown in FIG. 6.
In the embodiment of the invention, the first thinning thickness is 150-180 um, and the specific steps are as follows:
step S601, primarily thinning the SiC wafer, wherein the number of grinding wheels is 2500 meshes, the rotation number of the grinding wheels is 2400-2500min/R, the direction is anticlockwise rotated, and the thinning thickness is 80% of the first thinning thickness;
step S602, thinning the SiC wafer again, wherein the number of grinding wheels is 2000 meshes, the number of revolutions of the grinding wheels is 2400-2500min/R, the direction is clockwise rotation, and the thinning thickness is 20% of the first thinning thickness;
in step S603, CMP polishing is performed on the SiC wafer for 2min to ensure the smoothness of the device surface.
And S7, carrying out low-temperature annealing on the bonding sheet to eliminate the internal stress generated in the bonding sheet due to the first thinning.
S8, soaking the SiC wafer in a solution containing limonene, and performing a de-bonding process.
And S9, cleaning the SiC wafer and the Si slide to remove the bonding layer on the wafer and the slide.
S10, bonding glue coating is conducted on the SiC wafer again, and edge washing is conducted. In the embodiment of the invention, the bonding adhesive has the thickness of 15-20um, the edge washing width of 5mm, and the molding result is shown in figure 7.
S11, performing a temporary bonding process on the SiC wafer and the Si slide, wherein the molding result is shown in FIG. 8.
S12, measuring the thickness of the bonding sheet before thinning to determine the thickness of the bonding sheet before thinning for the second time.
S13, thinning the bonding sheet for the second time, and forming a result shown in fig. 9.
In the embodiment of the invention, the second thinning thickness is the thickness of the residual thickness to be thinned minus the thickness of the twice polishing loss by 1-3um, and the specific steps are as follows:
step S131, primarily thinning the SiC wafer, wherein the number of grinding wheels is 2500 meshes, the rotation number of the grinding wheels is 2400-2500min/R, the direction is anticlockwise rotated, and the thinning thickness is 80% of the first thinning thickness;
step S132, thinning the SiC wafer again, wherein the number of grinding wheels is 2000 meshes, the number of the grinding wheels is 2400-2500min/R, the direction is clockwise rotation, and the thinning thickness is 20% of the first thinning thickness;
and step S133, performing CMP polishing treatment on the SiC wafer, wherein the polishing time is 2min.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. The wafer thinning process is characterized by comprising the following steps:
performing a trimming process on the wafer;
carrying out laser grooving on the slide glass, and forming a deep groove on the front surface of the slide glass;
coating bonding glue on the wafer and washing edges;
performing a temporary bonding process on the wafer and the carrier;
carrying out first thinning treatment on the wafer;
the wafer and the slide glass after thinning are subjected to a de-bonding process;
carrying out bonding adhesive coating and edge washing on the thinned wafer;
performing a temporary bonding process on the thinned wafer and the slide glass;
and carrying out second thinning treatment on the thinned wafer.
2. The process of claim 1, wherein the wafer is trimmed in a plurality of steps, and the total depth of trimming is greater than or equal to the total depth of thinning.
3. The wafer thinning process according to claim 1, wherein the thickness of the wafer is 85-95% of the total thickness of the wafer during the first thinning process.
4. A wafer thinning process according to claim 1 or claim 3, wherein the first thinning is performed by a multi-process method, comprising the steps of:
performing primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the primary thinning thickness;
thinning the wafer again, wherein the thickness of the thinned wafer is 15-20% of that of the first thinning;
and polishing the wafer.
5. The wafer thinning process according to claim 1, wherein the wafer is further subjected to a low temperature annealing treatment between the first thinning treatment and the debonding treatment.
6. The wafer thinning process according to claim 5, wherein the low temperature annealing is performed at a temperature lower than a melting temperature of the bond paste.
7. The wafer thinning process according to claim 1, wherein the thickness of the wafer is 5-15% of the total thickness of the wafer during the second thinning process.
8. The wafer thinning process according to claim 1 or 7, wherein the second thinning process is performed by a multi-process method, comprising the steps of:
carrying out primary thinning on the wafer, wherein the primary thinning thickness is 80-85% of the secondary thinning thickness;
thinning the wafer again, wherein the thickness of the re-thinned wafer is 15-20% of that of the second thinning;
and polishing the wafer.
9. The wafer thinning process according to claim 1, wherein the wafer is further cleaned between the debonding process and the edge cleaning process.
10. A wafer prepared by the wafer thinning process according to any one of claims 1-9.
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