CN110323178A - A kind of manufacturing process method in zero cavity of SOI wafer edge - Google Patents

A kind of manufacturing process method in zero cavity of SOI wafer edge Download PDF

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Publication number
CN110323178A
CN110323178A CN201910597378.7A CN201910597378A CN110323178A CN 110323178 A CN110323178 A CN 110323178A CN 201910597378 A CN201910597378 A CN 201910597378A CN 110323178 A CN110323178 A CN 110323178A
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wafer
silicon
soi wafer
soi
edge
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CN201910597378.7A
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李彦庆
方小磊
陈艳明
张凯
赵东旭
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Changchun Long Round Chen Microelectronic Technology Co Ltd
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Changchun Long Round Chen Microelectronic Technology Co Ltd
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Priority to CN201910597378.7A priority Critical patent/CN110323178A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention discloses a kind of manufacturing process methods in zero cavity of SOI wafer edge, belong to SOI wafer material manufacturing field, this method comprises the following steps: step S01, early-stage preparations；Step S02, wafer once grinds off edge processing；Step S03, wafer bonding；Step S04, wafer is once thinned；Step S05, wafer is secondary grinds off edge processing；Step S06, wet etching edge excess silicon, so that two wafer bonding interfaces are without cavity；Step S07, wafer is secondary is thinned: by mechanical thinning process and chemical mechanical milling tech, realizing final thickness.The present invention uses bonding pattern under normal temperature and pressure, using optical alignment principle, alignment precision can guarantee within 50 microns, the present invention realized in the case where not increasing SOI manufacturing cost SOI wafer in normal temperature and pressure environment when Direct Bonding without cavity blemish, there are boundless market prospects.

Description

A kind of manufacturing process method in zero cavity of SOI wafer edge
Technical field
The invention belongs to SOI wafer material manufacturing fields, and in particular to a kind of manufacturing process in zero cavity of SOI wafer edge Method.
Background technique
SOI, that is, Silicon on Insulator, the silicon wafer based on insulator please refer to Fig. 1 to Fig. 5, a kind of existing By Direct Bonding technique manufacture SOI wafer method.Process flow includes the following steps: 1, as shown in Figures 1 and 2, standard Standby two panels covers oxygen layer as SOI wafer with the wafer A1 and wafer B2 of size, at least wafer surface growth oxide layer；2, As shown in figure 3, it is 2 millimeters that marginal surface, which grinds off width, 100 microns of depth by eventually as that wafer A1 of SOI wafer Silicon；3, it as shown in figure 4, two wafers are passed through corona treatment at room temperature, at a normal, is dried after water-bath, passes through bonding Equipment carries out Direct Bonding, and carries out thermal annealing with wafer after the temperature para-linkage lower than 800 DEG C, realizes two panels wafer bonding circle Face forms covalent bond；4, as shown in figure 5, by two wafers after bonding, wafer A1 passes through mechanical thinning process and chemical machinery Grinding technics realizes final thickness.
Wherein when step 3 wafer direct bonding, crystal round fringes a large amount of cavities since Joule-Thomson effect generates.Cavity Defect absolutely not allows SOI wafer.SOI crystalline substance is generally carried out in prior art using low pressure characteristics of Direct Wafer Bonded Round key closes, but due to needing to purchase a set of low-pressure bonding technology equipment, increases manufacturing cost.In view of this, it is necessary to provide one Wafer direct bonding legal system makes the process of SOI wafer under kind normal temperature and pressure.
Summary of the invention
When in order to solve wafer direct bonding in the prior art, crystal round fringes are a large amount of since Joule-Thomson effect generates Empty problem, the present invention provides a kind of manufacturing process methods in zero cavity of SOI wafer edge.
The present invention to solve above-mentioned technical problem the technical solution adopted is that:
A kind of manufacturing process method in zero cavity of SOI wafer edge, which is characterized in that this method comprises the following steps, and Following steps sequentially carry out:
Step S01, early-stage preparations: prepare two panels with the wafer of size, wafer is as in SOI wafer silicon dioxide layer Silicon, another wafer cover oxygen layer as SOI wafer as SOI wafer silicon substrate, at least wafer surface growth oxide layer；
Step S02, wafer once grinds off edge processing: will be as the wafer of silicon in SOI wafer silicon dioxide layer or surface The wafer of oxide layer is not grown, and it is 1 millimeter that marginal surface, which grinds off width, the silicon that depth is 100 microns；
Step S03, wafer bonding: two wafers are passed through into corona treatment at normal temperatures and pressures, by water after processing It is dried after bath, Direct Bonding, and carries out thermal annealing with wafer after the temperature para-linkage lower than 500 DEG C,
It realizes that two panels wafer bonding interface forms covalent bond, after thermal annealing, uses ultrasound scanning unit para-linkage wafer Carry out empty scanning；
Step S04, wafer is once thinned:, will be as the silicon layer on the wafer of silicon in SOI wafer silicon dioxide layer after bonding Thickness is ground to 320 microns；
Step S05, wafer is secondary grinds off edge processing: by the crystal column surface side as silicon in SOI wafer silicon dioxide layer It is 4 millimeters that edge, which grinds off width, the silicon that 300 microns of depth, so that the crystal round fringes silicon layer as silicon in SOI wafer silicon dioxide layer is pre- It stays with a thickness of 20 microns；
Step S06, wet etching edge excess silicon: will be in step S05 using the tetramethylammonium hydroxide that concentration is 5% 20 micron thickness silicon layers erode, while getting rid of as the cavity in SOI wafer silicon dioxide layer on the crystal round fringes of silicon, make Two panels wafer bonding interface is obtained without cavity；
Step S07, wafer is secondary is thinned: by mechanical thinning process and chemical mechanical milling tech, realizing SOI wafer most Whole thickness.
Preferably, two panels crystal column surface grows cover oxygen layer of the oxide layer as SOI wafer in step S01, and as SOI The crystal column surface of silicon grows 100 nano silicas by boiler tube thermal oxidation method in wafer silicon dioxide layer, as SOI wafer silicon The crystal column surface of base grows 500 nanometers of silica by boiler tube thermal oxidation method.
Preferably, the hot oxygen temperature in the thermal oxidation method is greater than 1000 DEG C.
The manufacturing process method in above-mentioned zero cavity of SOI wafer edge, further includes: after wafer once grinds off edge processing, By two wafers by first of RCA cleaning process cleaning, surface particles are removed, 75 DEG C of cleaning process environment temperature, are matched H2O2/H2O/NH4OH=1:4:50, so that two panels crystal column surface granularity is 0.2 micron less than 20, then by two wafers It is cleaned by second RCA cleaning process, removes crystal column surface metallic, 75 DEG C of cleaning process environment temperature, match H2O2/ H2O/HCl=1:2:8, so that wafer full wafer surface metal number atomicity per cubic centimeter is less than 5 × 1010。
Further, edge processing is once ground off in step S02 wafer and step S05 wafer is secondary grinds off edge processing process In be all made of #1500 diamond blade carry out edging, and rotating speed of flail be 2000 turns per minute.
Wherein, bath temperature is 80 DEG C in the step S03.
Through the above design, the present invention can be brought the following benefits:
Existing SOI uses bonding method processing technology, and two wafers are carried out silicon wafer key using low pressure volumes bonding machine platform It closes, bonding uses mechanical registeration, due to using vacuum environment Direct Bonding that alignment precision is caused to reduce, the same size of two panels in cavity The cut alignment precision of wafer is extremely difficult within 50 microns.The present invention uses bonding pattern under normal temperature and pressure, while using light Alignment principles are learned, alignment precision can guarantee within 50 microns.
It further has the beneficial effect that, the technique that existing SOI is processed by bonding method, first by wafer edging, generally The edging blade choice accuracy of processing technology not enough causes crystal round fringes chipping or dark line occur, very to inside wafer damage Greatly.The present invention carries out edging using 1500# diamond blade, and reducing blade reduces granularity pollution to the damage of wafer, it is ensured that Wafer edging back edge is smooth.
The present invention is realized in the case where not increasing SOI manufacturing cost (exclusively carrying out the board of SOI bonding without buying) SOI wafer in normal temperature and pressure environment when Direct Bonding without cavity blemish, there are boundless market prospects.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair Bright illustrative embodiments and their description explanation does not constitute improper restriction of the invention for understanding the present invention, in the accompanying drawings:
Fig. 1, which is that one kind is existing, manufactures wafer A structural schematic diagram in the method for SOI wafer by Direct Bonding technique.
Fig. 2, which is that one kind is existing, manufactures wafer B structure schematic diagram in the method for SOI wafer by Direct Bonding technique.
Fig. 3 is that wafer A marginal surface grinds off width in the existing method by Direct Bonding technique manufacture SOI wafer of one kind It is 2 millimeters, the structural schematic diagram after the silicon that 100 microns of depth.
Fig. 4 is that wafer A and wafer B is bonded in the existing method by Direct Bonding technique manufacture SOI wafer of one kind Combining structure schematic diagram after together.
Fig. 5 is a kind of existing two wafers manufactured in the method for SOI wafer after bonding by Direct Bonding technique, brilliant Circle A realizes the structural schematic diagram of final thickness by mechanical thinning process and chemical mechanical milling tech.
Fig. 6 is the first crystal circle structure in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention Schematic diagram.
Fig. 7 is the second crystal circle structure in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention Schematic diagram.
Fig. 8 is the first crystal column surface in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention Pass through structural schematic diagram after boiler tube thermal oxidation method 100 nano silicas of growth.
Fig. 9 is the second crystal column surface in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention Pass through structural schematic diagram after 500 nanometers of the growth of boiler tube thermal oxidation method of silica.
Figure 10 is the first wafer in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention through one The secondary structural schematic diagram ground off behind edge.
Figure 11 is the first wafer and the in a kind of manufacturing process method in zero cavity of SOI wafer edge of the embodiment of the present invention The SOI wafer semi-finished product structure schematic diagram that two wafer bondings obtain together.
Figure 12 be SOI wafer semi-finished product in Figure 11 the first wafer after primary thinned structural schematic diagram.
Figure 13 be Figure 12 in SOI wafer semi-finished product the first wafer through it is secondary grind off edge after structural schematic diagram.
Figure 14 be in SOI wafer semi-finished product in Figure 13 the first wafer through wet etching edge excess silicon treated structure Schematic diagram.
Figure 15 is that edge zero made from a kind of empty manufacturing process method in SOI wafer edge zero is empty in the embodiment of the present invention The SOI wafer finished product structure schematic diagram in hole.
It is respectively marked in figure as follows: the first wafer of 1- wafer A, 2- wafer B, 3-, the second wafer of 4-.
Specific embodiment
In order to illustrate more clearly of the present invention, the present invention is done further below with reference to preferred embodiments and drawings It is bright.It should be understood by those skilled in the art that.Specifically described content is illustrative and be not restrictive below, is not being departed from In the case where the invention mechanism and range that are illustrated in claim, user can carry out various changes to following parameters.For Essence of the invention of avoiding confusion, well known method and process are not described in detail.
In the description of the present invention, it is to be understood that, term " first ", " second " are used for description purposes only, and define The feature of " first " and " second " is not offered as any sequence, quantity or importance, and is used only to distinguish different compositions Part.
As shown in Fig. 6 to Figure 15, a kind of manufacturing process method in zero cavity of SOI wafer edge includes the following steps, and with Lower step sequentially carries out:
Step S01, early-stage preparations:
As shown in FIG. 6 and 7, the wafer of the identical size of preparation two panels, respectively the first wafer 3, the second wafer 4, first Wafer 3 and the second wafer 4 are all made of vertical pulling method or magnetic field Czochralski method growth, low-doped boron atom (atomicity 2 per cubic centimeter ×1015), the first wafer 3 and the second wafer 4 can be two panels diameter be 200 millimeters, silicon substrate with a thickness of 725 microns and crystal orientation < 100>p-type polished silicon wafer, be also possible to that two panels diameter is 300 millimeters, silicon substrate is thrown with a thickness of the p-type of 775 microns and crystal orientation<100> Mating plate, but the first wafer 3 and 4 silicon substrate diameter of the second wafer to be bonded must be identical；
As shown in figure 8,3 surface of the first wafer grows 100 nano silicas by boiler tube thermal oxidation method, as shown in figure 9, Second wafer, 4 surface grows 500 nanometers of silica by boiler tube thermal oxidation method, and hot oxygen temperature is greater than 1000 DEG C, but first The silicon dioxide thickness of wafer 3 and the second wafer 4 is not restricted to this, can be adjusted according to application requirement, 200 milli of diameter Rice, the flatness for the wafer that 725 microns of silicon substrate thickness are less than 0.7 micron；300 mm diameter, 775 microns of silicon substrate thickness Wafer planarization degree is less than 0.2 micron；
Step S02, wafer once grinds off edge processing:
As shown in Figure 10,3 marginal surface of the first wafer is ground off to the silicon 1 millimeter wide, depth is 100 microns, Wafer wafer Edging technique use #1500 diamond blade, 2000 turns per minute of revolving speed, check edging after 3 surface of the first wafer smooth zero It scratches, zero dark line is not greater than 4 microns of particle；
After once grinding off edge, the first wafer 3 is used as SOI as silicon in SOI wafer silicon dioxide layer, the second wafer 4 Wafer silicon substrate removes surface particles, cleaned by the first wafer 3 and the second wafer 4 by first of RCA cleaning process cleaning 75 DEG C of journey environment temperature, match H2O2/H2O/NH4It is brilliant to measure the first wafer of guarantee 3 and second by OH=1:4:50 after cleaning 4 surface particles degree of circle are 0.2 micron and pass through second RCA scavenger less than 20, then by the first wafer 3 and the second wafer 4 Skill cleaning removes crystal column surface metallic, 75 DEG C of cleaning process environment temperature, matches H2O2/H2O/HCl=1:2:8, wafer Wafer full wafer surface metal number atomicity per cubic centimeter is less than 5 × 1010；
Step S03, wafer bonding:
As shown in figure 11, two wafers are passed through into corona treatment at normal temperatures and pressures, are dried after 80 DEG C of water-baths, Direct Bonding is carried out by bonding apparatus, the wafer after bonding is in high temperature oven, after being used below 500 DEG C of temperature para-linkage Wafer carries out thermal annealing, is filled with nitrogen or oxygen in baking oven, as protective gas, heat is moved back in 500 DEG C of technological temperature Fire realized that two panels wafer bonding interface forms covalent bond after 1 hour；It is brilliant using ultrasound scanning unit para-linkage after thermal annealing Circle carries out empty scanning, and scanning accuracy is 5 × 5 microns, and bonded interface cavity is evenly distributed in 2 millimeters of crystal round fringes；
Step S04, wafer is once thinned:
As shown in figure 12, by mechanical reduction equipment that the silicon of the first wafer 3 is micro- by 725 by two wafers after bonding Rice is ground to 320 microns；
Step S05, wafer is secondary grinds off edge processing:
As shown in figure 13,3 marginal surface of the first wafer after grinding is ground off width is 2 millimeters, the silicon that 300 microns of depth, In reserved 20 microns of the silicon face in 3 edge of the first wafer；
Step S06, wet etching edge excess silicon:
As shown in figure 14, the tetramethylammonium hydroxide TMAH for the use of concentration being 5%, temperature are 80 DEG C, the time 1 hour item The 20 micron thickness silicon that edge in step S05 is reserved are eroded under part, while will be bonded at 2 millimeters in 3 edge of the first wafer Cavity is got rid of, and the first wafer 3 and 4 bonded interface of the second wafer are without cavity；
Step S07, wafer is secondary is thinned, and realizes final thickness:
As shown in figure 15, the first wafer 3 is ground to 20 microns by mechanical thinning process, then passes through chemical mechanical grinding CMP process realizes 17 microns of final thickness, and surface roughness is less than 1 micron.

Claims (6)

1. a kind of manufacturing process method in zero cavity of SOI wafer edge, which is characterized in that this method comprises the following steps, and with Lower step sequentially carries out:
Step S01, early-stage preparations: preparing two panels with the wafer of size, wafer as silicon in SOI wafer silicon dioxide layer, Another wafer covers oxygen layer as SOI wafer as SOI wafer silicon substrate, at least wafer surface growth oxide layer；
Step S02, wafer once grinds off edge processing: will not give birth to as the wafer of silicon in SOI wafer silicon dioxide layer or surface The wafer of long oxide layer, it is 1 millimeter that marginal surface, which grinds off width, the silicon that depth is 100 microns；
Step S03, wafer bonding: two wafers are passed through into corona treatment at normal temperatures and pressures, after processing after water-bath Drying, Direct Bonding, and thermal annealing is carried out with wafer after the temperature para-linkage lower than 500 DEG C, realize two panels wafer bonding interface Covalent bond is formed, after thermal annealing, ultrasound scanning unit para-linkage wafer is used to carry out empty scanning；
Step S04, wafer is once thinned:, will be as the silicon layer thickness on the wafer of silicon in SOI wafer silicon dioxide layer after bonding It is ground to 320 microns；
Step S05, wafer is secondary grinds off edge processing: will grind as the crystal column surface edge of silicon in SOI wafer silicon dioxide layer Falling width is 4 millimeters, the silicon that 300 microns of depth, so that the crystal round fringes silicon layer as silicon in SOI wafer silicon dioxide layer reserves thickness Degree is 20 microns；
Step S06, wet etching edge excess silicon: the tetramethylammonium hydroxide for the use of concentration being 5% is micro- by 20 in step S05 Meter Hou Du silicon layer erodes, while getting rid of as the cavity in SOI wafer silicon dioxide layer on the crystal round fringes of silicon, so that two Wafer bonded interface is without cavity；
Step S07, wafer is secondary is thinned: by mechanical thinning process and chemical mechanical milling tech, realizing that SOI wafer is finally thick Degree.
2. a kind of manufacturing process method in zero cavity of SOI wafer edge according to claim 1, it is characterised in that: step Two panels crystal column surface grows cover oxygen layer of the oxide layer as SOI wafer in S01, and as silicon in SOI wafer silicon dioxide layer Crystal column surface 100 nano silicas are grown by boiler tube thermal oxidation method, the crystal column surface as SOI wafer silicon substrate passes through furnace Pipe thermal oxidation method grows 500 nanometers of silica.
3. a kind of manufacturing process method in zero cavity of SOI wafer edge according to claim 2, it is characterised in that: described Hot oxygen temperature in thermal oxidation method is greater than 1000 DEG C.
4. a kind of manufacturing process method in zero cavity of SOI wafer edge according to claim 1, which is characterized in that also wrap It includes: after wafer once grinds off edge processing, by two wafers by first of RCA cleaning process cleaning, removing surface particles, 75 DEG C of cleaning process environment temperature, match H2O2/H2O/NH4OH=1:4:50, so that two panels crystal column surface granularity is 0.2 micro- Cleaning less than 20, then by two wafers by second RCA cleaning process for rice, removes crystal column surface metallic, cleaning 75 DEG C of process environment temperature, match H2O2/H2O/HCl=1:2:8, so that wafer full wafer surface metal number atom per cubic centimeter Number is less than 5 × 1010。
5. a kind of manufacturing process method in zero cavity of SOI wafer edge according to claim 1, it is characterised in that: in step Rapid S02 wafer once grinds off edge processing and the secondary edge processing that grinds off of step S05 wafer is all made of #1500 diamond in the process Blade carries out edging, and rotating speed of flail is 2000 turns per minute.
6. a kind of manufacturing process method in zero cavity of SOI wafer edge according to claim 1, it is characterised in that: described Bath temperature is 80 DEG C in step S03.
CN201910597378.7A 2019-07-04 2019-07-04 A kind of manufacturing process method in zero cavity of SOI wafer edge Pending CN110323178A (en)

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Cited By (7)

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CN110676159A (en) * 2019-10-24 2020-01-10 武汉新芯集成电路制造有限公司 Wafer bonding method and device
CN110767590A (en) * 2019-10-31 2020-02-07 长春长光圆辰微电子技术有限公司 Method for aligning and bonding two silicon wafers by using silicon wafer notches
CN110767589A (en) * 2019-10-31 2020-02-07 长春长光圆辰微电子技术有限公司 SOI silicon wafer alignment bonding method
CN115070515A (en) * 2022-06-20 2022-09-20 长春长光圆辰微电子技术有限公司 Method for reducing CMP large area edge peeling in GOI production
CN115947299A (en) * 2022-12-21 2023-04-11 上海芯物科技有限公司 Surface processing technology and semiconductor device
CN116072533A (en) * 2023-03-28 2023-05-05 成都功成半导体有限公司 Wafer and wafer thinning process thereof
CN117524870A (en) * 2023-12-29 2024-02-06 物元半导体技术(青岛)有限公司 Wafer processing method and wafer

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CN106847739A (en) * 2015-12-04 2017-06-13 上海新微技术研发中心有限公司 Method for manufacturing silicon-on-insulator material
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CN110676159A (en) * 2019-10-24 2020-01-10 武汉新芯集成电路制造有限公司 Wafer bonding method and device
CN110767590A (en) * 2019-10-31 2020-02-07 长春长光圆辰微电子技术有限公司 Method for aligning and bonding two silicon wafers by using silicon wafer notches
CN110767589A (en) * 2019-10-31 2020-02-07 长春长光圆辰微电子技术有限公司 SOI silicon wafer alignment bonding method
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CN115070515A (en) * 2022-06-20 2022-09-20 长春长光圆辰微电子技术有限公司 Method for reducing CMP large area edge peeling in GOI production
CN115947299A (en) * 2022-12-21 2023-04-11 上海芯物科技有限公司 Surface processing technology and semiconductor device
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CN117524870A (en) * 2023-12-29 2024-02-06 物元半导体技术(青岛)有限公司 Wafer processing method and wafer
CN117524870B (en) * 2023-12-29 2024-06-11 物元半导体技术(青岛)有限公司 Wafer processing method and wafer

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Application publication date: 20191011