CN103871870A - Method for removing wafer bonding edge defect - Google Patents
Method for removing wafer bonding edge defect Download PDFInfo
- Publication number
- CN103871870A CN103871870A CN201410072295.3A CN201410072295A CN103871870A CN 103871870 A CN103871870 A CN 103871870A CN 201410072295 A CN201410072295 A CN 201410072295A CN 103871870 A CN103871870 A CN 103871870A
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- Prior art keywords
- wafer
- wafer bonding
- sull
- edge defect
- bonding
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 230000007547 defect Effects 0.000 title claims abstract description 51
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 9
- 238000000280 densification Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 239000002994 raw material Substances 0.000 claims description 5
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a method for removing a wafer bonding edge defect. The method comprises the steps of providing a wafer to be bonded; depositing a layer of oxide film with the deposit rate being greater than 1.6TTV on a bonding surface of the wafer by utilizing a chemical vapor deposition method; performing a densifying process on the oxide film; performing a planarization process on the oxide film subjected to the densifying process, wherein the planarization grinding rate is greater than 0.9TTV, and the surplus of the oxide film is greater than 0.4TTV; bonding the wafer. By utilizing the chemical vapor deposition method, the oxide film with the deposit rate being greater than 1.6TTV is deposited on the bonding surface of the wafer, and in addition, the oxide film is subjected to planarization, and process parameters, such as the planarization grinding rate which is greater than 0.9TTV, and the surplus of the oxide film which is greater than 0.4TTV are set, so that the problem that the edge of the wafer has defects after the wafer is bonded is solved, a good substrate is provided for the subsequent manufacture procedure, and further the yield of products is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method of removing wafer bonding edge defect.
Background technology
Wafer bonding is an important technique in the semiconductor technologies such as 3D-IC, and the subject matter that current wafer bonding technique exists is that the crystal round fringes after bonding exists more defect, causes the yield of product in subsequent technique to reduce.
In prior art, to the solution of the problems referred to above be: choose the wafer raw material that flatness is higher or seek advanced wafer bonding formula.
Adopt above-mentioned solution, although can improve the impact that defect is brought, the still defect of cancel key synthetic rounded edge (showing as gap or splitting) fundamentally.Concrete condition as shown in Figure 1, its be after existing wafer bonding under ultrasonic scanning microscope, for the schematic diagram of crystal round fringes scanning, Fig. 1 can observe grayish part clearly, the part 10 of its defect that is crystal round fringes.In order to check the situation of wafer bonding and to carry out follow-up processing procedure, need the wafer after para-linkage to carry out sander and edge mechanical treatment, wherein, Fig. 2 be after existing wafer bonding, polish and edge mechanical treatment after, the schematic diagram of crystal round fringes under light microscope, gap area 20 is part 10 shown situation after polishing and mechanical treatment of the defect of crystal round fringes in Fig. 1 as shown in Figure 2.After follow-up bonding, in the process of wafer polishing attenuate, these defects can cause crystal round fringes peels off, and the fragment peeling off further becomes the next defect source of technique, and then has reduced the yield of product.
To sum up, need a kind of method that new removal wafer bonding edge defect is provided badly, with the problem of the defect of cancel key synthetic rounded edge fundamentally.
Summary of the invention
The object of the present invention is to provide a kind of method of removing wafer bonding edge defect, to solve in prior art, carry out after bonding for wafer, still there is the phenomenon of defect (showing as gap or splitting) in crystal round fringes, cause in the process of the wafer polishing attenuate of follow-up bonding, these defects can cause crystal round fringes peels off, and the fragment peeling off further becomes the next defect source of technique, has reduced the problem of the yield of product.
To achieve the above object, the invention provides a kind of method of removing wafer bonding edge defect, comprise step: provide the wafer for the treatment of bonding;
Utilizing the method for chemical vapor deposition, is the sull that is greater than 1.6TTV at bonding face deposit one deck deposition of described wafer;
Described sull is carried out to densification process;
Sull after densification process is carried out to flatening process, and the amount of grinding of planarization is greater than 0.9TTV, and the surplus of sull is greater than 0.4TTV;
The above-mentioned treated wafer for the treatment of bonding is carried out to wafer bonding technique.
Optionally, in the method for described removal wafer bonding edge defect, described sull is with TEOS and O
3for the SiO of raw material deposit
2film.
Optionally, in the method for described removal wafer bonding edge defect, described sull is TEOS film.
Optionally, in the method for described removal wafer bonding edge defect, the parameter of described densification process is: temperature is controlled at 300 DEG C～400 DEG C, and the time is controlled at 0.5h～3h.
Optionally, in the method for described removal wafer bonding edge defect, described TTV is the degree of depth of groove the darkest in defects of wafer edge.
Optionally, in the method for described removal wafer bonding edge defect, described planarization is to be realized by chemical mechanical milling tech.
Optionally, in the method for described removal wafer bonding edge defect, described planarization is carried out number of times and is equaled 1 time.
In the method for removal wafer bonding edge defect provided by the invention, by utilizing the method for chemical vapor deposition, bonding face deposit one deck deposition at described wafer is the sull that is greater than 1.6TTV, and sull is carried out to flatening process, the amount of grinding of planarization is greater than 0.9TTV, the surplus of sull is greater than the setting of the technological parameter of 0.4TTV, overcome the problem that wafer bonding back edge exists defect (showing as gap or splitting), for successive process provides good substrate, and then improve the yield of product.
Brief description of the drawings
Fig. 1 be after existing wafer bonding under ultrasonic scanning microscope, for the schematic diagram of crystal round fringes scanning;
Fig. 2 be after existing wafer bonding, polish and edge mechanical treatment after, the schematic diagram of crystal round fringes under light microscope;
Fig. 3 is the flow chart of the method for removal wafer bonding edge defect of the present invention;
Fig. 4 utilizes after the method for removal wafer bonding edge defect of the present invention, the schematic diagram scanning for crystal round fringes under ultrasonic scanning microscope;
Fig. 5 is the method for utilizing removal wafer bonding edge defect of the present invention, polish and edge mechanical treatment after the schematic diagram of crystal round fringes under light microscope;
Fig. 6 is the schematic diagram of defects of wafer edge before bonding.
Embodiment
Below with reference to Fig. 1～Fig. 6, the method for removal wafer bonding edge defect of the present invention is described in further detail.
Please refer to Fig. 3, it is the method for removal wafer bonding edge defect of the present invention, comprises step:
S1, provide the wafer for the treatment of bonding;
S2, utilizing the method for chemical vapor deposition, is the sull that is greater than 1.6TTV at bonding face deposit one deck deposition of described wafer;
S3, described sull is carried out to densification process;
S4, the sull after densification process is carried out to flatening process, the amount of grinding of planarization is greater than 0.9TTV, and the surplus of sull is greater than 0.4TTV;
S5, the above-mentioned treated wafer for the treatment of bonding is carried out to wafer bonding technique.
Preferably, described sull is with TEOS and O
3for the SiO of raw material deposit
2film.
Preferably, described sull is TEOS film.Tetraethoxysilane, english abbreviation is TEOS, molecular formula can be write Si(OC
2h
5)
4, in middle temperature deposition process, adopt low pressure pyrolysis tetraethoxysilane to form SiO
2inter-level dielectric film.Compared with other oxide deposition process, for example low temperature or high-temperature deposition method are compared, and this method is providing some advantages aspect the uniformity of the oxide skin(coating) of gained or density, and have good film thickness uniformity and repeatability, and its cost is than using SiH
4and N
2o is raw material deposit SiO
2cheap a lot, ensureing preferably also to have reduced the cost consuming in performance, save the spending of enterprise.
Preferably, the parameter of described densification process is: temperature is controlled at 300 DEG C～400 DEG C, and the time is controlled at 0.5h～3h.
Preferably, described TTV is the degree of depth of groove 2 the darkest in wafer 1 edge defect.Concrete, for the understanding of TTV incorporated by reference to Fig. 6.
Preferably, described planarization is to be realized by chemical mechanical milling tech.
Preferably, described planarization need be carried out number of times and is more than or equal to 1 time.Be the sull that is greater than 1.6TTV at the bonding face deposit one deck deposition that ensures wafer, the amount of grinding of planarization is greater than 0.9TTV, when the surplus of sull is greater than the restriction of these three parameters of 0.4TTV, planarization only needs to carry out once, just can remove the defect of crystal round fringes.Further simplify technique, avoided in traditional planar metallization processes, need repeatedly just can reach needed effect.
Concrete, please refer to Fig. 1 and Fig. 4.Wherein, Fig. 4 utilizes after the method for removal wafer bonding edge defect of the present invention, the schematic diagram scanning for crystal round fringes under ultrasonic scanning microscope, compare with Fig. 1, can significantly observe and in Fig. 4, not have light grey part, the part that is the defect of crystal round fringes has obvious removal, and corresponding region is 100.
Please refer to Fig. 2 and Fig. 5.Wherein, Fig. 5 is the method for utilizing removal wafer bonding edge defect of the present invention, polish and edge mechanical treatment after the schematic diagram of crystal round fringes under light microscope, compare with Fig. 2, can significantly observe apertured region 20 in Fig. 2, in Fig. 5, there is not gap, corresponding this region is 200, and then can prove in the method that has used removal wafer bonding edge defect of the present invention, can remove the defect at wafer bonding edge, for successive process provides good substrate, and then improve the yield of product.
To sum up, in the method for removal wafer bonding edge defect provided by the invention, by utilizing the method for chemical vapor deposition, bonding face deposit one deck deposition at described wafer is the sull that is greater than 1.6TTV, and sull is carried out to flatening process, the amount of grinding of planarization is greater than 0.9TTV, the surplus of sull is greater than the setting of the technological parameter of 0.4TTV, overcome the problem that wafer bonding back edge exists defect (showing as gap or splitting), for successive process provides good substrate, and then improve the yield of product.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (7)
1. a method of removing wafer bonding edge defect, is characterized in that, comprises step:
The wafer for the treatment of bonding is provided;
Utilizing the method for chemical vapor deposition, is the sull that is greater than 1.6TTV at bonding face deposit one deck deposition of described wafer;
Described sull is carried out to densification process;
Sull after densification process is carried out to flatening process, and the amount of grinding of planarization is greater than 0.9TTV, and the surplus of sull is greater than 0.4TTV;
The above-mentioned treated wafer for the treatment of bonding is carried out to wafer bonding technique.
2. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, described sull is with TEOS and O
3for the SiO of raw material deposit
2film.
3. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, described sull is TEOS film.
4. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, the parameter of described densification process is: temperature is controlled at 300 DEG C～400 DEG C, and the time is controlled at 0.5h～3h.
5. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, described TTV is the degree of depth of groove the darkest in defects of wafer edge.
6. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, described planarization is to be realized by chemical mechanical milling tech.
7. the method for removal wafer bonding edge defect as claimed in claim 1, is characterized in that, described planarization is carried out number of times and equaled 1 time.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410072295.3A CN103871870B (en) | 2014-02-28 | 2014-02-28 | A kind of method of removing wafer bonding edge defect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410072295.3A CN103871870B (en) | 2014-02-28 | 2014-02-28 | A kind of method of removing wafer bonding edge defect |
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| Publication Number | Publication Date |
|---|---|
| CN103871870A true CN103871870A (en) | 2014-06-18 |
| CN103871870B CN103871870B (en) | 2016-05-25 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105140143A (en) * | 2015-07-30 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Wafer bonding process |
| CN105826182A (en) * | 2016-05-25 | 2016-08-03 | 上海华力微电子有限公司 | Method of optimizing wafer edge defect of CMOS image sensor |
| CN108461512A (en) * | 2018-02-02 | 2018-08-28 | 豪威科技(上海)有限公司 | wafer bonding structure and wafer bonding method |
| CN108899268A (en) * | 2018-06-28 | 2018-11-27 | 武汉新芯集成电路制造有限公司 | A kind of preprocess method improving the performance of wafer bonding technique bubble |
| CN110459555A (en) * | 2019-08-29 | 2019-11-15 | 长春长光圆辰微电子技术有限公司 | Manufacturing process method of the back side illumination image sensor crystal round fringes without silicon fiml defect |
| CN110571163A (en) * | 2019-09-18 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | Bubble defect treatment method for wafer bonding process |
| CN112071802A (en) * | 2020-08-31 | 2020-12-11 | 上海华力集成电路制造有限公司 | Method and device for preventing void defects in wafer bonding process |
| CN115070515A (en) * | 2022-06-20 | 2022-09-20 | 长春长光圆辰微电子技术有限公司 | Method for reducing CMP large area edge peeling in GOI production |
| CN116072533A (en) * | 2023-03-28 | 2023-05-05 | 成都功成半导体有限公司 | Wafer and wafer thinning process thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112173A (en) * | 1992-09-28 | 1994-04-22 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor silicon epitaxial substrate |
| US20040126993A1 (en) * | 2002-12-30 | 2004-07-01 | Chan Kevin K. | Low temperature fusion bonding with high surface energy using a wet chemical treatment |
| CN101047144A (en) * | 2006-03-31 | 2007-10-03 | 硅绝缘体技术有限公司 | Method for fabricating a compound-material and method for choosing a wafer |
| KR20080002485A (en) * | 2006-06-30 | 2008-01-04 | 주식회사 하이닉스반도체 | Mehtod for manufacturing bonded soi wafer |
| CN101331585A (en) * | 2005-12-16 | 2008-12-24 | 信越半导体株式会社 | Method for manufacturing bonded substrate |
-
2014
- 2014-02-28 CN CN201410072295.3A patent/CN103871870B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112173A (en) * | 1992-09-28 | 1994-04-22 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor silicon epitaxial substrate |
| US20040126993A1 (en) * | 2002-12-30 | 2004-07-01 | Chan Kevin K. | Low temperature fusion bonding with high surface energy using a wet chemical treatment |
| CN101331585A (en) * | 2005-12-16 | 2008-12-24 | 信越半导体株式会社 | Method for manufacturing bonded substrate |
| CN101047144A (en) * | 2006-03-31 | 2007-10-03 | 硅绝缘体技术有限公司 | Method for fabricating a compound-material and method for choosing a wafer |
| KR20080002485A (en) * | 2006-06-30 | 2008-01-04 | 주식회사 하이닉스반도체 | Mehtod for manufacturing bonded soi wafer |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105140143B (en) * | 2015-07-30 | 2019-01-22 | 武汉新芯集成电路制造有限公司 | A kind of wafer bonding technique |
| CN105140143A (en) * | 2015-07-30 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Wafer bonding process |
| CN105826182A (en) * | 2016-05-25 | 2016-08-03 | 上海华力微电子有限公司 | Method of optimizing wafer edge defect of CMOS image sensor |
| CN105826182B (en) * | 2016-05-25 | 2018-08-24 | 上海华力微电子有限公司 | A kind of method of optimizing CMOS imaging sensor defects of wafer edge |
| CN108461512A (en) * | 2018-02-02 | 2018-08-28 | 豪威科技(上海)有限公司 | wafer bonding structure and wafer bonding method |
| CN108899268B (en) * | 2018-06-28 | 2021-04-06 | 武汉新芯集成电路制造有限公司 | Pretreatment method for improving bubble performance of wafer bonding process |
| CN108899268A (en) * | 2018-06-28 | 2018-11-27 | 武汉新芯集成电路制造有限公司 | A kind of preprocess method improving the performance of wafer bonding technique bubble |
| CN110459555A (en) * | 2019-08-29 | 2019-11-15 | 长春长光圆辰微电子技术有限公司 | Manufacturing process method of the back side illumination image sensor crystal round fringes without silicon fiml defect |
| CN110571163A (en) * | 2019-09-18 | 2019-12-13 | 武汉新芯集成电路制造有限公司 | Bubble defect treatment method for wafer bonding process |
| CN112071802A (en) * | 2020-08-31 | 2020-12-11 | 上海华力集成电路制造有限公司 | Method and device for preventing void defects in wafer bonding process |
| CN112071802B (en) * | 2020-08-31 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method and device for preventing void defect in wafer bonding process |
| CN115070515A (en) * | 2022-06-20 | 2022-09-20 | 长春长光圆辰微电子技术有限公司 | Method for reducing CMP large area edge peeling in GOI production |
| CN116072533A (en) * | 2023-03-28 | 2023-05-05 | 成都功成半导体有限公司 | Wafer and wafer thinning process thereof |
| CN116072533B (en) * | 2023-03-28 | 2023-06-13 | 成都功成半导体有限公司 | Wafer and wafer thinning process thereof |
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|---|---|
| CN103871870B (en) | 2016-05-25 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |