JPH08167584A - Manufacture of epitaxial wafer - Google Patents
Manufacture of epitaxial waferInfo
- Publication number
- JPH08167584A JPH08167584A JP6331749A JP33174994A JPH08167584A JP H08167584 A JPH08167584 A JP H08167584A JP 6331749 A JP6331749 A JP 6331749A JP 33174994 A JP33174994 A JP 33174994A JP H08167584 A JPH08167584 A JP H08167584A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- epitaxial
- epitaxial wafer
- epitaxial layer
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Mechanical Treatment Of Semiconductor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、発光素子製造用のエピ
タキシャルウェーハの製造方法に関する。さらに詳しく
は、半導体基板上にエピタキシャル層を成長したエピタ
キシャルウェーハの表面を平坦化する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an epitaxial wafer for manufacturing a light emitting device. More specifically, it relates to a method for flattening the surface of an epitaxial wafer having an epitaxial layer grown on a semiconductor substrate.
【0002】[0002]
【発明の背景技術】発光ダイオード等の発光素子は、通
常、化合物半導体からなる基板(ウェーハ)上に、複数
のエピタキシャル層を成長し、これを素子化することに
よって製造される。BACKGROUND OF THE INVENTION A light emitting device such as a light emitting diode is usually manufactured by growing a plurality of epitaxial layers on a substrate (wafer) made of a compound semiconductor and converting the epitaxial layers into devices.
【0003】一般にエピタキシャルウェーハ(エピタキ
シャル層)の表面は平坦ではなく、特に液相エピタキシ
ャル成長法で成長した場合はウェーハの外周部が厚くな
り、ウェーハ面内の厚さバラツキも大きく、そのままで
は使用し難い。また、ウェーハの外周部には面欠陥が発
生し易い。そこで、従来よりエピタキシャルウェーハの
表面を、シリカ粒子等の砥粒を含んだ研磨液(コロイダ
ルシリカ)を用いた表面ポリッシュを施して、平坦化且
つ面欠陥の除去をしていた。Generally, the surface of an epitaxial wafer (epitaxial layer) is not flat, and especially when it is grown by a liquid phase epitaxial growth method, the outer peripheral portion of the wafer becomes thick, and the thickness variation in the wafer surface is large, and it is difficult to use as it is. . Further, surface defects are likely to occur on the outer peripheral portion of the wafer. Therefore, conventionally, the surface of an epitaxial wafer has been subjected to surface polishing using a polishing liquid (colloidal silica) containing abrasive grains such as silica particles to planarize and remove surface defects.
【0004】[0004]
【発明が解決しようとする課題】しかし、従来の研磨液
を用いた表面ポリッシュのようなメカノケミカル的な研
磨では、ウェーハの外周部の面欠陥の除去を十分に行う
ことができなかった。これは、例えば酸素ドープGaP
エピタキシャル層の場合、ウェーハ外周部にはGa2O3
析出物が発生して欠陥を形成するが、これを除去するに
は30μm以上も研磨しなければならないが、あまり研
磨し過ぎるとウェーハ中央部の比較的薄い領域が必要以
上に研磨されてしまうためである。However, in the mechanochemical polishing such as the surface polishing using the conventional polishing liquid, the surface defects on the outer peripheral portion of the wafer cannot be sufficiently removed. This is, for example, oxygen-doped GaP
In the case of an epitaxial layer, Ga 2 O 3 is formed around the wafer.
Precipitates are generated to form defects, but in order to remove them, it is necessary to polish by 30 μm or more, but if they are polished too much, a relatively thin region in the center of the wafer will be polished more than necessary. Is.
【0005】従って、表面ポリッシュでは除去できない
ウェーハ外周部の面欠陥は、欠陥の部分だけ部分的にウ
ェーハを切断するか、あるいはウェーハ外周部から一定
幅で切断(面取り)して除去していた。しかし、この方
法では除去される部分が多く、歩留まり低下の原因とな
っていた。Therefore, the surface defects on the outer peripheral portion of the wafer which cannot be removed by the surface polishing are removed by partially cutting the wafer only at the defective portion or by cutting (chamfering) the outer peripheral portion with a constant width. However, in this method, many portions are removed, which causes a decrease in yield.
【0006】本発明は、エピタキシャルウェーハの外周
部に発生する面欠陥を効率的に除去し、ウェーハ面内の
厚さのバラツキを低減する方法を提供することを目的と
する。It is an object of the present invention to provide a method for efficiently removing surface defects generated in the outer peripheral portion of an epitaxial wafer and reducing variations in thickness within the wafer surface.
【0007】[0007]
【課題を達成するための手段】本発明は、半導体基板上
にエピタキシャル層を成長した後、該エピタキシャル層
の表面を研削加工して平坦化する工程を含むようにし
た。The present invention includes a step of growing an epitaxial layer on a semiconductor substrate and then grinding and flattening the surface of the epitaxial layer.
【0008】前記エピタキシャル層は、例えば液相エピ
タキシャル成長法により形成する。The epitaxial layer is formed by, for example, a liquid phase epitaxial growth method.
【0009】前記半導体基板及び前記エピタキシャル層
は、例えばIII−V族化合物半導体からなり、さらに
具体的には例えばGaP、GaAs及びGaAlAsか
ら選択されるいずれかの化合物半導体からなる。The semiconductor substrate and the epitaxial layer are made of, for example, a III-V group compound semiconductor, and more specifically, a compound semiconductor selected from, for example, GaP, GaAs, and GaAlAs.
【0010】前記研削加工は、エピタキシャルウェーハ
面内の最大厚さと最小厚さとの差で定義される厚さバラ
ツキが5μm以下であることが望ましい。In the grinding process, it is desirable that the thickness variation defined by the difference between the maximum thickness and the minimum thickness in the plane of the epitaxial wafer is 5 μm or less.
【0011】[0011]
【作用】エピタキシャルウェーハ(エピタキシャル層)
の表面を平面研削装置等により平面状に研削加工するこ
とにより、ウェーハ表面を機械的且つ高精度に平坦化す
る。この場合、ウェーハの凹状に湾曲突出した外周部は
深く研削されるが、ウェーハ中央部の比較的薄い領域は
浅く研削される。従って、中央部が必要以上に研削され
ることなく外周部の厚く且つ面欠陥の多い領域を効率良
く除去することができ、且つウェーハ面内の厚さのバラ
ツキを低減することができる。[Function] Epitaxial wafer (epitaxial layer)
The surface of the wafer is flattened mechanically and highly accurately by grinding the surface of the wafer into a planar shape by a surface grinding device or the like. In this case, the outer peripheral portion of the wafer which is curved and protrudes in a concave shape is deeply ground, while the relatively thin region in the central portion of the wafer is shallowly ground. Therefore, it is possible to efficiently remove the thick peripheral region with many surface defects without grinding the central portion more than necessary, and reduce the variation in the thickness within the wafer surface.
【0012】[0012]
【実施例】次に、本発明の実施例を詳細に説明する。EXAMPLES Next, examples of the present invention will be described in detail.
【0013】図1は、本発明の方法の概念図である。す
なわち、図1(a)に示すように、半導体基板2上に液
相エピタキシャル成長法によりエピタキシャル層3を成
長した直後のエピタキシャルウェーハ1は、表面が凹状
に湾曲している。この湾曲面を、図1(b)に示すよう
に、平面研削盤を用いて高精度に平面状に研削加工す
る。以下、実施例及び比較例のエピタキシャルウェーハ
についてその評価結果を具体的に説明する。FIG. 1 is a conceptual diagram of the method of the present invention. That is, as shown in FIG. 1A, the surface of the epitaxial wafer 1 immediately after the epitaxial layer 3 is grown on the semiconductor substrate 2 by the liquid phase epitaxial growth method is concavely curved. As shown in FIG. 1B, this curved surface is highly precisely ground into a flat surface by using a surface grinder. Hereinafter, the evaluation results of the epitaxial wafers of Examples and Comparative Examples will be specifically described.
【0014】(実施例)約48mmφのn型GaP単結
晶基板11上にn型GaPエピタキシャル層12及びZ
n−Oドープp型GaPエピタキシャル層13を液相エ
ピタキシャル成長法により順次成長して、図2(a)に
示すような厚さ分布の赤色発光素子用GaPエピタキシ
ャルウェーハ10を得た。(Example) An n-type GaP epitaxial layer 12 and Z were formed on an n-type GaP single crystal substrate 11 having a diameter of about 48 mm.
The n-O-doped p-type GaP epitaxial layer 13 was sequentially grown by a liquid phase epitaxial growth method to obtain a GaP epitaxial wafer 10 for a red light emitting device having a thickness distribution as shown in FIG. 2 (a).
【0015】このエピタキシャルウェーハ10につい
て、平面研削盤として芝山機械(株)製の全自動グライ
ンディングマシンSVG−201を用い、以下の研削条
件で研削加工を行い、図2(b)に示すエピタキシャル
ウェーハ20(目標厚さ295μm)を得た。 研削ホイール:レジンボンド#2000タイプF テーブル回転数:100rpm スピンドル回転数:2400rpm 砥石送り速度:20〜30μm/minThis epitaxial wafer 10 was ground under the following grinding conditions using a fully automatic grinding machine SVG-201 manufactured by Shibayama Kikai Co., Ltd. as a surface grinder, and the epitaxial wafer shown in FIG. 20 (target thickness 295 μm) was obtained. Grinding wheel: Resin bond # 2000 type F Table rotation speed: 100 rpm Spindle rotation speed: 2400 rpm Grinding wheel feed speed: 20 to 30 μm / min
【0016】上記研削加工処理を施したエピタキシャル
ウェーハ20(サンプル枚数:500)の厚さのバラツ
キを評価し、その結果を表1に示す。具体的には、ウェ
ーハ面内9点(外周から3mmの点を4点、外周から半
径r/2の点を4点及び中心1点)で厚さを測定し、最
大厚さと最小厚さとの差をバラツキR(μm)とした。
なお、下線付きの数字はその数を含むことを表し、下線
のない数字はその数を含まないことを表す。The variation in thickness of the epitaxial wafer 20 (the number of samples: 500) which has been subjected to the above-mentioned grinding processing was evaluated, and the results are shown in Table 1. Specifically, the thickness is measured at 9 points on the wafer surface (4 points at 3 mm from the outer circumference, 4 points at the radius r / 2 from the outer circumference and 1 point at the center), and the maximum thickness and the minimum thickness are measured. The difference was defined as the variation R (μm).
It should be noted that a number with an underline indicates that the number is included, and a number without an underline indicates that the number is not included.
【0017】次に、上記エピタキシャルウェーハ20を
発光ダイオードに素子化し、VF値(順方向動作電流、
例えば10mAを流すのに必要な印加電圧)及び輝度を
測定した。すなわち、図3(a)に示すように、研削加
工処理を施したエピタキシャルウェーハ20を、各個別
素子に対応するp側電極14(100μmφ、350μ
mピッチ)及びn側電極15(50μmφ、100μm
ピッチ)を形成し、個別素子ごとにハーフダイシングし
て分離溝17を形成し、ウェーハ1枚当たり約1400
0個のメサ型発光ダイオード16(300μm×300
μm)に加工した(図3(b))後、ダイシング歪除去
エッチング(塩酸、80℃、15分)を行った。Next, the epitaxial wafer 20 is formed into a light emitting diode, and a V F value (forward operation current,
For example, the applied voltage required to pass 10 mA) and the brightness were measured. That is, as shown in FIG. 3A, the epitaxial wafer 20 that has been subjected to the grinding process is processed into the p-side electrode 14 (100 μmφ, 350 μm) corresponding to each individual element.
m pitch) and n-side electrode 15 (50 μmφ, 100 μm
Pitch), and half dicing is performed for each individual element to form the separation groove 17, and about 1400 per wafer is formed.
0 mesa type light emitting diodes 16 (300 μm × 300
(FIG. 3 (b)), and then dicing strain removing etching (hydrochloric acid, 80 ° C., 15 minutes) was performed.
【0018】このようにして得られたメサ型発光ダイオ
ード16のVF値及び輝度を、縦及び横についてそれぞ
れ4個ごとに1個の頻度で測定し、ウェーハ全面のマッ
ピングを行った。図4及び図5は、それぞれサンプルの
VF値及び輝度の頻度分布を示す。The V F value and the luminance of the thus obtained mesa type light emitting diode 16 were measured at a frequency of one every four in the vertical and horizontal directions, and the entire surface of the wafer was mapped. 4 and 5 show the frequency distribution of the V F value and the luminance of the sample, respectively.
【0019】[0019]
【表1】 [Table 1]
【0020】(比較例)実施例で用いたのと同種のエピ
タキシャルウェーハ10についてコロイダルシリカを含
む研磨液を用いて実施例と同じ目標厚さで研磨加工し
た。この処理を施したエピタキシャルウェーハ20(サ
ンプル枚数:500)の厚さのバラツキを評価し、その
結果を実施例と併せて表1に示す。また、このエピタキ
シャルウェーハ20を実施例と同様に発光ダイオードに
素子化し、VF値及び輝度を測定した。その結果を図4
及び図5に実施例と併せて示す。(Comparative Example) The same type of epitaxial wafer 10 as that used in the example was polished to the same target thickness as that of the example using a polishing liquid containing colloidal silica. The variation in the thickness of the epitaxial wafer 20 (the number of samples: 500) subjected to this treatment was evaluated, and the results are shown in Table 1 together with the examples. Further, this epitaxial wafer 20 was formed into a light emitting diode as in the example, and the V F value and the brightness were measured. The result is shown in Figure 4.
5 and FIG. 5 together with the examples.
【0021】(厚さのバラツキの評価結果)表1から分
かるように、比較例のポリッシュ加工による厚さバラツ
キRは、10〜15μmが46.8%と最も多く、平均
値が12.6μmと比較的大きいのに対し、実施例の研
削加工による厚さバラツキRは、0〜5μmに100%
集中し、平均値も2.5μmと極めて小さく、均一な厚
さのウェーハが得られることが確認できた。また、工程
歩留は、比較例が77.8%であったのに対し、実施例
では93.4%とこれも良好な結果が得られた。(Evaluation result of thickness variation) As can be seen from Table 1, the thickness variation R by polishing in the comparative example is 10 to 15 μm, which is the largest at 46.8%, and the average value is 12.6 μm. In comparison with the comparatively large value, the thickness variation R due to the grinding process of the example is 100% in 0 to 5 μm.
It was confirmed that the wafers were concentrated and the average value was 2.5 μm, which was extremely small, and a wafer having a uniform thickness was obtained. Further, the process yield was 77.8% in the comparative example, whereas it was 93.4% in the example, which was also a good result.
【0022】(素子特性の評価結果)各図から分かるよ
うに、実施例の方法によれば、VF値及び輝度ともに比
較例と比べてバラツキが極めて小さく、良好な結果が得
られた。その他、波長特性、外観検査ともに実施例の場
合、問題ないレベルであった。(Evaluation result of device characteristics) As can be seen from the respective drawings, according to the method of the embodiment, both the V F value and the luminance are extremely smaller than those of the comparative example, and good results are obtained. In addition, in the case of the example, both the wavelength characteristics and the appearance inspection were at a level without problems.
【0023】[0023]
【発明の効果】以上説明したように本発明によれば、エ
ピタキシャルウェーハの凹状に湾曲突出した外周部に多
く発生する面欠陥を効率良く除去することができ、歩留
りの向上に寄与するとともに、エピタキシャルウェーハ
の定形化が可能になる。また、ウェーハ表面を精度良く
平坦化することができるので、厚さのバラツキが少ない
ウェーハを供給することができる。したがって、エピタ
キシャルウェーハの表面検査や厚さ測定の簡略化を図る
ことができる。As described above, according to the present invention, it is possible to efficiently remove the surface defects that often occur in the outer peripheral portion of the epitaxial wafer that is curved and convex in a concave shape, which contributes to the improvement of the yield and to the epitaxial growth. Enables standardization of wafers. Further, since the wafer surface can be accurately flattened, it is possible to supply a wafer having a small variation in thickness. Therefore, the surface inspection and thickness measurement of the epitaxial wafer can be simplified.
【0024】また、エピタキシャルウェーハを使用する
面からは、歩留り及び生産性の向上あるいは製品の均一
性が得られる利点がある。具体的には、ウェーハ表面が
精度よく平坦化されているため、所定の形状、サイズで
電極形成することができる。また、ウェーハ表面の面欠
陥が効率よく除去されているため、面欠陥起因の特性不
良素子を減少することができる。さらに、エピタキシャ
ルウェーハの厚さが均一に制御されているため、素子特
性の均一化が図れるとともに、チップの厚さ(高さ)が
均一となり、組立工程の際の工程トラブルを減少するこ
とができる。From the aspect of using an epitaxial wafer, there is an advantage that yield and productivity can be improved or product uniformity can be obtained. Specifically, since the wafer surface is accurately flattened, electrodes can be formed in a predetermined shape and size. Further, since the surface defects on the wafer surface are efficiently removed, the number of defective elements due to the surface defects can be reduced. Further, since the thickness of the epitaxial wafer is controlled uniformly, the device characteristics can be made uniform, and the chip thickness (height) becomes uniform, which can reduce process troubles during the assembly process. .
【図1】本発明の方法によるエピタキシャルウェーハの
表面加工方法を示す説明図である。FIG. 1 is an explanatory diagram showing a method of processing a surface of an epitaxial wafer according to the method of the present invention.
【図2】本発明の実施例の方法によるエピタキシャルウ
ェーハの表面加工方法を示す説明図である。FIG. 2 is an explanatory view showing a surface processing method of an epitaxial wafer according to the method of the embodiment of the present invention.
【図3】赤色発光素子用GaPエピタキシャルウェーハ
からメサ型発光ダイオードに加工する方法を示す説明図
である。FIG. 3 is an explanatory diagram showing a method of processing a GaP epitaxial wafer for a red light emitting device into a mesa type light emitting diode.
【図4】実施例及び比較例で得られたメサ型発光ダイオ
ードのVF値分布を示すグラフである。FIG. 4 is a graph showing V F value distributions of the mesa type light emitting diodes obtained in Examples and Comparative Examples.
【図5】実施例及び比較例で得られたメサ型発光ダイオ
ードの相対輝度分布を示すグラフである。FIG. 5 is a graph showing a relative luminance distribution of the mesa type light emitting diodes obtained in Examples and Comparative Examples.
1,10 20 エピタキシャルウェーハ 2 半導体基板 3 エピタキシャル層 11 n型GaP単結晶基板 12 n型GaPエピタキシャル層 13 Zn−Oドープp型GaPエピタキシャル層 14 p側電極 15 n側電極 16 メサ型発光ダイオード 17 分離溝 1, 10 20 Epitaxial wafer 2 Semiconductor substrate 3 Epitaxial layer 11 n-type GaP single crystal substrate 12 n-type GaP epitaxial layer 13 Zn-O-doped p-type GaP epitaxial layer 14 p-side electrode 15 n-side electrode 16 Mesa-type light-emitting diode 17 Separation groove
Claims (5)
した後、該エピタキシャル層の表面を研削加工して平坦
化する工程を含むことを特徴とするエピタキシャルウェ
ーハの製造方法。1. A method for manufacturing an epitaxial wafer, which comprises a step of growing an epitaxial layer on a semiconductor substrate and then grinding and flattening the surface of the epitaxial layer.
エピタキシャル成長法であることを特徴とする請求項1
に記載のエピタキシャルウェーハの製造方法。2. The method of forming the epitaxial layer is a liquid phase epitaxial growth method.
A method for manufacturing an epitaxial wafer according to item 1.
層がIII−V族化合物半導体からなることを特徴とす
る請求項1又は請求項2に記載のエピタキシャルウェー
ハの製造方法。3. The method for producing an epitaxial wafer according to claim 1, wherein the semiconductor substrate and the epitaxial layer are made of a III-V group compound semiconductor.
P、GaAs及びGaAlAsから選択されるいずれか
であることを特徴とする請求項3に記載のエピタキシャ
ルウェーハの製造方法。4. The group III-V compound semiconductor is Ga.
The epitaxial wafer manufacturing method according to claim 3, wherein the epitaxial wafer is selected from P, GaAs, and GaAlAs.
ハ面内の最大厚さと最小厚さとの差で定義される厚さバ
ラツキが5μm以下であることを特徴とする請求項1又
は請求項2に記載のエピタキシャルウェーハの製造方
法。5. The thickness variation defined by the difference between the maximum thickness and the minimum thickness within the epitaxial wafer surface in the grinding process is 5 μm or less, and the grinding process according to claim 1 or 2. Method of manufacturing epitaxial wafer.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6331749A JPH08167584A (en) | 1994-12-09 | 1994-12-09 | Manufacture of epitaxial wafer |
TW84105073A TW318948B (en) | 1994-12-09 | 1995-05-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6331749A JPH08167584A (en) | 1994-12-09 | 1994-12-09 | Manufacture of epitaxial wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08167584A true JPH08167584A (en) | 1996-06-25 |
Family
ID=18247191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6331749A Pending JPH08167584A (en) | 1994-12-09 | 1994-12-09 | Manufacture of epitaxial wafer |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH08167584A (en) |
TW (1) | TW318948B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114450584A (en) * | 2019-09-20 | 2022-05-06 | 芝浦机械株式会社 | Stack molding system |
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JPH0467626A (en) * | 1990-07-09 | 1992-03-03 | Mitsubishi Materials Corp | Silicon wafer |
JPH04122023A (en) * | 1990-09-13 | 1992-04-22 | Hitachi Ltd | Manufacture of semiconductor wafer and manufacture semiconductor integrated circuit device |
JPH0567598A (en) * | 1991-07-11 | 1993-03-19 | Fujitsu Ltd | Manufacture of semiconductor substrate |
JPH05315305A (en) * | 1992-05-06 | 1993-11-26 | Mitsubishi Materials Shilicon Corp | Wafer polishing method |
-
1994
- 1994-12-09 JP JP6331749A patent/JPH08167584A/en active Pending
-
1995
- 1995-05-19 TW TW84105073A patent/TW318948B/zh active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61101496A (en) * | 1984-10-24 | 1986-05-20 | Shizuoka Univ | Crystal growth process |
JPS62181869A (en) * | 1986-01-31 | 1987-08-10 | Sumitomo Electric Ind Ltd | Polishing of semiconductor wafer |
JPH0467626A (en) * | 1990-07-09 | 1992-03-03 | Mitsubishi Materials Corp | Silicon wafer |
JPH04122023A (en) * | 1990-09-13 | 1992-04-22 | Hitachi Ltd | Manufacture of semiconductor wafer and manufacture semiconductor integrated circuit device |
JPH0567598A (en) * | 1991-07-11 | 1993-03-19 | Fujitsu Ltd | Manufacture of semiconductor substrate |
JPH05315305A (en) * | 1992-05-06 | 1993-11-26 | Mitsubishi Materials Shilicon Corp | Wafer polishing method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114450584A (en) * | 2019-09-20 | 2022-05-06 | 芝浦机械株式会社 | Stack molding system |
Also Published As
Publication number | Publication date |
---|---|
TW318948B (en) | 1997-11-01 |
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