JPH0346353A - Formation of wiring - Google Patents

Abstract

PURPOSE:To prevent a defect, of an element, caused by a cavity by a method wherein a substratum metal film is formed of a plated film only inside a via hole and a plated film is then formed on the rear surface of a substrate. CONSTITUTION:An Au/Ti film 13 as a substratum metal film whose bonding property with reference to Au is good is formed on the whole rear surface of a substrate 11 including a via hole 12; and a photoresist film 14 is left only inside the via hole 12. After that, also the Au/Ti film 13 on a sidewall near an opening of the via hole 13 is removed simultaneously by, e.g. an ion milling operation and, in addition, by implanting ions obliquely. An electric current is applied to a source pad 4 and to the Au/Ti film 13; an Au film 15 is precipitated inside the via hole 12 by an electrolytic plating method. When the Au film 15 is formed in advance only inside the via hole by the electrolytic plating method in this manner, the via hole can be filled completely with the Au film 15. Thereby, a cavity is not produced inside the via hole and a defect is not produced in a heat treatment during a post process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming plated wiring in a via hole penetrating a semiconductor substrate.

[Conventional technology]

High power GaAsFET, especially at frequency X-.

The FET used in the band has a source inductance L8. which is a parasitic element. In order to effectively reduce the source resistance R8, a via hole/PH3 structure is adopted to increase the gain and output of the element. Among these, the via hole structure is used to ground the source by drilling a hole from the back side of the GaAs substrate in line with the source electrode, because it can shorten the wiring distance between the source electrode and the earth ground, and provide a large ground area.

Effective in reducing

High-output FETs require large DC input power to be applied to obtain high output, and since the efficiency of the device is less than 50%, an increase in thermal resistance Rth increases the channel temperature of the device and reduces electron mobility. This results in an increase in Rs and a decrease in transfer conductance gm.

The PH3 structure is effective in this low Rth range, and the GaAs substrate thickness is reduced to about 25 to 50 μm, and the Au is reduced to 30 to 50 μm.
Heat dissipation is improved by arranging it in a plate shape with a thickness of μm.

Conventionally, wet etching has been used to process bias holes, but due to its isotropic etching characteristics, the width of the source electrode must be made larger than necessary, and the width of the chip also increases accordingly. Therefore, as the frequency becomes higher, the periodic operation with respect to the human input signal becomes worse, resulting in an increase in circuit matching loss. For this reason, a method has recently been developed to narrow the source electrode width by vertically processing the via hole using dry etching, and is now being put into practical use.

Via hole processed by this dry etching / PH3
Different structures of high-power GaAsFETs are shown in partially cutaway perspective views in FIGS. 3 and 4. Figure 3 shows GaA
A via hole 12 is formed directly under the source pad 4 formed on the s-substrate 11, and an Au film 17A is formed on the back surface of the substrate 11 including the via hole 12 to electrically connect to the source pad 4. . In addition, in order to reduce the noise in FIG. 4 even more than in FIG. 3, a via hole 12 is formed directly under each source electrode 5.
An Au film 17A is formed on the back surface of the substrate including the substrate.

This manufacturing process is shown in FIG. After forming the FET element on the surface of the GaAs substrate 11, as shown in FIG. 5(a), a via hole 12 is processed and penetrated from the back surface of the GaAs substrate 11 by chlorine gas RIE in alignment with the source pad 4. In this case, the thickness of the GaAs substrate 11 is 30 μm.
, the opening width of the via hole 12 is 20 um.

Next, as shown in FIG. 5(b), the A u /Ti film 1
3 was grown to a thickness of 2000 by sputtering. Then, as shown in FIG. 5(C), this A u / T
Using the i-film 13 as a plating current path, the Au film 17 is formed on the back surface of the substrate 11 and inside the via hole 12 by a normal electrolytic plating method.
A is coated with a thickness of 35 μm.

[Problem to be solved by the invention]

The conventional via hole wiring formation method described above is shown in FIG.
As shown in C), the Au film 17 formed by electrolytic plating
A is not completely filled into the via hole 12, and a cavity X is created. This is because, as shown in FIG. 6, which shows the deposition process of the Au film 17A, the replacement efficiency of the plating bath in the via hole 12 is poor, and metal ions (A u ) near the bottom and sidewalls are depleted, resulting in the Au electrodeposition reaction. This is due to the interaction between the decrease in the field and the concentration of the electric field at the edge of the opening of the via hole 12, which increases the current density, and the deposition rate of Au becomes the fastest, eventually closing the hole opening.

Because the reaction gas and plating solution during plating remain in this cavity
There is a problem in that the source electrode is lifted up, causing swelling and tearing, resulting in device failure.

An object of the present invention is to provide a method for forming wiring that eliminates such problems.

[Means to solve the problem]

The wiring forming method of the present invention includes a step of forming a plating current path continuous to an electrode formed on the surface of a semiconductor substrate, a step of opening a via hole penetrating the semiconductor substrate on the back side of the electrode, and a step of forming a via hole that penetrates the semiconductor substrate on the back side of the electrode. A step of forming a thin base metal film on the back surface of the semiconductor substrate including the hole, and a step of coating and forming a resin film on the back surface of the semiconductor substrate and selectively removing it to leave the resin film only in the via hole. and a step of etching the thin base metal film using this resin film as a mask, leaving the base metal film only in the via hole, and supplying current to the base metal film through the plating current path and electrode to remove the base metal film inside the via hole. The method includes a step of forming a plating film only on the surface of the semiconductor substrate, and a step of forming a plating film connected to the plating film on the back surface of the semiconductor substrate.

(Function) In this manufacturing method, a plating film is first formed only in the via hole using a base metal film, and then a plating film is formed on the back side of the substrate, so the via hole opening is formed by the plating film. Blockage can be avoided and cavities can be prevented from forming within the via hole.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a high-power GaAs FET chip 1 according to an embodiment of the present invention, in which 2 is a gate pad connected to a gate electrode 3, 4 is a source pad integrated with a source electrode 5,
6 is a drain pad integrated with the drain electrode 7. Further, in a part of the chip separation line 8 provided around the chip 1, a plating current path 9 necessary for wiring formation is formed.

This plating current path 9 is connected to the final metal A u / P t / T constituting the gate, source, and drain pads.
It is formed at the same time as forming FET chip 1, and is electrically connected to the source pad 4 of each FET chip 1.

A via hole is opened in the substrate on the back side of the source pad 4 or the source electrode 5, and a plated wiring electrically connected to the source pad 4 is formed.

The subsequent steps are shown in FIGS. 2(a) to (h).

First, as shown in FIG. 2(a), an FET is formed on the front surface of a GaAs substrate 11, and then the back surface is polished and etched by wet etching to finish the thickness of the GaAs substrate 11 to 30 μm. Here, a via hole I is formed by RIE using chlorine gas from the back side in line with the source pad 4.
form 2. The Ti of the source pad 4 is exposed through the via hole. Note that when a via hole is opened in the source electrode 5, the AuGe-GaAs alloy is exposed.

Next, as shown in FIG. 2(b), an Au/Ti film 13 with a thickness of 250 mm is coated on the entire back surface of the substrate 11 including the via hole 12 by sputtering as a base metal film with good adhesion to Au.
Form to a thickness of 0 people.

Next, as shown in FIG. 2(C), the photoresist film 14 is overcoated on the back surface of the substrate 11 in 2.3 times, so that the thickness of the photoresist film 14 in the via hole 12 is 5 to 10 mm.
Make it so that it is μm. Although the photoresist film 14 is not sufficiently coated at the opening of the via hole 12, this is not a problem.

Next, as shown in FIG. 2(d), the photoresist film 14 is
selectively expose and develop the via hole 12.
The photoresist film 14 is left only inside. Thereafter, as shown in FIG. 2(e), the substrate 11 is removed by, for example, ion milling.
The A u/Ti film 13 on the back surface of the via hole 12 is removed, and the A u/Ti film 13 on the side wall near the opening of the via hole 12 is also removed at the same time by making the ion incidence oblique.

Next, as shown in FIG. 2(f), the photoresist 14 in the via hole 12 is removed using O2 plasma and an organic solvent. Thereafter, as shown in FIG. 2(g), using the plating current path 9 shown in FIG.
Electricity is applied to the Ti film 13, and an Au film 15 is deposited in the via hole 12 by electrolytic plating. Furthermore, after the via hole 12 is filled with the Au film 15, as shown in FIG.
/TiwA 16 is formed to a thickness of 2500 mm, and using this as a plating pass, an Au film 17 is plated to a thickness of 35 μm.

In this method, the via hole can be completely filled with the Au film 15 by first forming the Au film 15 only in the via hole by electrolytic plating. Therefore, no cavities are formed in the via hole 12, and the source electrode is not lifted up, bulged, or bulged during heat treatment in the subsequent process.
No problems such as tearing will occur.

〔Effect of the invention〕

As explained above, the present invention selectively forms a base metal film only within the via hole, forms a plating film using this base metal film only within the via hole, and then forms a plating film on the back surface of the substrate. Because of this, it is possible to avoid the via hole opening from being blocked by the plating film and prevent the formation of cavities within the via holes, making it possible to prevent element failures caused by these cavities. effective.

[Brief explanation of drawings]

Fig. 1 is a plan view of an FET according to an embodiment of the present invention, Figs. 2 (a) to (h) are sectional views showing an embodiment of the present invention in the order of steps, and Figs. 3 and 4 are different from each other. A partially cutaway perspective view of a via hole/PH3 structure, Figures 5(a) to (C) are cross-sectional views showing the conventional manufacturing method in the order of steps, and Figure 6 is a cross-sectional view for explaining defects in the conventional method. be. 1...FET chip, 2...gate pad, 3...
- Gate electrode, 4... Source pad, 5... Source electrode, 6... Drain pad, 7... Drain electrode, 8... Chip separation line, 9... Plating current path, 11. ...GaAs substrate, 12... via hole,
13... Au/Ti film, 14... Photoresist film, 15-Au film, 16... Au/Ti film, 1
7.17A・"Au film. Fig. 4 Fig. 2

Claims (1)

[Claims] 1. A step of forming a plating current path that is continuous with the electrode formed on the surface of the semiconductor substrate, a step of opening a via hole penetrating the semiconductor substrate on the back side of the electrode, and a step of forming a plating current path that is continuous with the electrode formed on the surface of the semiconductor substrate. a step of forming a thin base metal film on the back surface; a step of coating and forming a resin film on the back surface of the semiconductor substrate; and a step of selectively removing this to leave the resin film only in the via hole; Etching the thin base metal film using a mask to leave the base metal film only in the via hole, and forming a plating film only in the via hole by applying current to the base metal film through the plating current path and electrode. 1. A wiring forming method comprising the steps of: forming a plating film connected to the plating film on the back surface of a semiconductor substrate.