JPH0346259A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0346259A
JPH0346259A JP1183082A JP18308289A JPH0346259A JP H0346259 A JPH0346259 A JP H0346259A JP 1183082 A JP1183082 A JP 1183082A JP 18308289 A JP18308289 A JP 18308289A JP H0346259 A JPH0346259 A JP H0346259A
Authority
JP
Japan
Prior art keywords
seal frame
metal lid
inner edge
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1183082A
Other languages
Japanese (ja)
Other versions
JP2689621B2 (en
Inventor
Isato Usami
宇佐美 勇人
Satoshi Kikuchi
智 菊地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1183082A priority Critical patent/JP2689621B2/en
Publication of JPH0346259A publication Critical patent/JPH0346259A/en
Application granted granted Critical
Publication of JP2689621B2 publication Critical patent/JP2689621B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To enable the miniaturization of a semiconductor device by a method wherein a seal frame is seam-welded along its inner edge. CONSTITUTION:A metal lead 27 placed on a seal frame 26 whose corners are adequately rounded is welded to the seal frame 26 along the inner edge of the seal frame 26 through seam welding 28. Therefore, an electrode support arm 34 can be located inside the metal lid 27 and a seam welding electrode 32 which seam-welds the metal lid 27 to the seal frame 26 can be prevented from being located outside of the seal frame 26, so that a space between an outer lead 8 and the seal frame 26 required for the support arm 34 can be dispensed with. Therefore, an outer lead and a seal frame can be provided to the same package substrate without enlarging a device in size. By this setup, a semiconductor device of this design can be miniaturized.

Description

【発明の詳細な説明】 〔概要〕 シールフレームに蓋をシーム溶接した半導体装置の構成
に関し、 パッケージ基体の同一面にシールフレームト外リードと
を設けた半導体装置の小型化を目的とし、半導体チップ
を収容する凹所の形成されたパッケージ基体の上面には
、該凹所を囲い少なくともコーナ部に適当な丸みを有す
る金属のシールフレームが取着され、該シールフレーム
に!I!置した金属の蓋が、該シールフレームの内縁エ
ツジに沿ってシーム溶接されてなることを特徴とする特
許装置、 および、半導体チップを収容する凹所の形成されたパッ
ケージ基体の上面に形成され、該凹所の周囲を囲み、丸
みを帯びたコーナ部を有するシールフレーム上に、該凹
所を塞ぐように該シールフレームの内縁エツジに沿って
曲げ加工されてコーナ部を有する金属の蓋を載置する工
程と、該シールフレームの内側からの支持アームによっ
て支持される電極が、該金属の蓋の内縁エツジを該シー
ルフレームの内縁エツジに向けて押すと共に、該電極に
電流を流し該シールフレームの内縁エツジと該金属の蓋
とを溶接する工程と、を有することを特徴とする半導体
装置の製造方法である。
[Detailed Description of the Invention] [Summary] Regarding the structure of a semiconductor device in which a lid is seam welded to a seal frame, this invention aims to miniaturize the semiconductor device in which leads outside the seal frame are provided on the same surface of the package base. A metal seal frame that surrounds the recess and has appropriate roundness at least at the corners is attached to the upper surface of the package base in which a recess is formed to accommodate the recess. I! The patented device is characterized in that a metal lid is seam-welded along the inner edge of the seal frame, and a metal lid is formed on the upper surface of a package base in which a recess is formed for accommodating a semiconductor chip, A metal lid that is bent along the inner edge of the seal frame and has a corner portion is mounted on a seal frame that surrounds the recess and has a rounded corner portion, so as to close the recess. placing an electrode supported by a support arm from inside the seal frame to push the inner edge of the metal lid toward the inner edge of the seal frame while applying current to the electrode and pushing the inner edge of the metal lid toward the inner edge of the seal frame; A method for manufacturing a semiconductor device, comprising the step of welding an inner edge of the metal lid to the metal lid.

〔産業上の利用分野〕[Industrial application field]

本発明はパッケージ基体の凹所に半導体チップを収容し
、該凹所を囲う金属のシールフレームに金属蓋をシーム
溶接した半導体装置に関する。
The present invention relates to a semiconductor device in which a semiconductor chip is housed in a recess in a package base, and a metal lid is seam-welded to a metal seal frame surrounding the recess.

最近の半導体装置は、半導体チップのパッシベーション
技術が向上してモールドパッケージのものが多いが、高
信頼性を必要としたり特殊環境下で使用されるものにつ
いては、依然として金属やセラ逅ツク等を組み合わせて
気密封止したパッケージが使用されている。
Recent semiconductor devices have improved in semiconductor chip passivation technology and are often packaged in molds, but those that require high reliability or are used in special environments still use combinations of metals, ceramics, etc. A hermetically sealed package is used.

〔従来の技術〕[Conventional technology]

第6図は半導体チップをセラくツクパッケージに収容し
た従来の半導体装置の構成例を示す断面図である。
FIG. 6 is a sectional view showing an example of the configuration of a conventional semiconductor device in which a semiconductor chip is housed in a ceramic package.

第6図において、半導体装置1はセラミックにてなるパ
ッケージ基体2の凹所3に半導体チップ4を収容し、凹
所3を囲うように基体2の上面には金属(コバール等)
のシールフレーム6を取着し、そのシールフレーム6に
金属(コバール等)の蓋7をシーム溶接してなる。
In FIG. 6, a semiconductor device 1 houses a semiconductor chip 4 in a recess 3 of a package base 2 made of ceramic, and the top surface of the base 2 is made of metal (such as Kovar) so as to surround the recess 3.
A seal frame 6 is attached to the seal frame 6, and a lid 7 made of metal (such as Kovar) is seam welded to the seal frame 6.

パッケージ基体2は多層配線構造であり、半導体チップ
4は、ボンディングワイヤ5およびパッケージ基体2内
に形成された配線を介して、パッケージ基体2の下面よ
り導出された外リード8に接続されており、シールフレ
ーム6と金属蓋7との溶接9は、シールフレーム6の上
面と金属蓋7の外縁部との重なり部分に形成される。
The package base 2 has a multilayer wiring structure, and the semiconductor chip 4 is connected to outer leads 8 led out from the bottom surface of the package base 2 via bonding wires 5 and wiring formed within the package base 2. A weld 9 between the seal frame 6 and the metal lid 7 is formed at the overlapped portion of the upper surface of the seal frame 6 and the outer edge of the metal lid 7.

第7図は従来の前記半導体装置における金属蓋のシーム
溶接方法の説明図である。
FIG. 7 is an explanatory diagram of a conventional seam welding method for a metal lid in the semiconductor device.

第7図において、上下方向に移動可能であり適当な押圧
力で金属蓋7の外縁部をシールフレーム6に押し付ける
電極10は、支持アーム12に嵌合する軸11が回動自
在であり、例えば8ボルト、140〜180アンペア程
度の電力が加えられた状態で金属蓋7に接触し、シール
フレーム6に沿って移動する。すると、金属蓋7とシー
ルフレーム6との接触部に発生するジュール熱によって
金属蓋7の一部が溶融され、金属蓋7とシールフレーム
6は溶接9にて接合されるようになる。
In FIG. 7, the electrode 10, which is movable in the vertical direction and presses the outer edge of the metal lid 7 against the seal frame 6 with an appropriate pressing force, has a shaft 11 that fits into a support arm 12 and is rotatable, for example. It contacts the metal lid 7 and moves along the seal frame 6 while being applied with a power of about 8 volts and 140 to 180 amperes. Then, a portion of the metal lid 7 is melted by Joule heat generated at the contact portion between the metal lid 7 and the seal frame 6, and the metal lid 7 and the seal frame 6 are joined by welding 9.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上説明したように従来の半導体装置1は、金属蓋7の
外縁部がシールフレーム6に溶接された構成であり、ジ
ュール熱を集中的に発生させる電極10はテーパ状であ
り、金属蓋7の外縁端に接触す電極10を支持するアー
ム12は、シールフレー・ムロより外側を移動するよう
になる。
As explained above, the conventional semiconductor device 1 has a structure in which the outer edge of the metal lid 7 is welded to the seal frame 6, and the electrode 10 that intensively generates Joule heat is tapered. The arm 12 supporting the electrode 10 in contact with the outer edge moves outside of the seal frame.

しかながら、半導体装置1の半導体チップ4に冷却フィ
ンを設けようとすると、その冷却フィンはパッケージ基
体2の下面に取着することになり、外リード8は冷却フ
ィンの邪魔にならないように基体2の上面より導出させ
ることになる。
However, if cooling fins are to be provided on the semiconductor chip 4 of the semiconductor device 1, the cooling fins will be attached to the lower surface of the package base 2, and the outer leads 8 will be attached to the base 2 so as not to get in the way of the cooling fins. It will be derived from the top surface of .

このような冷却フィンおよび、パッケージ基体2の上面
から外リード8の導出された半導体装置は、電極10を
使用して金属蓋7を溶接しようとすると、外リード8と
シールフレーム6との間に支持アーム12のためのスペ
ースが必要になり、基体2が大形化されるという問題点
があった。
In a semiconductor device having such a cooling fin and an outer lead 8 led out from the top surface of the package base 2, when attempting to weld the metal lid 7 using the electrode 10, there may be a gap between the outer lead 8 and the seal frame 6. There is a problem in that a space is required for the support arm 12 and the base body 2 is increased in size.

〔課題を解決するための手段〕[Means to solve the problem]

前記問題点に鑑みてなされた本発明は、その実施例を示
す第1図によれば、半導体チップ4を収容する凹所25
の形成されたパッケージ基体22の上面には、凹所25
を囲う金属のシールフレーム26が取着され、少なくと
もコーナ部で適当な丸みを有するシールフレーム26に
載置した金属の蓋27が、シールフレーム26の内縁エ
ツジに沿うシーム溶接28によって、シールフレーム2
6に接合されたことを特徴とする半導体装置、 ならびにシーム溶接28を行う方法として、シールフレ
ーム26上に凹所25を塞ぐように金属の蓋27を載置
する工程と、シールフレーム26の内側から支持アーム
によって支持される電極にてシールフレーム26の内縁
エツジ29に金属の蓋27を溶接する工程と、を有する
ことを特徴とする半導体装置の製造方法である。
The present invention, which has been made in view of the above-mentioned problems, has a recess 25 for accommodating a semiconductor chip 4, as shown in FIG.
A recess 25 is formed on the upper surface of the package base 22.
A metal sealing frame 26 surrounding the sealing frame 26 is attached, and a metal lid 27 placed on the sealing frame 26 having appropriate roundness at least at the corners is attached to the sealing frame 2 by seam welding 28 along the inner edge of the sealing frame 26.
A method for performing seam welding 28 includes a step of placing a metal lid 27 on the seal frame 26 so as to close the recess 25, and a step of placing a metal lid 27 on the seal frame 26 to close the recess 25, and This method of manufacturing a semiconductor device is characterized by the step of welding a metal lid 27 to an inner edge 29 of a seal frame 26 using an electrode supported by a support arm.

〔作用〕[Effect]

上記手段によれば、シールフレームに金属蓋をシーム溶
接させる電極支持用アームを金属蓋の内側にすることお
よび、シーム溶接用電極はシールフレームの外側に出な
いようにすることが可能になり、外リードとシールフレ
ームとの間に支持アームのためのスペースが不必要にな
る。
According to the above means, it is possible to place the electrode support arm for seam welding the metal lid to the seal frame on the inside of the metal lid, and to prevent the seam welding electrode from protruding outside the seal frame. No space is needed for a support arm between the outer lead and the seal frame.

従って、外リードとシールフレームとは、装置を大形化
させることなくパッケージ基体の同一面に設けることが
可能となり、特に冷却用のフィンを必要とする半導体装
置に対し、金属蓋の外縁部が溶接された従来構成より小
型化できる。
Therefore, it is possible to provide the outer leads and the seal frame on the same surface of the package base without increasing the size of the device, and the outer edge of the metal lid is particularly useful for semiconductor devices that require cooling fins. It can be made smaller than the conventional welded configuration.

〔実施例〕〔Example〕

以下に、図面を用いて本発明の実施例による半導体装置
を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による半導体装置の断面図、
第2図は第1図に示すシールフレームの斜視図、第3図
は第1図に示す金属蓋の斜視図、第4図は第1図に示す
シールフレームに金属蓋をシーム溶接する方法の説明図
、第5図はシーム溶接に使用した電極の斜視図である。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
Figure 2 is a perspective view of the seal frame shown in Figure 1, Figure 3 is a perspective view of the metal lid shown in Figure 1, and Figure 4 shows a method of seam welding the metal lid to the seal frame shown in Figure 1. Explanatory drawing, FIG. 5 is a perspective view of the electrode used for seam welding.

前出図と共通部分に同一符号を使用した第1図において
、冷却フィンを取着する半導体装置21は、セラミック
にてなるパッケージ基体22の中心にあけられた透孔に
、例えばモリブデンにてなる金属ステージ23が嵌合し
、パッケージ基体22の下面および金属ステージ23の
下面には銅等にてなる金属底板24が接合され、底板2
4の下面に冷却フィン(図示せず)が取着されるように
なる。
In FIG. 1, in which the same reference numerals are used for parts common to those in the previous figure, a semiconductor device 21 to which a cooling fin is attached is made of molybdenum, for example, in a through hole drilled in the center of a package base 22 made of ceramic. The metal stage 23 is fitted, and a metal bottom plate 24 made of copper or the like is bonded to the lower surface of the package base 22 and the lower surface of the metal stage 23.
Cooling fins (not shown) are attached to the lower surface of 4.

パッケージ基体22の上面に開口する凹所25の周囲に
は、コバール等の金属にてなるシールフレーム26を取
着し、その外側に複数本の外リード8が突出し、凹所2
5の底面となるステージ23の上面には半導体チップ4
を搭載し、シールフレーム2Gにはコバール等の金属に
てなる蓋27がシーム溶接される。
A seal frame 26 made of metal such as Kovar is attached around the recess 25 that opens on the upper surface of the package base 22, and a plurality of outer leads 8 protrude from the outside of the seal frame 26.
The semiconductor chip 4 is placed on the top surface of the stage 23, which is the bottom surface of the semiconductor chip 5.
A lid 27 made of metal such as Kovar is seam-welded to the seal frame 2G.

パッケージ基体22は多層配線構造であり、半導体チッ
プ4は、ボンディングワイヤ5およびパッケージ基体2
2内に形成された配線を介して、パッケージ基体22の
上面より導出された外リード8に接続されている。
The package base 22 has a multilayer wiring structure, and the semiconductor chip 4 is connected to the bonding wires 5 and the package base 2.
It is connected to an outer lead 8 led out from the upper surface of the package base 22 via wiring formed inside the package base 22 .

シールフレーム26と金属蓋27との溶接28は、シー
ルフレーム26の上面内側コーナ部(内縁エツジ)と、
該コーナに沿う如く曲げ加工された金属蓋27のコーナ
部との接合部分に形成される。
Welding 28 between the seal frame 26 and the metal lid 27 connects the inner corner of the upper surface of the seal frame 26 (inner edge),
It is formed at the joint portion with the corner portion of the metal lid 27 which is bent along the corner.

パッケージ基体22の上面に例えば銀ろう材でろう接さ
れたシールフレーム26は、金属蓋27を溶接するため
第2図に示す如く四隅に適当な半径rの丸みを有する角
形であり、シールフレーム26の内縁エツジ29と金属
蓋27との溶接は、該丸みの中心部30間に分けて行う
ようになる。
The seal frame 26, which is soldered to the upper surface of the package base 22 with, for example, silver brazing material, has a square shape with rounded corners with an appropriate radius r, as shown in FIG. 2, in order to weld the metal lid 27. Welding between the inner edge 29 of the metal lid 27 and the metal lid 27 is performed separately between the center portions 30 of the roundness.

第3図において、シールフレーム26に嵌合する金属蓋
27は、シールフレーム26の内縁エツジ29に沿って
曲げ加工された皿形であり、シールフレーム26に金属
蓋27を溶接させる電極は、金属蓋27の内縁エツジ3
1に当接するようになる。
In FIG. 3, the metal lid 27 that fits into the seal frame 26 is dish-shaped and bent along the inner edge 29 of the seal frame 26, and the electrode for welding the metal lid 27 to the seal frame 26 is a metal lid. Inner edge 3 of lid 27
It comes into contact with 1.

第4図において、適当な押圧力で金属121の内縁エツ
ジ31を押す電極32は、支持アーム34に嵌合する軸
33が回動自在であり、例えば8ボルト、140〜18
0アンペア程度の電力が加えられた状態で内縁エツジ3
1に接触し、内縁エツジ31に沿って移動する。すると
、内縁エツジ29と31との接触部に発生するジュール
熱によって金属蓋27はシールフレーム26に溶接され
るようになるが、支持アーム34は金属M27の内側で
電極32を支持するように配設されるため、シールフレ
ーム26に近接せしめて外リード8を配置可能とする。
In FIG. 4, the electrode 32 that presses the inner edge 31 of the metal 121 with an appropriate pressing force has a shaft 33 that fits into the support arm 34 and is rotatable.
Inner edge 3 with approximately 0 ampere of power applied.
1 and moves along the inner edge 31. Then, the metal lid 27 is welded to the seal frame 26 by the Joule heat generated at the contact portion between the inner edges 29 and 31, but the support arm 34 is arranged to support the electrode 32 inside the metal M27. Therefore, the outer lead 8 can be placed close to the seal frame 26.

シールフレーム26の中心部30間を溶接する電極32
は、第5図に示すようにテーパーをα、大きい方の外径
をり、厚さをもとしたとき、コーナ丸み半径rが0.5
1であるシールフレーム26に対し、α=60度、  
D = 6 mm、厚さt=5mmのものを使用した。
Electrode 32 welding between center portions 30 of seal frame 26
As shown in Figure 5, when the taper is α, the larger outer diameter is the thickness, and the corner radius r is 0.5.
1 for the seal frame 26, α=60 degrees,
The one with D=6 mm and thickness T=5 mm was used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、シールフレームに
金属蓋をシーム溶接させる電極支持用アームが金属蓋の
内側に設けることおよび、シーム溶接用電極はシールフ
レームの外側に出ないようにすることが可能になる。
As explained above, according to the present invention, the electrode support arm for seam welding the metal lid to the seal frame is provided inside the metal lid, and the seam welding electrode is prevented from protruding outside the seal frame. becomes possible.

従って、外リードとシールフレームとは、装置を大形化
させることなくパッケージ基体の同一面に設け、特に冷
却用のフィンを必要とする半導体装置に対し、従来のも
のより小型化することができた効果を有する。
Therefore, the outer leads and seal frame can be provided on the same surface of the package base without increasing the size of the device, and can be made smaller than conventional devices, especially for semiconductor devices that require cooling fins. It has a good effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体装置、第2図は
第1図に示すシールフレーム、第3図は第1図に示す金
属蓋、 第4図は第1図に示す金属蓋の溶接方法の説明図、 第5図は溶接用電極、 第6図は従来の半導体装置、 第7図は従来の半導体装置における金属蓋の溶接方法の
説明図、 である。 図中において、 4は半導体チップ、 21は半導体装置、 22はパッケージ基体、 25は凹所、 26は金属のシールフレーム、 27は金属の蓋、 29は内縁エツジ、 31は金属蓋の内縁エツジ、 32は電極、 34は支持アーム、 を示す。 ) 木極明の一家先例し:より半{体装置 11  囚 0 ’Jg1図に示すシールフレーム 彊 回 11刷;示イを鳥l 噛3圓 溶旙喝覧急 15田 喝1田LZ、?\1&:鳥五の凶−争方瓜の梯σ月回従
来の+1体食五 %G第
1 shows a semiconductor device according to an embodiment of the present invention, FIG. 2 shows a seal frame shown in FIG. 1, FIG. 3 shows a metal lid shown in FIG. 1, and FIG. 4 shows a metal lid shown in FIG. 1. FIG. 5 is an explanatory diagram of a welding method, FIG. 5 is a welding electrode, FIG. 6 is a conventional semiconductor device, and FIG. 7 is an explanatory diagram of a method of welding a metal lid in a conventional semiconductor device. In the figure, 4 is a semiconductor chip, 21 is a semiconductor device, 22 is a package base, 25 is a recess, 26 is a metal seal frame, 27 is a metal lid, 29 is an inner edge, 31 is an inner edge of the metal lid, 32 is an electrode, and 34 is a support arm. ) Kigyokumei's family precedent: more half-body device 11 prisoner 0 'Jg1 The seal frame shown in figure 11th printing; \1&: Torigo no Kyou-Kouho no Kada σ Monthly conventional +1 body food 5% G No.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体チップ(4)を収容する凹所(25)の形
成されたパッケージ基体(22)の上面には、該凹所(
25)を囲い少なくともコーナ部に適当な丸みを有する
金属のシールフレーム(26)が取着され、該シールフ
レーム(26)に載置した金属の蓋(27)が、該シー
ルフレーム(26)の内縁エッジ(29)に沿ってシー
ム溶接されてなることを特徴とする半導体装置。
(1) On the upper surface of the package base (22) in which the recess (25) for accommodating the semiconductor chip (4) is formed, the recess (25) is formed.
A metal seal frame (26) that surrounds the seal frame (25) and has an appropriate roundness at least at the corners is attached, and a metal lid (27) placed on the seal frame (26) is attached to the seal frame (26). A semiconductor device characterized by being seam-welded along an inner edge (29).
(2)半導体チップ(4)を収容する凹所(25)の形
成されたパッケージ基体(22)の上面に形成され、該
凹所(25)の周囲を囲み、丸みを帯びたコーナ部を有
するシールフレーム(26)上に、該凹所(25)を塞
ぐように該シールフレーム(26)の内縁エッジ(29
)に沿って曲げ加工されてコーナ部(31)を有する金
属の蓋(27)を載置する工程と、 該シールフレーム(26)の内側からの支持アーム(3
4)によって支持される電極(32)が、該金属の蓋(
27)の内縁エッジ(31)を該シールフレーム(26
)の内縁エッジ(29)に向けて押すと共に、該電極(
32)に電流を流し該シールフレーム(26)の内縁エ
ッジ(29)と該金属の蓋(27)とを溶接する工程と
、を有することを特徴とする半導体装置の製造方法。
(2) Formed on the upper surface of the package base (22) in which a recess (25) for accommodating the semiconductor chip (4) is formed, surrounding the recess (25), and having a rounded corner portion. An inner edge (29) of the seal frame (26) is placed on the seal frame (26) so as to close the recess (25).
) and a step of placing a metal lid (27) having a corner portion (31) by bending along the edge of the seal frame (26);
The electrode (32) supported by the metal lid (
The inner edge (31) of the seal frame (27)
) towards the inner edge (29) of the electrode (
32) to weld the inner edge (29) of the seal frame (26) and the metal lid (27).
JP1183082A 1989-07-13 1989-07-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2689621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1183082A JP2689621B2 (en) 1989-07-13 1989-07-13 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1183082A JP2689621B2 (en) 1989-07-13 1989-07-13 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0346259A true JPH0346259A (en) 1991-02-27
JP2689621B2 JP2689621B2 (en) 1997-12-10

Family

ID=16129448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1183082A Expired - Fee Related JP2689621B2 (en) 1989-07-13 1989-07-13 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2689621B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202058A (en) * 1993-12-30 1995-08-04 Nec Corp Semiconductor device
JP2002353350A (en) * 2001-05-28 2002-12-06 Kyocera Corp Package for storing electronic part

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4580881B2 (en) * 2006-03-08 2010-11-17 株式会社住友金属エレクトロデバイス Rectangular metal ring brazing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202058A (en) * 1993-12-30 1995-08-04 Nec Corp Semiconductor device
JP2002353350A (en) * 2001-05-28 2002-12-06 Kyocera Corp Package for storing electronic part

Also Published As

Publication number Publication date
JP2689621B2 (en) 1997-12-10

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