JPH0345947B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a received signal time width adjustment device for time division multiplex transmission, etc.

If noise or the like enters the transmission path during time division multiplex transmission, the transmission will be interrupted during that time. This interruption causes the time width of the transmission signal to fluctuate. If the time width of the transmitted signal fluctuates in this way and becomes less than the minimum allowable time width required on the receiving side, it may become impossible for the receiving side to distinguish between the transmitted signals.

This invention has been made in view of the above-mentioned circumstances, and the received signal that is extremely shorter than a preset time width and the received signal that is longer than the set time width are output as they are, and the received signal that is extremely short than the extremely short received signal is It is an object of the present invention to provide a received signal time width adjustment device that corrects all received signals to a preset time width when the received signal is long and shorter than a set time width.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an OR circuit, and a received signal A is supplied to the first input of this OR circuit 1. The output signal of the OR circuit 1 is supplied to an amplifier (not shown) as an output signal of a received signal time width adjustment device, and is also supplied to the set side S of a shift register 2 consisting of a flip-flop. The shift register 2 is composed of seven stages of flip-flops ₂₁ to ₂₇ , each stage is supplied with a timing signal CL from an oscillator OSC, and the set side S of the flip-flop ₂₁ of the first stage and the The output signal of the output side _{Q2 of the second stage flip-flop 22 is} input to the first AND circuit 3. Reference numeral 4 denotes a knot circuit inserted between the reset side R of the shift register 2 and the output terminal of the OR circuit 1. 5 is a second AND circuit, the first input of which is supplied with the output signal of the first AND circuit 3, and the second input is supplied with the output signal of the seventh stage constituting the shift register 2. An output signal from the inverting output ₇ of the flip-flop ₂₇ is supplied. The output signal of the second AND circuit 5 is supplied to the second input of the OR circuit 1.

Before describing the operation of the embodiment, the operation of the shift register applied to the present invention will be described with reference to FIGS. 3 to 6. (This shift register is a well-known general type.) In Fig. 3, each of the shift registers 2 ₁ to 2 ₃ ... has "S" and "R" as input sections, and "Q" as output section. It has “CL” as a timing input.

The input parts “S” and “R” are as shown in FIG.
1 and 0 are inverted with respect to each other, and the states of "S" and "R" at the rising edge of the timing input "CL", t _1U and t _2U , are the states of "S" and "R" at the rising edge of the next "CL", t _1D ,
t _2D has the function of outputting to output sections "Q" and "", respectively.

In order to invert the input parts "S" and "R", in the case of the first stage shift register 2 ₁ , the input signal "I" is connected to "S ₁ " as shown in FIG. “I” is inverted and connected to “R ₁ ” by a knot circuit 4.

Each input “S” of the shift register after the second stage,
Since the outputs "Q" and "" of the shift register at the previous stage are inverted as shown in FIG. 4, "R" is directly connected as shown in FIG. 3.

The timing signal "CL" is supplied to each shift register as shown in FIG. 3 by an oscillator with a required period (the period is T in FIGS. 5 and 6).

Figure 5 shows that even when the pulse width of “S ₁ ”, which is equivalent to the input signal “I”, is from the minimum shown by the solid line to “just under 2T” shown by the dotted line, the above-mentioned “S 1 ” at the rising edge of the CL signal is ”, “R” states are output to the outputs “Q” and “” at the next rise of the CL signal, respectively, thereby illustrating a relationship in which the output pulse width is set to a constant value “T”.

Figure 6 similarly shows an example where the input signal width "T" becomes the output signal width "T", an example where "3T or less" is reduced to "2T", and an example where "4T or more" becomes "ST". In other words, it shows the function of correctly setting the input signal width to an integral multiple of "T" and the fact that the next stage is delayed (shifted) by a cycle "T" from the previous stage.

Next, the operation of the embodiment configured as described above will be described.

Suppose that a received signal A of, for example, 20 m _sec to 60 m _sec or less, as shown by the solid line in FIG. 2 A, arrives at the first input _of the OR circuit 1 (in the example of FIG.
below). This signal is outputted to the output terminal I of the OR circuit 1, and inputted to the set side S of the first stage flip-flop ₂₁ of the shift register 2. Since a clock signal with a period of 10 _msec is supplied to the shift register 2, the input signal is shifted by the flip-flop ₂₁ in the first stage, and the output side _Q1 is outputted as shown in Fig. 2B. The rising wavelength appears after being shifted by 0 to 10 m _sec . The output sides _Q2 to _Q7 of each flip-flop ₂₂ to ₂₇ are shown in Fig. 2C.
A rising waveform shifted by 10 m _sec as shown in ~H is obtained. At this time, the input signal of the flip-flop ₂₁ and the output signal I and C of the flip-flop ₂₂ are input to the first AND circuit 3, and since the received signal A is less than 20 _msec , both I and C are output at the time of _T1 . When the AND condition is satisfied, the rising signal shown in FIG. 2J is supplied to the second AND circuit 5. Second
When the signal shown in FIG. 2 J is supplied to the first input of _the AND circuit 5, the signal _K shown in FIG. has been done. This signal is "1" at time _T1 . This name,
The output L of the second AND circuit 5 in FIG. 2 changes from "0" to "1". This output state continues until the output _Q7 of the flip-flop ₂₇ has a shifted waveform as shown in FIG. 2H, and the inverted output ₇ becomes " ₀ ". Time T ₂ until the flip-flop ₂₇ sends out the inverted output ₇
If the time width between _T1 and the time T1 required for the flip-flop ₂₂ to send out the output _Q2 is set to 50 _msec , even if the received signal A disappears between _T1 and _T2 , the OR circuit 1 Since the output signal I of the OR circuit 1 continues due to the second input L of _the
All 60 m _sec output signals are 60 m _sec to 70 m _sec of the 10 to 20 m _sec from the rise of the received signal A to the T ₁ time in Figure 2 and the 50 m _sec time from T ₁ to T ₂ . The signal is corrected and supplied to an amplifier (not shown).

In this embodiment, a signal with a duration of 70 m _sec or more is transmitted during normal operation, but even if a short signal of 20 m _sec or less arrives at the first input of the OR circuit 1 due to noise etc. The signal shown in is the output signal as it is. This is because the received signal A disappears before the signal is output to the shift register 2, so the signal disappears, the AND condition of the first AND circuit 3 does not hold, and the output signal J does not rise. Originally, short signals caused by noise should be eliminated and not used as output signals, but doing so would require a filter and cause a time delay between input and output. Therefore, in this embodiment, the signal is output as is because it is desired to reduce the delay as much as possible, and because the receiving side does not react with a short signal and does not cause malfunction. Furthermore, even in the case of a long signal of 70 m _sec or more, the time width of signal A is input to the amplifier as it is as an output signal, since A◯◯ in Fig. ₂ is longer than the time T2.

As described above, according to the present invention, when a signal with a cycle that is extremely shorter than a signal with a preset cycle and a signal that is longer than that, the signal is sent as is, and a signal with a cycle that is within a preset range is transmitted as is. Since all the signals are sent out as signals corrected to the set period, there is an advantage that the transmitted signals can be sufficiently discriminated even if the time width of the transmitted signals fluctuates somewhat.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 A to L are time charts of the operation explanatory diagram of Fig. 1, and Figs. 3 to 6 are shift registers applied to this invention. 3 is a block diagram, and FIGS. 4 to 6 are time charts. 1...OR circuit, 2...Shift register, 2 ₁
From 2 ₇ ...flip-flop, 3...first AND circuit, 4...not circuit, 5...second AND circuit.

Claims (1)

[Claims] 1 An OR circuit to which the received signal is supplied to a first input, an output end of this OR circuit connected to the set side and the reset side connected via a NOT circuit, and a shift operated by the output signal of the OR circuit. The register and the output terminal of the second stage on the set side of the first stage of this shift register are respectively connected to the input terminal, and the first stage outputs the AND output of both input terminals.
an AND circuit, the output terminal of the first AND circuit and the inverted output terminal of the final stage of the shift register are connected to the input terminals, respectively, and the AND output of both input terminals is supplied to the second input of the OR circuit. A received signal time width adjustment device comprising a second AND circuit and an oscillator that is supplied to the shift register and sends out a signal for controlling the output timing of the shift register.