JPS61288514A - Circuit for compensating missing pulse - Google Patents

Abstract

PURPOSE:To obtain a signal where almost no pulse missing takes place with a simple device while not requiring other signal by allowing a reception signal itself to correct missing pulse in the reception signal. CONSTITUTION:If pulse missing takes place in an output of a limiter amplifier 2, a reference reproducing signal outputted from a driver 3 is divided into two; one is delayed by 3pi/2 by a delay device 4 and latched by the leading of the reference reproducing signal at a flip-flop 5 and by the leading of the inverted reference reproducing signal at a flip-flop 6. If the reference reproducing signal has a missing pulse, a pulse of one period length appears at any output of the flip-flops 5, 6 and converted into a pulse at a half-period at the next gate. In taking the sum of delay times at points 4, 6, 10 as T1, the other reference reproduction signal being the division is delayed by T1 at a point 11 and inputted to a AND gate 12 and the missing pulse is corrected. Further, an output 9 is delayed by a delay time T2 at a point 12 and the result is inputted to an OR gate 14. Then the remaining missing pulse is corrected and a signal with less missing pulse is outputted at an output terminal 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a limiter circuit ζ2 that stabilizes a received signal with level fluctuations and performs Peruni adjustment.

[Conventional technology]

FIG. 3 is an example of a block diagram of a conventional limiter circuit. In the figure, (1) is an input terminal, (2) is a +7 mitter amplifier, and 9 is an output terminal.

Next, the operation will be explained using two terminals.The received signal input to the terminal (1) is amplified to a constant limiter output level by the limiter amplifier (21), and becomes a rectangular wave to the terminal (15).
1m output.

[Problem that the invention seeks to solve]

Since conventional limiter circuits are configured as described above, the limiter input signal contains noise components, and as shown in Figure 5 (:), the amplitude of the input signal may not exceed the threshold value in a certain period. Then, there was a problem that pulses in that part of the output signal were missing.

The present invention was made in order to solve the above-mentioned problems.It is an object of the present invention to provide a limiter that compensates for pulse loss in a limiter amplifier output signal and outputs an output without pulse loss.

[Means for solving problems]

The limiter circuit according to the present invention includes a conventional limiter circuit followed by a C driver, followed by a pulse missing detection circuit 1.2.
A correction circuit consisting of a delay device 1.2, an AND gate, and an OR gate is installed.

[Effect]

The correction circuit in this invention (:) detects the pulse loss of the reference reproduction signal which is the output of the driver by the pulse loss detection circuit 1.2.
The pulse path detection circuit 1-2 generates a pulse with a half-period length, and adds or removes this pulse to the missing pulse portion of the reference reproduction signal, which is timed by a delay device. Reproduction signal (=corrects the included pulse loss.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In Figure 1, ill is an input terminal, (2) is a limiter amplifier, (31 is a driver, (4) is a delay device that delays the phase by /2, +51 and +61 are D-type flip-flops, [71, 181 is a delay device that delays the phase by π, (9J, concave is NOR and NAND gate respectively, ■.

(13 is a delay device that delays the signal by TI and T2, respectively, (AL (14) is an output terminal, (151 is an output terminal. The blocks indicated by ue and aη are pulse missing detection circuits 1 and 2, respectively. , (181
The block shown in is called a correction circuit! - to do. ■〜0
is a checkpoint to see the signal with the same number shown in the timing chart of FIG.

! 5 shows a timing chart when a pulse drop occurs in the limiter amplifier output of (2)'' in FIG. 1''--FIG.

In Fig. 1, the reference reproduction signal (■) output from the driver (3) is divided into two parts, one of which is delayed by 0/2 in the delay device (4), and then (■), which is output from the flip-flop 1 of (61). : is the rising edge of the inverted reference reproduction signal (■), and in the flip-flop (5), the reference reproduction signal (■) is rising.
■) is latched at the rising edge. If there is a pulse dropout in the reference reproduction signal, +51. (61 either 7
Lip-flop output 1: A pulse with a period length of 1 appears (0
, 0), these pulses are ground in the next gate for half a period of pulse 1: (O20). Also, (41, +61,
If the sum of the transmission delay times of αα is Tt, the other divided reference reproduction signal is delayed by TI in (11) and (
[phase]), along with the concave output signal (13 AND gate 1: is input, and some pulse omissions are corrected. Also, t
The output (■) of 9+ is delayed (@) by the transmission delay time T2 of (I) and is input to the OR gate of I together with the output of α2, where the remaining pulse loss is corrected, (15)
A signal (O) with few pulse dropouts is output to the output terminal of.

〔Effect of the invention〕

As described above, according to the present invention, since the pulse loss in the received signal is corrected by the received signal itself, there is no need for other signals, and a signal with almost no pulse loss can be obtained with a simple device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a pulse loss compensation circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of each part of the $1 diagram, and FIG. 3 is a block diagram showing a limiter device. 4 and 5 are waveform diagrams showing output signals of the limiter device. (1) is an input terminal, (21 is a limiter amplifier, (3) is a driver, (41 is a 3π/2 delay device, +51, +
61 is a D type flip 70 tube, +71, 181 is a π delay device, +91. (1G is NOR and NAND, respectively.
/7'-t, C11), (13 HA L Tsure Tt, T
z delay device, α21. (14) Hout are AND and OR gates respectively, αω is an output terminal, αe and η are pulse dropout detection circuits 1.2, (181 is a correction circuit). In addition, the same reference numerals in the figures indicate the same or equivalent parts. .

Claims (1)

[Claims] A driver inputs the output of a limiter amplifier that inputs a received signal and outputs a square wave signal with a constant level, and outputs a reference reproduction signal and an inverted reference reproduction signal whose polarity is reversed, and Consists of a D flip-flop that inputs a signal delayed by a predetermined phase to the D terminal and an inverted reference reproduction signal input to the clock terminal, and a gate that inputs the signal delayed in phase of the output of the flip-flop 2 and the flip-flop output signal. A pulse loss compensation circuit comprising: a pulse loss detection circuit; and a gate that receives the output of the pulse loss detection circuit and a signal obtained by delaying the reference reproduction signal by the same time as the delay time of the pulse loss detection circuit 1.