JPS6025754Y2 - Read/write timing pulse generation circuit in storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing pulse generation circuit for controlling drive current pulses in a memory device.

As shown in FIG. 1, a conventional timing pulse generation circuit of this type is a pulse generation circuit 1 which generates one pulse of a predetermined width (FIG. 3b) when a starting pulse (FIG. 3a) is input. and a delay line 2 that sequentially transmits the output thereof.

Each tap output of the delay line 2 becomes a delayed signal.

FIG. 3C shows the intermediate tap output, and d shows the final tap output.

The read timing pulse generation circuit 3 is composed of, for example, a flip-flop, and generates the tap output of the delay line 2 that is delayed by a predetermined time from the activation pulse until the appearance of the read timing, and the read pulse from that tap output. The read timing pulse is obtained by setting and resetting with two tap outputs, one delayed by a width of .

It is also possible to use a logic circuit instead of a flip-flop to AND the two tap outputs of the delay line 2 to obtain the read timing pulse.

Like the read timing pulse generation circuit 3, the write timing pulse generation circuit 4 is also composed of flip-flops and logic circuits, and outputs two taps of the delay line 2 so as to obtain a pulse of a constant width after a constant time from the start pulse. is selected.

Figures 3e and 3f show the read timing pulse and write timing pulse, respectively.

However, in the conventional method, in order to obtain the desired read and write timing pulses, it is necessary to increase the length of the delay line. For example, when using a delay line of about 10 taps, it is necessary to connect multiple delay lines in cascade. there were.

This means a high cost for the equipment.

An object of the present invention is to provide a circuit that can obtain longer read and write timing pulses than conventional ones using a short delay line with a simple circuit configuration.

The present invention will be described in detail below with reference to embodiments shown in the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which the double pulse generating circuit 11 operates in response to the starting pulse shown in FIG. 4 C, which is similar to that shown in FIG. This circuit outputs two consecutive signals as shown in FIG. 4 (1).

The output of the double pulse generating circuit 11 is input to the input 12 with a delay, and is sequentially transmitted while being delayed.

The read timing pulse generation circuit 13, similar to 3 in FIG. 1, is a circuit that combines the tap outputs of the delay line 12 to generate a pulse with a desired pulse width at a desired time position. It can be composed of a loop circuit.

In this case, the tap output of the delay line 12 outputs double pulses that are delayed from the double pulses shown in Figure 4, so the read timing pulse is formed by focusing on the earlier of the double pulses. Even if Jt is used, a pulse generated from the later pulses will be obtained following this.

That is, in the output of the read timing pulse generation circuit 13, unnecessary pulses accompany the required read timing pulses as shown in FIG. 4C.

On the other hand, the write timing pulse generation circuit 14 similarly
This circuit is composed of logic circuits, flip-flop circuits, etc., and combines predetermined tap outputs of the delay relays 12 to create a write timing pulse of a required time width at a required time position.

In this case, focusing on the later pulse of the double pulses of each tap output of the delay relay, the tap outputs are combined to obtain the desired write timing pulse.

In this way, the write timing pulse generation circuit 14
In this case, the desired write timing pulse is obtained as shown in FIG. 4d, but the pulse based on the preceding pulse of the double pulse of the tap output of the delay relay 12 appears before the write timing pulse.

Masking circuits 15 and 16 are connected to the output sides of the read timing pulse generation circuit 13 and the write timing pulse generation circuit 14, respectively, and are circuits for removing unnecessary pulses appearing in the respective outputs, and operate with the output from the masking signal generation circuit 17. do.

Masking signal generation circuit 17 combines the outputs of the starting tap and intermediate tap of delay relay 12 and sends masking command signals to masking circuits 15 and 16, respectively.

A one-shot multi can be used as the masking signal generation circuit 17, and its Q output and Q output are connected to the masking circuit 1.
5 and 16 as masking command signals.

FIG. 4e shows a masking command signal to the masking circuit 15, which operates the masking circuit 15 to pass only the preceding pulse among the double pulses output from the read timing pulse generation circuit 13 and mask the others. It has become.

Therefore, a read timing pulse as shown in FIG. 4f can be obtained from the masking circuit 15.

FIG. 4g shows a masking command signal to the masking circuit 16, which operates the masking circuit 16 so that only the later pulses of the write timing pulse generation circuit are passed through and the others are masked. .

In this way, a write timing pulse as shown in the fourth diagram can be obtained from the masking circuit 16.

A gate circuit can be used as the masking circuit.

A read/write method in a storage device in which pulses with a fixed width are sequentially delayed and transmitted using a delay line, and the outputs of each tap are combined to generate read timing pulses and write timing pulses with the required time width and time position. In the write timing pulse generation circuit, the present invention inputs a double pulse to the delay line, obtains the preceding read timing pulse by a combination of the preceding double pulses of the tap output of the delay line, and generates the subsequent write timing pulse. As a result, even if a delay line of the same length as the conventional one is used, the pulse after the double pulse from the last tap is obtained from the input time of the input pulse of the starting tap. The time width, interval, and time position of the pair of mode and write timing pulses can be changed freely within the time until the end of the output. You can freely choose between these within the time until the end of the pulse.

Therefore, read and write timing pulses can be freely obtained with a shorter delay line than in the past.

Note that, if the tap output of the delay line 12 is utilized, the double pulse generating circuit 11 is constructed of the conventional pulse generating circuit 1 that generates a single pulse and a simple logic circuit.

For example, an OR circuit is provided on the input side of a pulse generating circuit similar to 1 in Fig. 1, such as a one-shot multi, and one input is used as a starting pulse, and the other input is used as a differential waveform of a predetermined tap output of a delay line. It's fine if you do this.

In this case, this differential wave causes the pulse generation circuit to generate a second pulse, resulting in a double pulse.

In this case, a gate is provided between the differential output and the OR circuit to prevent the differential wave of the tap output from entering the pulse generation circuit again due to the delayed transmission of the second pulse. All you have to do is combine the tap outputs of the delay lines and close them.

Since the first pulse and the second pulse enter the delay line with a time difference from each other, these pulses also appear on one tap with a time difference.

Therefore, it is possible to operate the gate circuit in such a way that the differential output of the first pulse appearing at one tap passes through, but not the differential output of the second pulse, by using the outputs of other taps of the delay line. It is.

As described above, the present invention does not use long delay lines.
There is an advantage that a pair of read and write timing pulses can be freely selected within a relatively long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the conventional technology, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the time relationships of various signals to explain the operation of FIG. 1. , FIG. 4 is a diagram showing the time relationship of signals of each part for explaining the operation of the embodiment of FIG. 2. 11...Double pulse generation circuit, 12...
... Delay line, 13 ... Read timing pulse generation circuit, 14 ... Write timing pulse generation circuit, 15.16 ... Masking circuit,
17...Masking command signal generation circuit.

Claims (1)

[Scope of utility model registration request] a generation circuit that generates a pulse of a predetermined width in response to one activation pulse; a delay line that delays the output of the pulse generation circuit; a circuit that creates a read timing pulse from a predetermined tap output of the delay line; In a read/write timing pulse generation circuit in a storage device having a circuit for generating a write timing pulse from a predetermined tap output, the pulse generation circuit receives the one activation pulse and continuously generates two pulses of the predetermined width. It is configured as a double pulse generation circuit to output two pulses.
two masking circuits are provided for masking the latter of the double pulses appearing at the output of the read timing pulse generation circuit and masking the earlier of the double pulses appearing at the output of the write timing pulse generation circuit; The earlier pulse of the double pulse output from the read timing pulse generation circuit is output as the read timing pulse, and the later pulse of the double pulse appearing at the output of the write timing pulse generation circuit is output as the write timing. A read/write timing pulse generation circuit in a storage device configured as described above.