JPS5840676Y2 - receiving circuit - Google Patents

receiving circuit

Info

Publication number
JPS5840676Y2
JPS5840676Y2 JP1976154550U JP15455076U JPS5840676Y2 JP S5840676 Y2 JPS5840676 Y2 JP S5840676Y2 JP 1976154550 U JP1976154550 U JP 1976154550U JP 15455076 U JP15455076 U JP 15455076U JP S5840676 Y2 JPS5840676 Y2 JP S5840676Y2
Authority
JP
Japan
Prior art keywords
signal
circuit
amplifier
receiving circuit
amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1976154550U
Other languages
Japanese (ja)
Other versions
JPS5372425U (en
Inventor
清太郎 宮島
勇二 三品
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1976154550U priority Critical patent/JPS5840676Y2/en
Publication of JPS5372425U publication Critical patent/JPS5372425U/ja
Application granted granted Critical
Publication of JPS5840676Y2 publication Critical patent/JPS5840676Y2/en
Expired legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Noise Elimination (AREA)

Description

【考案の詳細な説明】 一般に長い伝送線路を経由してデータを受信する端末装
置において、受信信号に混入するノイズのため色々な誤
動作が発生する。
[Detailed Description of the Invention] Generally, in a terminal device that receives data via a long transmission line, various malfunctions occur due to noise mixed into the received signal.

本考案は、このような分野で耐ノイズ性能を強化する手
段を必要とする端末装置に適用する受信回路に関する。
The present invention relates to a receiving circuit applied to a terminal device in such a field that requires means for enhancing noise resistance.

従来用いられてきた方法として、ノイズフィルタの挿入
がある。
A conventionally used method is to insert a noise filter.

この方法は極めて単純であり相当の効果が期待出来るも
ので今後共多用されると考えられるが、信号の伝送速度
が高速になると応答性という面で問題が発生する。
This method is extremely simple and can be expected to be quite effective, so it is thought that it will be used frequently in the future, but as the signal transmission speed increases, problems arise in terms of responsiveness.

また、別の方法として信号の最小パルス幅より十分に短
い時間幅Tを設定し、T以下の時間幅を持つパルスを無
視する手段も各種提案されている。
In addition, as another method, various methods have been proposed in which a time width T is set sufficiently shorter than the minimum pulse width of the signal, and pulses having a time width smaller than T are ignored.

この方法も大変有効な方法であるが、混入するノイズの
パルス幅が広い場合には適用出来ない。
Although this method is also very effective, it cannot be applied when the pulse width of the mixed noise is wide.

そこで本考案は、受信する信号レベルが比較的大きいこ
とが期待出来る場合において、信号レベルに比べ、低レ
ベルの混入ノイズを不感動レベルを設定することによっ
て、受信信号に混入するノイズを排除する受信回路の実
現を目的とする。
Therefore, in the case where the received signal level can be expected to be relatively large, the present invention aims to eliminate the noise mixed in the received signal by setting a low-level mixed noise level compared to the signal level. The purpose is to realize the circuit.

本考案によれば、受信信号から互いに逆相の2つの信号
を取出す。
According to the present invention, two signals having mutually opposite phases are extracted from a received signal.

この逆相の信号をA信号、B信号とする時、A信号を第
1の増幅器へ、B信号を第2の増幅器へ印加する。
When these opposite phase signals are used as an A signal and a B signal, the A signal is applied to the first amplifier and the B signal is applied to the second amplifier.

第1.第2の増幅器は自己のしきい値を越えた入力信号
に対して動作し、しきい値以下の(バイアス電圧によっ
て深くなった)入力信号に対しては動作せず不感動領域
となる。
1st. The second amplifier operates in response to an input signal exceeding its own threshold value, and does not operate in response to an input signal below the threshold value (deepened by the bias voltage), resulting in an insensitive region.

第1.第2の増幅器の出力からはそれぞれ180°位相
の異なる同一波形が得られ、次段の整形回路により信号
を整形する。
1st. The same waveforms having a phase difference of 180° are obtained from the outputs of the second amplifiers, and the signals are shaped by the shaping circuit in the next stage.

第1図は本考案の一実施例のブロック図であり、1は通
信線路から信号を受信するための受信変成器、2および
3はバイアス回路であり、3に矢印を付しであるのはバ
イアス電圧を可変にすることを示している。
FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a receiving transformer for receiving signals from a communication line, 2 and 3 are bias circuits, and 3 is marked with an arrow. This shows that the bias voltage can be made variable.

4,5は1対の増幅器、6は整形回路である。4 and 5 are a pair of amplifiers, and 6 is a shaping circuit.

この例では、受信変成器1として2次側巻線センタタッ
プを付した平衝形結合変成器を用いて、センタタップに
バイアス電圧を与え両端子を増幅器4,5に接続して逆
相信号を得る例を示している。
In this example, a balanced coupling transformer with a secondary winding center tap is used as the receiving transformer 1, a bias voltage is applied to the center tap, both terminals are connected to amplifiers 4 and 5, and the reverse phase signal is output. Here is an example of how to get .

第2図において、Aは増幅器4に印加する波形であり、
Bは増幅器5に印加する波形である。
In FIG. 2, A is the waveform applied to the amplifier 4,
B is a waveform applied to the amplifier 5.

7はそれぞれの増幅器のしきい値であり、このしきい値
を越えた電圧(図中の斜線部)により増幅器が動作する
7 is a threshold value of each amplifier, and the amplifier is operated by a voltage exceeding this threshold value (shaded area in the figure).

8はバイアス電位である。増幅器4,5の出力はそれぞ
れC,Dに示すものとなり、受信波形と比べそれぞれテ
゛ニーティサイクルが異なるが、次段の整形回路6はフ
リップフロップであって、増幅器4の信号によってセッ
ト、増幅器5の信号によってリセットされるものであり
、整形回路6の出力でEに示す波形を得ることが出来る
8 is a bias potential. The outputs of amplifiers 4 and 5 are as shown in C and D, respectively, and have different tenity cycles compared to the received waveform, but the shaping circuit 6 at the next stage is a flip-flop, and is set by the signal from amplifier 4, and is set by the signal from amplifier 5. The waveform shown in E can be obtained from the output of the shaping circuit 6.

なお、第2図においては、受信信号を正弦波により表現
したが、一般のテ゛イジタルデータ伝送では方形波或は
パルス波形の信号形態が多く、本考案によれば、信号の
立上り、立下りが割に急峻であるため、信号のエツジ(
立上り部、立下り部)に乗るノイズはあまり影響を受け
ない。
In Fig. 2, the received signal is expressed as a sine wave, but in general digital data transmission, the signal form is often square wave or pulse waveform, and according to the present invention, the rising and falling edges of the signal are The edge of the signal (
Noise on the rising edge and falling edge is not affected much.

また、伝送路がらの受信を受けていない状態でノイズの
み入力して来て誤動作を誘発する如きトラブルに対し効
果は大きい。
Furthermore, it is highly effective against troubles such as noise that is input only when no signal is being received from the transmission line, inducing malfunctions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロック図、第2図は第1
図の各部波形を示した図である。 図において 1・・・・・・受信変成器、2,3・・間
バイアス回路、4,5・・・・・・増幅器、6・・・・
・・整形回路。
Fig. 1 is a block diagram of an embodiment of the present invention, and Fig. 2 is a block diagram of an embodiment of the present invention.
It is a figure which showed the waveform of each part of a figure. In the figure: 1...receiving transformer, 2, 3... bias circuit, 4, 5... amplifier, 6...
...Shaping circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 伝送線路と接続される受信回路において、受信信号から
互いに逆相の2つの信号を得る回路と、当該回路からの
2つの信号がそれぞれ入力される1対の増幅器と、当該
増幅器の各々に共通なバイアス電位を与えるバイアス回
路とを備えた受信回路。
A receiving circuit connected to a transmission line includes a circuit that obtains two signals with opposite phases from the received signal, a pair of amplifiers into which the two signals from the circuit are respectively input, and a circuit that is common to each of the amplifiers. A receiving circuit comprising a bias circuit that provides a bias potential.
JP1976154550U 1976-11-19 1976-11-19 receiving circuit Expired JPS5840676Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1976154550U JPS5840676Y2 (en) 1976-11-19 1976-11-19 receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1976154550U JPS5840676Y2 (en) 1976-11-19 1976-11-19 receiving circuit

Publications (2)

Publication Number Publication Date
JPS5372425U JPS5372425U (en) 1978-06-17
JPS5840676Y2 true JPS5840676Y2 (en) 1983-09-13

Family

ID=28762703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1976154550U Expired JPS5840676Y2 (en) 1976-11-19 1976-11-19 receiving circuit

Country Status (1)

Country Link
JP (1) JPS5840676Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5618021Y2 (en) * 1974-10-21 1981-04-27

Also Published As

Publication number Publication date
JPS5372425U (en) 1978-06-17

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