JPS5954344A - Timing reproducer - Google Patents

Timing reproducer

Info

Publication number
JPS5954344A
JPS5954344A JP57165359A JP16535982A JPS5954344A JP S5954344 A JPS5954344 A JP S5954344A JP 57165359 A JP57165359 A JP 57165359A JP 16535982 A JP16535982 A JP 16535982A JP S5954344 A JPS5954344 A JP S5954344A
Authority
JP
Japan
Prior art keywords
circuit
output
input
delay
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57165359A
Other languages
Japanese (ja)
Other versions
JPH0328862B2 (en
Inventor
Tomio Kato
富雄 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP57165359A priority Critical patent/JPS5954344A/en
Publication of JPS5954344A publication Critical patent/JPS5954344A/en
Publication of JPH0328862B2 publication Critical patent/JPH0328862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0276Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate

Abstract

PURPOSE:To attain timing reproduction from an NRZ code with a simple constitution, by providing the 1st and the 2nd pulse generating circuits comprising an AND circuit, delay circuit and an NOT circuit, and a circuit picking up an NOR output of the AND circuit so as to eliminate malfunction. CONSTITUTION:The 1st pulse generating circuit 20 comprises an AND circuit 11, a delay circuit 13 giving a delay to its output by a 1/2-bit length of a receiving signal, and an NOT circuit 17 inverting its output and applying the result to other input of the AND circuit 11. The 2nd pulse generating circuit 21 comprises an AND circuit 12 taking an input signal inverted at an NOT circuit 16 as one input, a delay circuit 14 giving a delay to its output by a 1/2-bit length of a receiving signal, and an NOT circuit 18 inverting its output and applying the result to the other input of an AND circuit 12. Further, the NOR circuit of the AND circuits 11, 12 is picked up at an NOR circuit 15.

Description

【発明の詳細な説明】 発明の技術分野 本発明は自己同期式のベースバンドデータ伝送において
NIIZ符号からタイミング再生するタイミング再生装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a timing recovery device for recovering timing from a NIIZ code in self-synchronous baseband data transmission.

従来技術と問題点 ベースバンドデータ伝送における符号方式に、RZ (
Retwrn to Zero )符号方式とNRZ 
(Non Returnto Zero )符号方式と
が知られているが、後者の方が前者より符号化回路及び
復号化回路の構成が簡単であり且つ同一の送受信要素を
用いて約2倍のデータ伝送速度が実現できることから、
特に高速のデータ伝送に賞月されている。しかし、連続
する1″或いは“θ″が含まれる場合ベースバンド信号
に変化点が現れないことから、そのタイミング再生装置
はRZ符号方式における同種装置より構成が複雑となり
又精度の点でも問題がある。
Prior Art and Problems RZ (
Return to Zero) coding system and NRZ
(Non Return to Zero) encoding system is known, but the latter has a simpler configuration of the encoding circuit and decoding circuit than the former, and the data transmission speed is approximately twice as high using the same transmitting and receiving elements. Because it can be achieved,
It has been particularly praised for its high-speed data transmission. However, since no change point appears in the baseband signal when consecutive 1'' or θ'' are included, the timing regeneration device has a more complex configuration than a similar device in the RZ coding system, and also has problems in terms of accuracy. .

例えば第1図に示すように、NRZ符号を受けてその信
号に同期した正極性の信号e1を発生するワンショット
マルチバイブレータ1と、同じくNRZ符号を受けて負
極性の(信号C2を発生するワンショットマルチバイブ
レータ2と、前記信号C1を入力とするオア回路ろと、
このオア回路乙の出力をワンショットマルチバイブレー
タ4.5を介して一方の入力とし前記信号e2を他方の
入力とするアンド回路6とを備え、ビットタイミングな
オア回路乙の出力から得るように構成したタイミング再
生装置が知られている(特開昭52−95106号公報
ン。しかし、4つものワンショットマルチバイブレータ
を必要とする為依然回路構成は複雑であり、また木質的
にノイズに弱いワンショットマルチバイブレータを用い
ているので誤動作し易い欠点がある。即ち、データの送
受信回路は一般的に伝送線に係るノイズの侵入を受は易
いところにあり、入力に瞬時の信号(ひげ状のノイズ等
〕が含まれることが多く、これによりワンショットマル
チバイブレータがトリガされて誤動作するものである。
For example, as shown in FIG. 1, there is a one-shot multivibrator 1 that receives an NRZ code and generates a positive polarity signal e1 synchronized with the signal, and a one-shot multivibrator that also receives an NRZ code and generates a negative polarity signal C2. A shot multivibrator 2 and an OR circuit inputting the signal C1,
An AND circuit 6 is provided which receives the output of this OR circuit B via a one-shot multivibrator 4.5 as one input and the signal e2 as the other input, and is configured to obtain the output from the bit timing OR circuit B. A timing regenerator is known (Japanese Unexamined Patent Publication No. 52-95106).However, the circuit configuration is still complicated because it requires as many as four one-shot multivibrators, and the one-shot multivibrator is weak against noise due to its wooden structure. Because it uses a Schott multivibrator, it has the disadvantage of being prone to malfunction.In other words, data transmitting/receiving circuits are generally susceptible to the intrusion of noise related to transmission lines, and the input is subject to instantaneous signals (whisker-like noise). etc.], which triggers the one-shot multivibrator and causes it to malfunction.

発明の目的 本発明はそのような誤動作をなくし、然もより簡単な回
路構成でNIIZ符号からタイミング再生することがで
きるタイミング再生装置を提供することにある。以下実
施例(、二ついて詳細に説明する。
OBJECTS OF THE INVENTION An object of the present invention is to provide a timing recovery device that eliminates such malfunctions and can recover timing from NIIZ codes with a simpler circuit configuration. Below, two examples will be described in detail.

発明の実施例 第2図は、本発明実施例装置の要部ブUツク図であり、
10はNRZ符号の信号が加わる入力端子。
Embodiment of the invention FIG. 2 is a block diagram of the main parts of an apparatus according to an embodiment of the invention.
10 is an input terminal to which the NRZ code signal is applied.

11.12はアンド回路、13.14は遅延回路、15
はノア回路、16〜18は否定回路、19は出力端子、
20は第1のパルス発生回路、21は第2のパルス発生
回路である。
11.12 is an AND circuit, 13.14 is a delay circuit, 15
is a NOR circuit, 16 to 18 are negative circuits, 19 is an output terminal,
20 is a first pulse generating circuit, and 21 is a second pulse generating circuit.

本実施例のタイミング再生装置は、同図に示すように、
入力信号を一方のへカとするアンド回路11と、アンド
回路11の出力を受信信号の1/2ビツト長だけ遅延す
る遅延回路16と、その出力を反転しアンド回路11の
他方の入力に加える否定回路17とから成る第1のパル
ス発生回路20 、否定回路16で反転された入力信号
を一方のへカとするアンド回路12と、このアンド回路
12の出方を受信信号の1/2ビツト長だけ遅延する遅
延回路14と、その出力を反転してアンド回路12の他
方の人力に加える否定回路18とからなる第2のパルス
発生回路21、並びにアンド回路11 、12の)ア出
力をとるノア回路15を備えている。
As shown in the figure, the timing regeneration device of this embodiment has the following features:
An AND circuit 11 which takes the input signal as one input, a delay circuit 16 which delays the output of the AND circuit 11 by 1/2 bit length of the received signal, and the output is inverted and applied to the other input of the AND circuit 11. a first pulse generating circuit 20 consisting of a NOT circuit 17; an AND circuit 12 which uses the input signal inverted by the NOT circuit 16 as one input; A second pulse generating circuit 21 consisting of a delay circuit 14 that delays by a long time, and a negative circuit 18 that inverts its output and applies it to the other input of the AND circuit 12, as well as the a) outputs of the AND circuits 11 and 12. A NOR circuit 15 is provided.

第6図は第2図示装置を動作させた場合(=おける各部
の信号波形の一例を示す線図であり、以下同図を参照し
て第2図示装置の動作を説明する。
FIG. 6 is a diagram showing an example of signal waveforms at various parts when the second illustrated apparatus is operated. The operation of the second illustrated apparatus will be described below with reference to the same figure.

はじめに人力αが0″であったとすると、このとき遅延
回路13の出力は“0″、否定回路17の出力従ってア
ンド回路11の他方の入力は“1″となっている。この
状態で人力σが1”になると、アンド回路11の出力が
′1”になり、この出力2は遅延回路13により一定時
間遅延され否定回路17で反転されてアンド回路11の
一方の入力に加えられる。このため、アンド回路11の
出力すはO″となり、遅延回路13の入力は再び“O″
となる。従って一定時間遅延の後、再度アンド回路11
の他方の人力が1″になる。このようにして、アント゛
回路11.遅延回路13.否定回路17よりなる帰還ル
ープは、遅延回路13の遅延時間の2倍を周期とする第
1のパルス発生回路20として動作し、この動作は入力
αが“0′になるまで続けられる。
Assuming that the human power α is 0" at the beginning, the output of the delay circuit 13 is "0", and the output of the NOT circuit 17 and therefore the other input of the AND circuit 11 is "1". In this state, the human power σ When becomes 1", the output of the AND circuit 11 becomes 1", and this output 2 is delayed for a certain period of time by the delay circuit 13, inverted by the NOT circuit 17, and added to one input of the AND circuit 11. , the output of the AND circuit 11 becomes "O", and the input of the delay circuit 13 becomes "O" again.
becomes. Therefore, after a certain time delay, the AND circuit 11
In this way, the feedback loop consisting of the antenna circuit 11, the delay circuit 13, and the negative circuit 17 generates the first pulse with a period twice the delay time of the delay circuit 13. It operates as the circuit 20, and this operation continues until the input α becomes "0".

一方、入力αが“1”である間否定回路1Bの出力従′
つ°Cアン1゛回路12の他方の人力はO”であるから
、第2のパルス発生回路24はその77−1パルスを発
生しない。しかし、人力aが“0′になると、否定回路
1Bを通しでアンド回路12の他方の入力が1″となる
ので、第2のパルス発生回路21は先の第1のパルス発
生回路20と全く同様の動作を行なう。なお、第2のパ
ルス発生回路21が動作している間入力aは“O″であ
り、その間第1のパルス発生回路20はパルスを発生し
ない。
On the other hand, while the input α is “1”, the output slave of the NOT circuit 1B is
Since the human power on the other side of the C an1 circuit 12 is O", the second pulse generating circuit 24 does not generate the 77-1 pulse. However, when the human power a becomes "0", the negative circuit 1B Since the other input of the AND circuit 12 becomes 1'' through 21 is operating, the input a is "O", and the first pulse generating circuit 20 does not generate pulses during that time.

第1のパルス発生回路20から得られたパルス出力りと
第2のパルス発生回路21から1冒られたパルス出力C
とはノア回路15に加えられており、タイミングはこの
ノア回路15の出力すの立ち下がりでiひられる。なお
、」1記遅延回路13 、14としては例えばセラミッ
クマイクロチップコンデンサとフェライトコアとを用い
たディレィ・ライン・モジュールと吋ばれる集中定数形
遅延素子が使用でき、遅延時間を可変することができる
ものを使用すれば伝送速度の変更に容易に対処し得るも
のとなる。
Pulse output C obtained from the first pulse generation circuit 20 and pulse output C obtained from the second pulse generation circuit 21
is added to the NOR circuit 15, and the timing is determined by the falling edge of the output of this NOR circuit 15. As the delay circuits 13 and 14, for example, a lumped constant delay element called a delay line module using a ceramic microchip capacitor and a ferrite core can be used, and the delay time can be varied. By using , it becomes possible to easily deal with changes in transmission speed.

第4図は本発明の別の実施例を表す要部ブロック図であ
り、第2図と同一符号は同一部分を示し、41は制御1
菖号入力端子、42は排他的論理和回路、43 、44
は6人力のアンド回路である。受信部等の特性によつ°
Cは、人力信号が歪むとき常に“1”のパルス幅が広が
る方向に歪むようになったり、またその逆に“1”のパ
ルス幅が狭まる方向に歪むようになったりすることがあ
る。例えば第5図(A)に示すようなNRZ符号で、立
ち上がり特性に比べ立ちトがり特性の劣るスイッチング
素子を駆動した場合、スイッチング素子の出力は同図C
B)に示すものとなり、これを閾値5Dで2値化した信
号は同図(C)に示すように“1″のパルス幅が広がっ
てしまう。本実施例はこのような場合に多少の歪があっ
ても正確なタイミング再生が行なわれるようにしたもの
であって、第2図のアンド回路11 、12を5人力の
アンド回路45.44に置き換えて否定回路17の出力
をアンド回路44の入力とするとともに否定回路18の
出力をアンド回路46の入力とし、且つ入力aと制御信
号yとの排他的論理和をとる排他的論理和回路42を設
けて’ifi制御信号ダを1″、“0″に切換えること
に上りへカaを反転し得るようにしたものである。
FIG. 4 is a block diagram of main parts representing another embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and 41 is a control 1
Iris input terminal, 42 is an exclusive OR circuit, 43, 44
is a six-person AND circuit. Depends on the characteristics of the receiver etc.
When the human input signal is distorted, the signal C may become distorted in such a direction that the pulse width of "1" is widened, or conversely, it may become distorted in the direction that the pulse width of "1" is narrowed. For example, when driving a switching element whose rising characteristic is inferior to its rising characteristic with an NRZ code as shown in Fig. 5 (A), the output of the switching element is as shown in Fig. 5(A).
The signal obtained by binarizing this signal using a threshold value of 5D has a widened pulse width of "1" as shown in FIG. 3(C). In this embodiment, accurate timing reproduction is performed even if there is some distortion in such a case, and the AND circuits 11 and 12 in FIG. 2 are replaced with AND circuits 45 and 44 operated by five people. An exclusive OR circuit 42 which replaces the output of the NOT circuit 17 with the input of the AND circuit 44 and the output of the NOT circuit 18 with the input of the AND circuit 46, and calculates the exclusive OR of the input a and the control signal y. is provided so that the upward direction can be reversed by switching the ``ifi'' control signal ``da'' to ``1'' and ``0''.

例えば、入力αが°1″のパルス幅が常に狭まる傾向の
歪を受ける場合には、制御信号yを0“とする。第6図
はこのときの第4図示装置各部の信号波形の一例を示す
線図であり、人力aの111ffのパルス幅が狭まって
も、第2のパ/1.ス発生回路21のアンド回路44は
9L1のパルス発生回路2oの否定回路17の出力が“
1″にならないと“1″にならないので、第2のパルス
発生回路21の出力パルス61 、62は人力aの正規
の波形(点線で示す)に同期しで発生する。
For example, if the input α is subject to distortion in which the pulse width of 1" always tends to narrow, the control signal y is set to 0". FIG. 6 is a diagram showing an example of the signal waveform of each part of the device shown in FIG. The AND circuit 44 of the pulse generating circuit 21 outputs the output of the NOT circuit 17 of the pulse generating circuit 2o of 9L1.
Since the output pulses 61 and 62 of the second pulse generating circuit 21 are generated in synchronization with the normal waveform (indicated by the dotted line) of the human power a, the output pulses 61 and 62 of the second pulse generation circuit 21 are generated in synchronization with the normal waveform (shown by the dotted line) of the human power a.

また、人力aが“1″のパルス幅が常に広がる傾向の歪
を受ける場合には、制i+++ +;r号1を°゛1″
にして入力aを反転して処理ずれば良い。第7図はこの
ときの第4図示装置各部の(イ号彼形の一例を示す線図
であり、人力σの“1”のパルス幅が広がっても人力α
を反転して置けば、アンド回路4ろの出力は人力aがO
”になっても否定回路1Bの出刃が1”tユなるまで“
1″(=ならないので、第1のノーレス発生回路20の
出カックルスフ0,7i&1八ブjαの正規の波形(点
線で示す)に同期して発生する。
In addition, when the human power a is subjected to distortion in which the pulse width of "1" always tends to widen, the control i +++ +; r number 1 is changed to °゛1''
It is only necessary to invert the input a and shift the processing. FIG. 7 is a diagram showing an example of the (I) shape of each part of the device shown in FIG. 4 at this time.
By inverting , the output of AND circuit 4 is as follows:
Even if it becomes ``, the blade of negative circuit 1B becomes 1''t.''
1'' (= does not hold), the signal is generated in synchronization with the normal waveform (shown by the dotted line) of the output cackle waves 0, 7i & 18b jα of the first no-response generating circuit 20.

ナオ、人力aが、1nのA)レス幅が常(二狭まる傾向
の歪を受けるシステムでは、排他的論理和回路42を省
略しても良い。また、入力aの歪力−。
In a system where the human power a is subject to distortion where the response width always tends to narrow (A), the exclusive OR circuit 42 may be omitted.Also, the distortion force of the input a.

“1″のパルス幅を狭める方向と広カーる方1司の双方
に現れる場合でも、第4図の制御信号ダを°゛0′にし
た叩ち排他的論理和回路42を省略した構lj父の各部
の信号波形は、例えば第8図(二示すよう(二、ノア回
路15の出力dは歪の影響を受(すず人ブ〕αの正規の
波形に正しく同期して発生する。ただ、“1″のパルス
幅が広がったところで11、アンド回路43 、44か
ら通常の幅より狭b)ノζルヌ80 、81力−発生し
、これが合成されるので、ノア回路15の出力d(二ひ
げ状の微小な信号成分82力玉現れることがある。この
ような成分82力−不65合であるときkよ、ノア回路
15の後段にそのような成分82を除去するフィルタを
設ければ良い。このとき、ノア回路15の出力dの立ち
下がりが人力αのビットのr4コい。
Even if the pulse width of "1" appears both in the narrowing direction and in the widening direction, the configuration in which the exclusive OR circuit 42 with the control signal DA set to 0' in FIG. 4 is omitted is used. The signal waveforms of each part of the father are generated in correct synchronization with the normal waveform of α, which is affected by distortion, as shown in FIG. , 11, when the pulse width of "1" is widened, the AND circuits 43 and 44 generate a force that is narrower than the normal width b) Two-whisker-like minute signal components 82 may appear.When such a component 82 is negative, a filter to remove such components 82 should be provided at the subsequent stage of the NOR circuit 15. At this time, the fall of the output d of the NOR circuit 15 is equal to r4 of the bit of the human power α.

発明の詳細 な説明したよう(二、本発明(二よれば、2個の遅延回
路と僅かなゲートだけの構成でNRZ符号から高精度に
タイミング信号を抽出することができ、然もノイズに弱
いワンショットマルチバイブレータを使用していないの
で、人力信号にひげ状のノイズが含まれていてもそれに
よって誤動作する虞は皆無となる。q′ケ(二、第1の
否定回路の出刃を第2のアンド回路に帰還し且つ第2の
否定回路の出力を第1のアンド回路に帰還する構成(二
よれば、人力に多少の歪があってもその影響を受けずに
タイミング再生できる利点がある。
As explained in detail about the invention (2. According to the present invention (2), it is possible to extract a timing signal from an NRZ code with high precision using only two delay circuits and a small number of gates, and it is susceptible to noise. Since a one-shot multivibrator is not used, there is no risk of malfunction even if the human signal contains whisker-like noise. A configuration in which the output of the second negative circuit is fed back to the AND circuit, and the output of the second negative circuit is fed back to the first AND circuit (According to 2, there is an advantage that the timing can be reproduced without being affected by some distortion due to human input. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のタイミング再生装置のブロック図、第2
図、第4図は本発明のそれぞれ異なる実施例を表す要部
ブロックタ1.第3図は第2図示装置の動作説明用線図
、第5図〜第8図は第4図示装置の動作説明用線図であ
る。 10はNRZ符号の入力1言号が加わる入力端子、11
.12はアンド回路、15 、14は遅延回路、15は
ノア回路、16〜18は否定回路、19は出力端子、2
0は第1のパルス発生回路、21は第2のノくレス発生
回路、41は制御信号入力端子、42は排他的論理和回
路、43.44は6人力のアンド回路である。 特許出願人   富士電機製造株式会社(外1名〕
Figure 1 is a block diagram of a conventional timing regeneration device;
Figures 1 and 4 are main block diagrams showing different embodiments of the present invention. FIG. 3 is a diagram for explaining the operation of the second illustrated device, and FIGS. 5 to 8 are diagrams for explaining the operation of the fourth illustrated device. 10 is an input terminal to which one input word of the NRZ code is added; 11
.. 12 is an AND circuit, 15 and 14 are delay circuits, 15 is a NOR circuit, 16 to 18 are NOT circuits, 19 is an output terminal, 2
0 is a first pulse generation circuit, 21 is a second pulse generation circuit, 41 is a control signal input terminal, 42 is an exclusive OR circuit, and 43 and 44 are six-manufactured AND circuits. Patent applicant: Fuji Electric Manufacturing Co., Ltd. (1 other person)

Claims (1)

【特許請求の範囲】[Claims] (1)  NRZ符号の入力(4号からタイミングを再
生する方式にt6いて、1¥IJ記人力信号が第1の入
力端子に加わる第1のアンド回路と該アンド回路出力を
所定時間遅延する第1の遅延回路と該遅延回路出力を反
転して前記第1のアンド回路の第2の入力端fに加える
第1の否定回路とから成る第1のパルス発生回路、前記
人力信号の反転信号が第1の入力端子に加わる第2のア
ンド回路と該アンド回路出力を所定時間遅延する第2の
遅延回路と該遅延回路出力を反転して前記第2のアンド
回路の第2の入力端トに加える第2の否定回路とから成
る第2のパルス発生回路。 該第2及び前記第1のパルス発生回路の出力を合成して
ターf ミンク13号を出力するゲートを具備したこと
を!特徴とするタイミング再生装置。 (’l)  NRZ符号の入力信号からタイミングを再
生する方式において、がJ組人力信号が第1の入力端子
に加わる第1のアンド回路と該アンド回路出力を所定時
間遅延する第1の遅延回路と該遅延回路出力を反転して
前記第1のアンド回路の第2の入力端子に加える第1の
否定回路とから成7..)第1のパルス発生回路、前記
人力信号の反転信号が第1の入力端子に加わる第2のア
ンド回路と該アンド回路出力を所定時間遅延する第2の
古、6l−t4回路と該遅延回路出力社′反転しCMi
l記第2のアンド回路の第2の人力η;1.1子に加え
る第2の・−r足回路とから成る第2のバノトス光生回
路、該第2及び前g122’B1のパルス発生回路の出
力を合成してダイミングfrj号を出力−(−るゲート
を備え、前記第1の否定回路の14i力を前記’)L 
2のアンド回路の第5の人力0iii子に人力し、I−
1つ前記第2の占定回路の出力を前記Wl’l 1のア
〕・・ド回路の第6の人力ailW子に人力する構成と
したことを特徴とするタイミング再生装置。 (51NRZ符号の入力信号からタイミングを再生する
方式において、nfS記人力信吋を反転する手段と、該
反転入力信号が第1の入力端子に加わる第1のアンド回
路と該アンド回路出力を所定時間遅延する第1の遅延回
路と該遅延回路出力を反転して前記第1のアンド回路の
第2の入力端子に加える第1の否定回路とから成る第1
のパルス発生回路、前記反転入力信号を更に反転した信
号が第1の入力端子に加わる第2のアンド回路と該アン
ド回路出力を所定時間遅延する第2の遅延回路と該遅延
回路出力を反転して前記$2のアンド回路の第2の入力
端子に加える第2の否定回路とから成る第2のパルス発
生回路、該第2及び前記第1のパルス発生回路の出力を
合成してタイミング信号を出力するゲートを備え、前記
第1の否定回路の出力を前記第2のアンド回路の第6の
入力端子に入力し、且つ前記第2の否定回路の出力を前
記第1のアンド回路の第3の入力端子に入力する構成と
したことを特徴とするタイミング再生装置。
(1) Input of NRZ code (with t6 in the method of regenerating the timing from No. 4, a first AND circuit to which the 1\IJ input signal is applied to the first input terminal and a second circuit that delays the output of the AND circuit by a predetermined time) a first pulse generating circuit comprising a first delay circuit and a first negative circuit which inverts the output of the delay circuit and applies it to a second input terminal f of the first AND circuit; a second AND circuit that is applied to the first input terminal; a second delay circuit that delays the output of the AND circuit for a predetermined time; and a second delay circuit that inverts the output of the delay circuit and connects it to the second input terminal of the second AND circuit. a second pulse generating circuit comprising a second inverting circuit and a second negative circuit; a gate for combining the outputs of the second pulse generating circuit and the first pulse generating circuit and outputting term f minc No. 13; ('l) In a method of reproducing timing from an input signal of an NRZ code, a first AND circuit to which a J group human input signal is applied to a first input terminal and the output of the AND circuit are delayed by a predetermined time. 7.) a first pulse generating circuit comprising a first delay circuit and a first NOT circuit which inverts the output of the delay circuit and applies it to the second input terminal of the first AND circuit; a second AND circuit whose inverted signal is applied to the first input terminal; a second AND circuit which delays the output of the AND circuit by a predetermined time; and a second AND circuit which delays the output of the AND circuit by a predetermined time;
The second human power η of the second AND circuit; 1. The second Banotos light-generating circuit consisting of the second -r foot circuit added to the first child, and the second and previous g122'B1 pulse generation circuits. The outputs of the first negative circuit are combined to output the dimming frj signal -(-, and the 14i power of the first negative circuit is expressed as the ')L
2 of the AND circuit, input the 5th input 0iii, and
1. A timing reproducing device characterized in that the output of the second occupancy circuit is manually inputted to the sixth manually-powered ailW child of the Wl'l1 add circuit. (In a method for regenerating timing from an input signal of a 51NRZ code, a means for inverting the nfS signal, a first AND circuit to which the inverted input signal is applied to a first input terminal, and an output of the AND circuit for a predetermined period of time. a first delay circuit that delays the delay; and a first NOT circuit that inverts the output of the delay circuit and applies it to the second input terminal of the first AND circuit.
a second AND circuit which applies a signal obtained by further inverting the inverted input signal to a first input terminal; a second delay circuit which delays the output of the AND circuit for a predetermined time; and a second delay circuit which inverts the output of the delay circuit. and a second NOT circuit which is applied to the second input terminal of the $2 AND circuit, and the outputs of the second and first pulse generating circuits are combined to generate a timing signal. The output of the first NOT circuit is input to the sixth input terminal of the second AND circuit, and the output of the second NOT circuit is input to the third input terminal of the first AND circuit. What is claimed is: 1. A timing reproducing device characterized by having a configuration in which input is input to an input terminal of the timing reproducing device.
JP57165359A 1982-09-22 1982-09-22 Timing reproducer Granted JPS5954344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165359A JPS5954344A (en) 1982-09-22 1982-09-22 Timing reproducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165359A JPS5954344A (en) 1982-09-22 1982-09-22 Timing reproducer

Publications (2)

Publication Number Publication Date
JPS5954344A true JPS5954344A (en) 1984-03-29
JPH0328862B2 JPH0328862B2 (en) 1991-04-22

Family

ID=15810865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165359A Granted JPS5954344A (en) 1982-09-22 1982-09-22 Timing reproducer

Country Status (1)

Country Link
JP (1) JPS5954344A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0569179A2 (en) * 1992-05-08 1993-11-10 AT&T Corp. A method and apparatus for clock recovery
WO1996005672A1 (en) * 1994-08-08 1996-02-22 Siemens Aktiengesellschaft Integrable clock recovery circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0569179A2 (en) * 1992-05-08 1993-11-10 AT&T Corp. A method and apparatus for clock recovery
EP0569179A3 (en) * 1992-05-08 1994-06-01 American Telephone & Telegraph A method and apparatus for clock recovery
WO1996005672A1 (en) * 1994-08-08 1996-02-22 Siemens Aktiengesellschaft Integrable clock recovery circuit

Also Published As

Publication number Publication date
JPH0328862B2 (en) 1991-04-22

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