JPH0340463A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an isolating region where a narrow channel effect is never induced so as to enable an LSI to be highly integrated by a method wherein a region which is 5X10<15>-1X10<17>cm<-3> in impurity concentration at a depth of 1.0mum from its interface with an element insulating isolating film is provided. CONSTITUTION:A P well 2 and an N well 3 are provided onto a P-type substrate 9, and an SiO2 film 18 and an Si3N4 film 19 are laid thereon. A resist mask 20 is provided and the Si3N4 film 19 on a channel stopper forming region is removed. B ions of P-type impurity are implanted 21 through an opening via the SiO2 film 18. At this point, ions are implanted so as to make a region have a prescribed impurity concentration later at a prescribed depth from its interface with an SiO2 layer 23 by controlling the implanting energy of ion. Then, a resist makes 22 is provided, the Si3N4 film 19 is removed again, and the resist mask 22 is removed. The isolating region 23 is oxidized. In an after process, an N-type and a P-layer MOSFET are formed. At this time, as a layer 21 is provided, a narrow channel effect is not induced and consequently a memory cell can be reduced in size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same suitable for a memory that needs to be highly integrated.

[Conventional technology]

Between NMOSFETs used in conventional LSI or N
Regarding the isolation method between MOSFET and PMO5FET, see Nikkei Electronics Special Issue Micro Devices Special Issue 1.5-1μm era VLSILSI manufacturing technology-72-
LOGO3 (LocalOxida)
tion of 5 ilicon) method.

When separated simply by the LOCO5 method, Si
An inversion layer is generated at the ng-8i interface.

In order to prevent this inversion layer, boron ions are implanted into the channel stopper region before LOGOS oxidation to prevent inversion at the 5iOz-Si interface.

[Problem to be solved by the invention]

In the prior art described above, the P-type impurity (generally boron is used) implanted as a channel stopper diffuses during selective oxidation, increasing the impurity concentration in the active region (ie, gate region) of the NMOSFET. As a result, the threshold voltage VT increases in devices with narrow gate widths, such as NMOSFETs used in memory cells.
A so-called narrow channel effect occurs.

When conventional technology is used, such narrow channel effects begin to occur with gate widths of 2.0 μm or less, and with gate widths of 1.5 μm or less,
m or less, the threshold voltage Vr increases twice,
This is a significant obstacle to reducing the area of memory cells.

The present invention is intended to realize a semiconductor device having an isolation region in which no narrow channel effect occurs, in order to achieve high integration of LSI (miniaturization of memory cells).

[Means to solve the problem]

In order to achieve the above object, the present invention includes a plurality of semiconductor elements formed on a semiconductor substrate, and an isolation region that separates the semiconductor elements, and an insulating film is formed on the surface of the isolation region. In the isolation region and at a depth of 1.0 .mu.m from the interface with the insulating film, the impurity concentration is 5.times.10.sup.12I to 1.times.10.sup.17.times.3.

[Effect]

First, the mechanism by which the narrow channel effect occurs will be explained in detail. The explanation uses the separation between an NMOSFET and a PMO5FET as an example. Currently, as shown in Figure 2(a),
Since the formation of the P-well and N-well uses self-alignment technology, the oxide film 12 of the P-well is thinned, and the oxide film 13 of the N-well is thinned.
P-well ion implantation 11 is performed with the P-well ion implanted in a thick state, and after heat treatment, SiaN 4m is formed, and resist and 5iaNil are formed in the active region (region where elements are formed).
In this state, boron is not implanted into the N-well region, but only into the channel stopper region of the P-well. I will make it possible for you to do so.

In order to satisfy this condition, it is necessary to lower the boron implantation energy. For this purpose, boron is implanted into a thin region of the Si surface. After this, the resist was removed and 5iaN
Selective oxidation is performed using the a film as a mask to form isolation regions. At this time, since boron has the property of being easily incorporated into the oxide film, boron is incorporated into the oxide film and the Si-
The boron concentration at the oxide film interface decreases, and on the other hand, as a channel stopper, S
The concentration at the i-oxide film interface needs to be 1×10 18 or more. Therefore, the amount of boron implanted as an impurity for the channel stopper is determined in consideration of the amount incorporated into the oxide film. That is, it is necessary to implant a large amount of boron. Therefore, as shown in Fig. 1(b), although the boron concentration at the Si-oxide film interface is IlX101BQ'-'', the depth is 0.6μ.
The impurity distribution is shown in the depth direction, but the distribution is similar in the lateral direction, and the impurity concentration in the active region is 1×10.
It can be seen that the value is 170″″3 or more. Due to this mechanism, NMOS with narrow gate width can be fabricated using conventional formation methods.
NMOSF with high threshold voltage VT when fabricating FET
It becomes ET.

In general, in memory devices manufactured using sub-μm technology, the width of the MOSFET used in the memory cell is 1.0
It is around μm or less. Therefore, the concentration of the active region becomes 1×10"am""3 or more.

The impurity concentration in the active region is 1×1017c! In the case of 1""3, the threshold voltage is 1 even if the gate oxide film thickness is 100.
．． 08V, so speeding up cannot be measured. Including reliability, since the gate oxide film that does not generate tunnel current is 80 m, the impurity in the active region must be 1 x 10170 m. Also, impurities are 5X 1011
If sam"" is less than 3, punch-through will occur in the isolation region. Therefore, if the impurity concentration is 5 x 10 L15 arm-'' or more at a depth of 1 μm (the distribution is similar to that in the horizontal row),
It can be seen that it must be less than or equal to "cs-".

In the present invention, the narrow channel NMO8F, which does not cause the narrow channel effect, is based on the narrow channel mechanism.
It is characterized by having ET. In other words, even after selective oxidation, the boron concentration (
The structure is characterized in that the amount of P-type impurity in the shell is less than lX 1017aa-' within a depth of 1 μm from at least the interface. The formation method is not to implant P-type impurities near the Si surface and then perform selective oxidation as in the conventional method, but to selectively oxidize the Si
After p-type impurities are implanted in advance at a depth where the 0z-Si interface will be formed, selective oxidation is performed. Then, Figure 1 (b)
), the amount of P-type impurity incorporated into the oxide film is reduced, and the amount of P-type impurity implanted is also reduced.As a result, the impurity concentration that spreads laterally due to diffusion is reduced, and the narrow channel effect occurs. As described above, by using the present invention, it is possible to form an NMOSFET having a narrow channel width without the narrow channel effect, and it becomes possible to realize a highly integrated LSI.

〔Example〕

[Example 1] As shown in FIG. 2(a), P-well and N-well regions are formed on a P-substrate 9 by a method similar to the conventional method. after that,
After heat treatment and removal of the 5ift films of 12 and 13, 5iO
FIG. 3(a) showing the formation of the Z film 18 and the Si3N4 film 19
, then use photolithography technique and dry etching to form the channel stopper.
After removing the isN4 film 19, ions of P-type impurity are implanted 21, and at this time, this impurity is used as the 5iO that will be formed later.
FIG. 3(a) adjusts the implantation energy so that it is implanted into the interface of x-3i (in this example, the implantation energy of boron ion species is 100 kaV). Next, as shown in FIG. 3(b), the area where the PMOSFET is formed and the P-well area are covered with photoresist, and the
Dry etching.

Thereafter, after removing the resist, the isolation region 23 is selectively oxidized using the 5iaN4 film as a mask (FIG. 3(C)). After that, the NMOSFET and PM
By forming an OSFET and forming the state shown in FIG. 1(a), an element can be formed.

[Example 2] In the conventional method, boron was used as the P-type impurity in FIG. 2(b). However, in FIG. 2(b), potassium or indium is used as the P-type impurity since it is incorporated into the oxide film. The subsequent manufacturing method of the device is the same as the conventional method, and the device shown in FIG. 1(a) is manufactured. By doing so, impurities are not incorporated into the oxide film at the stage of selective oxidation but are pushed out to the Si width, so that the distribution can be similar to the distribution of the present invention shown in FIG. 1(b, ).

[Example 3] In Examples 1 and 2, the high concentration P region was formed only under the selective oxide film, but as shown in FIG. It may be formed in a region. However, in this case, the substrate bias coefficient of the NMOSFET becomes large.

[Example 4] In Example 1, as shown in FIG. 3(b), the resist 20 was removed only in the portion that would become the channel stopper region, and the 5iaN4 film 19 in the same area was removed. And further PMO
Although the 5iaNa film 19 in the separation region No. 8 was removed, due to the alignment margin of photolithography in this step, the previous 5i Na film 19 was removed.
In the region where the aNa film 19 has been removed, there is a region to be removed again, and in this region where the removal process is applied again, the 5iOz film 18 is removed and even the Si surface becomes rough. In order to avoid this drawback, the present invention could be implemented in the following manner.

As shown in FIG. 2(a), a P well 2 is placed on a P substrate 9,
After forming the N well 3 and performing heat treatment, the 5i02 film 12,1
Remove 3. Thereafter, a Sing film 18.
5iaNalB119.5ins membrane (e.g. HLDli
l) Sequentially forming layers 25@ (The original 25 of the SxOs+ film 25 should have a thickness of 1500 Å or more in order to serve as a mask for B ion implantation later) After this, as shown in FIG. 6(a), photolithography is performed. Technology nN05FET, p
SingL in the isolation region leaving the active region of MOsFET
6 Next, the film 25.5iaNa film 19 is removed (Fig.
After applying the resist 15 as shown in b), the resist 15 in the region where the channel stopper is to be formed is removed. Note that the region where the resist is removed may be expanded to the nMOSFET, that is, the P well. In this state, B ions are implanted into a predetermined region 21, and then conventional CMO3FII
If it is manufactured by an IT manufacturing process, it can be made as shown in FIG. 1(a).

Example 1. Although a CMOSFET is used as an example in both Examples 2 and 3, it is clear that the present invention is applicable to BiCMO5, NMO5FETs, or SRAMs, DRAMs, lodges, etc. using these.

〔Effect of the invention〕

In the present invention, even if the gate width is narrowed, the impurity concentration in the active region does not increase. Therefore, as shown in FIG. In contrast to the sudden rise in threshold voltage, in the case of the present invention, there is no sudden rise in threshold voltage even if the gate width is narrowed. The width can be reduced, and a highly integrated semiconductor memory device can be realized.

It is clear that this effect is produced similarly for the entire semiconductor LSI.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view of a device according to an embodiment of the present invention.
Figure (b) is a distribution diagram of the impurity concentration on line AA' in Figure 1 (a), Figures 2 (a) and 2 (b) are diagrams showing the conventional manufacturing method, and Figure 3 3(a) to 3(b) are diagrams showing the manufacturing method of the present invention, FIG. 4 is a sectional view of a device according to another embodiment of the present invention, and FIG. 5 is a diagram showing the gate width and threshold voltage. FIG. 6, which is a diagram showing the relationship, is a sectional view of the device for explaining Embodiment 4 of the present invention. 1...Channel stopper, 2...P well, 3...
・N well, 4...N ten areas, 5...P◆territory area 6
... Polycrystalline Si gate, 7... Electrode wiring, 8...
S i Ox film = 9° 10...P substrate, 11...P
Type ion implantation, 12... P-well oxide film, 13...
・N-well oxide film, 14...S iaNa[Is
(, 15... Resist, 16... Channel stopper (P type) ion implantation, 17... Channel stopper implantation region, 18... 5 iOz film, 19... 5iaN film. 20. ...Resist, 21...Channel stopper region, 22...Resist, 23...Isolation region, Schematic diagram (d-) ΔA' Bulk diagram (b) Hi'! of sLot-s,, lq et al. (, gm) 2nd year high school figure (
a,) 2nd grade (b) 3rd grade high school (former 3rd day (b) 3rd grade (0 4th day high school 5th day - TOT crystal (P-Tn) Procedural amendment (method) % formula % Person who corrects semiconductor devices and their manufacturing methods 'I'-1'I Tono Seki 1i #Mi'rrlxlf
i person R+8+ +51o+ K formula'j +t 8 factory agent? ti Field for brief description of drawings in the correct subject specification

Claims (1)

[Claims] 1. A plurality of semiconductor elements formed on a semiconductor substrate, and an isolation region that separates the semiconductor elements, and an insulating film is formed on the surface of the isolation region. 1.0 within and from the interface with the insulating film
A semiconductor device characterized in that the impurity concentration is 5×10^1^5 to 1×10^1^7 cm^-^3 at a depth of μm. 2. The semiconductor device according to claim 1, wherein the isolation region is a P-type well. 3. Between multiple NMOSFETs formed on a semiconductor substrate,
and 1.0 μm from the insulating film-semiconductor interface in the P-well isolation region between NMOSFET and PMOSFET.
P-type impurity concentration in the semiconductor region at a depth of 5×10^1^5
1 x 10^1^7 cm^-^3. 4. Adding P-type impurities to a thickness of 0.1 μm to 0.6 μm in the semiconductor serving as the isolation region of the P well in Claim 3
1. A method for manufacturing a semiconductor device, which comprises selectively oxidizing an isolation region after ion implantation under conditions that achieve a range of . 5. A method for manufacturing a semiconductor device, characterized in that the P-type impurity in claim 4 is Ga or In. 6. A memory device characterized by integrating the semiconductor device according to claim 3. 7. A semiconductor device comprising an NMOSFET with a gate width of 1.5 μm or less and a threshold voltage in the range of 0 to 1.0V. 8. Gate width is 1.5 μm or less and threshold voltage is 0 to 1
．． 0V (7) NMOSFET and NMOSFE with a gate width of 1.5 μm or more and a threshold voltage of -1.0 to 1.0V
A semiconductor device comprising: T. 9. A semiconductor characterized in that a selective oxide film is formed in a P-well region in a semiconductor substrate in which an NMOSFET is formed and a selective oxide film is formed in the semiconductor at a higher concentration than in other regions. Device.