JPH034039Y2 - - Google Patents
Info
- Publication number
- JPH034039Y2 JPH034039Y2 JP12332483U JP12332483U JPH034039Y2 JP H034039 Y2 JPH034039 Y2 JP H034039Y2 JP 12332483 U JP12332483 U JP 12332483U JP 12332483 U JP12332483 U JP 12332483U JP H034039 Y2 JPH034039 Y2 JP H034039Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat
- chip carrier
- heat diffusion
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 25
- 230000017525 heat dissipation Effects 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12332483U JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12332483U JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6033437U JPS6033437U (ja) | 1985-03-07 |
| JPH034039Y2 true JPH034039Y2 (enEXAMPLES) | 1991-02-01 |
Family
ID=30281557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12332483U Granted JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6033437U (enEXAMPLES) |
-
1983
- 1983-08-10 JP JP12332483U patent/JPS6033437U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6033437U (ja) | 1985-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6188578B1 (en) | Integrated circuit package with multiple heat dissipation paths | |
| JP3281220B2 (ja) | 回路モジュールの冷却装置 | |
| US20030104653A1 (en) | Recessed encapsulated microelectronic devices and methods for formation | |
| JPH1174425A (ja) | フリップチップパッケージ用高性能熱拡散装置 | |
| JPH10247703A (ja) | ボールグリッドアレイパッケージ及びプリントボード | |
| JP3922809B2 (ja) | 半導体装置 | |
| JPH04291750A (ja) | 放熱フィンおよび半導体集積回路装置 | |
| JPH034039Y2 (enEXAMPLES) | ||
| JP3378174B2 (ja) | 高発熱素子の放熱構造 | |
| JPH03214763A (ja) | 半導体集積回路装置のリードフレーム及びこれを用いた半導体集積回路装置 | |
| JPH03174749A (ja) | 半導体装置 | |
| JPH03266456A (ja) | 半導体チップ用放熱部材及び半導体パッケージ | |
| JPH0448740A (ja) | Tab半導体装置 | |
| JPH046860A (ja) | 半導体装置 | |
| JPS6092642A (ja) | 半導体装置の強制冷却装置 | |
| CN100362654C (zh) | 具有散热装置的球栅阵列封装 | |
| JPH0878616A (ja) | マルチチップ・モジュール | |
| JPH0497554A (ja) | 高放熱型半導体パッケージ | |
| JPS63289847A (ja) | Lsiパッケ−ジの放熱構造 | |
| JPH04299849A (ja) | 半導体装置 | |
| JP2007036035A (ja) | 半導体装置 | |
| KR940011796B1 (ko) | 반도체장치 | |
| JPH04124860A (ja) | 半導体パッケージ | |
| JPH0467658A (ja) | 半導体装置 | |
| JPS6228766Y2 (enEXAMPLES) |