JPH0339410B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit consisting of a multi-output NOR circuit, and more particularly to a flip-flop circuit using a multi-output NOR circuit constituted by a non-shushhold logic circuit.

Logic LSI formed by master slicing method
As a basic circuit constituting a master slice LSI (hereinafter referred to as a master slice LSI), there is, for example, a non-shocket logic circuit (hereinafter referred to as an NTL circuit) as shown in FIG.

However, since the conventional NTL circuit has one output (NOR) as shown in the figure, when configuring a flip-flop circuit with clock synchronous set and reset terminals, for example, in the master slice LSI, as shown in Fig. 3, 6 NOR circuits G ₁ ~
It was necessary to create a three-stage circuit using _G6 .

Therefore, the conventional single-output NOR circuit (Figure 1)
Flip-flop circuits using the above have problems in that the number of elements and stages is large, resulting in low packaging density and slow operation speed.

Therefore, the present invention constructs a circuit by configuring a flip-flop circuit using a multi-output NOR circuit that can take out two or more NOR outputs by providing a plurality of emitter followers in the output stage of an NTL circuit. It is an object of the present invention to reduce the number of elements and stages involved in flip-flop circuits, thereby reducing the mounting area of a flip-flop circuit and improving its operating speed.

The present invention will be explained below using the drawings.

First, an example of a NOR circuit constituting the flip-flop circuit of the present invention will be briefly explained.

Figure 2 shows a 3-input, 2-output circuit consisting of an NTL circuit.
A NOR circuit is shown. The collectors and emitters of the three input transistors T _r1 , T _r2 , and T _r3 provided in parallel are connected to each other, and the collectors of the input transistors T _r1 to _{T r3} are connected to the ground point (GND) of the circuit. A resistor _R1 is connected between them. Further, a resistor _R2 is connected between the emitters of the input transistors T _r1 to _{T r3} and the power supply voltage V _EE . The above input transistors T _r1 to T _r3 and resistor R ₁ ,
_R2 constitutes an input stage.

The output stage of the NTL circuit is not particularly limited, but
Consisting of two Emitsuta follower EF1 and EF2,
The potential of the connection node n between the collectors of the input transistors T _r1 to T _r3 and the resistor R ₁ is supplied to the bases of the output transistors T _r4 and T _r5 constituting the emitter followers EF1 and EF2.

The above NTL circuit uses input signals V _io1 to _{V io3} as follows:
When at least one is brought to a high level, the corresponding input transistor is turned on and current flows through resistor _R1 . Then, the potential of the node n falls, the output transistors T _r4 and T _r5 are turned off, and their output levels are both set to low level.

Furthermore, when all input signals V _io1 to V _io3 are set to low level, all input transistors T _r1 to T _r3 are turned off, the potential of node n rises, and output transistors T _r4 and T _r5 are turned on. and their output levels are both set to high level.

In this way, the NTL circuit shown in FIG. 2 is operated as a 3-input, 2-output NOR circuit.

Next, FIG. 4 shows an example of a flip-flop circuit using the above-mentioned NOR circuit (FIG. 2), and shows a clock-synchronized set of circuits in a master slice LSI.
A flip-flop circuit with a reset terminal is shown.

This flip-flop circuit consists of three 3
Input 2 output NOR circuit G ₁₁ , G ₁₂ , G ₁₃ and the next stage 1
2-input 2-output NOR circuit G ₂₁ total 4 NOR circuits
Consists of circuits. The three input terminals of the first NOR circuit _G11 in the first stage receive the data signal D and the clock signal.
CK and a set signal S are supplied. The input terminal of the second NOR circuit _G12 in the first stage is
A data signal D, a set signal S, and a feedback signal of an output Q are supplied. In addition, the input terminal of the third NOR circuit _G13 in the first stage is connected to a clock signal.
CK, a set signal S, and a feedback signal of the output Q are supplied.

Then, by bundling the wiring connected to one output terminal of these three two-output NOR circuits G ₁₁ to _{G 13} in the first stage, the NOR circuits G ₁₁ to G 13 are connected to one output terminal.
The output of _G13 is wired ORed and used as the output of the flip-flop circuit.

In addition, the wires connected to the other output terminals of NOR circuits G ₁₁ to _{G 13} are similarly bundled into one wire, so that they are wired ORed and connected to the next stage NOR circuit G ₂₁
is supplied to the input terminal of This latter NOR
A select signal R is supplied to the other input terminal of the circuit _G21 .

The output Q of the flip-flop circuit is taken out from one output terminal of the above two-output NOR circuit _G21 ,
Also, from the other output terminal, the first stage NOR mentioned above is connected.
Feedback signals to circuits G ₁₂ and G ₁₃ are taken out.

Note that the output stages of the NOR circuits G ₁₁ to _{G 13} are composed of two emitter followers with low output impedance, so as mentioned above, each
Bundle and wire the outputs of NOR circuits G ₁₁ to _{G 13}
It is possible to take OR.

In the flip-flop circuit of the above embodiment, the output signal Q is changed to a high level "1" or a low level "0" in synchronization with the negative edge of the clock CK, depending on the state of the data signal D.

Furthermore, when the reset signal R is set to a high level, the output of the NOR circuit _G21 is set to a low level regardless of the data signal, and the output Q of the flip-flop is set to "0". Then this
NOR circuit G ₁₂ by the output “0” of NOR circuit G ₂₁
Since the output of G13 and _G13 are set to high level, the output of the flip-flop is set to "1" (however, at this time, the set signal S is set to "0").

On the other hand, when the set signal S is set to high level (however, the reset signal R is "0"), the first stage NOR
The outputs of circuits G ₁₁ to _{G 13} are all set to low level.
Therefore, the output of the flip-flop is set to "0", the output of the NOR circuit _G21 is set to high level, and the output Q of the flip-flop is set to "1".

In the flip-flop circuit of the above embodiment, a signal from an output terminal separate from the output terminal of the NOR circuit G ₂₁ from which the output Q is taken out is transmitted to the NOR circuit G ₁₂ ,
Since it is fed back to _G13 , even if a relatively long wire is connected to the output terminal Q of the flip-flop and the load on NOR circuit _G21 due to stray capacitance becomes large, it is fed back to NOR circuits _G12 and _G13 . The signal is not affected and changes are not delayed. Therefore, the output of the flip-flop circuit is not affected by the load on the output Q side.

In addition, the output of the flip-flop is formed by wired OR of the signals taken out from output terminals that are separate from the output terminals of the first-stage NOR circuits _{G 11 to G 13} that take out the signals that form the input signals of the NOR circuit G 21. Therefore, even if the load on the wiring connected to the output terminal is relatively large, the change in the signal at the output Q will not be delayed.

Therefore, the flip-flop circuit of the above embodiment is most suitable for a flip-flop circuit formed on a master slice LSI in which the length of the wiring on the output side is often relatively long.

In order to prevent the other output signal from being affected by the load due to the length of the wiring on the output side as described above, NOR circuits _G5 and _G6 are provided in the circuit shown in FIG.

As can be seen by comparing Figures 3 and 4, when constructing a flip-flop circuit with the same function, the flip-flop shown in Figure 3, which consists of a 1-output NOR circuit, uses 6 NOR circuits and 3
It needs to be structured in stages. On the other hand, 2 outputs
The flip-flop circuit of the present invention, which is composed of a NOR circuit, may be configured in two stages using four NOR circuits.

Therefore, the flip-flop circuit of the present invention is
The number of elements that make up the circuit is small, which improves packaging density, and because the number of stages is small, each
Although the delay time in the NOR circuit is the same, the delay time of the entire circuit is shortened, and the operation speed is increased.
Moreover, since each multi-output NOR circuit is composed of an NTL circuit that can operate at high speed, LSI
The overall speed can be increased.

In the above embodiment, a clock-synchronous type flip-flop circuit with set and reset terminals was explained as an example, but the present invention is not limited to this, and can be applied to other types of flip-flop circuits. . For example, a simple clock-synchronous flip-flop circuit as shown in FIG. 5 can be constructed using a two-input, two-output NOR circuit. In this circuit as well, consideration is given so that the load on one output side does not affect the output of the other, and the number of elements and stages are reduced compared to one configured with a one-output NOR circuit.

[Brief explanation of the drawing]

Figure 1 shows a conventional 1-output NOR consisting of an NTL circuit.
A circuit diagram showing the circuit, Figure 2, was proposed this time.
A circuit diagram showing an example of a multi-output NOR circuit consisting of an NTL circuit. Figure 3 is a circuit diagram showing an example of a flip-flop circuit using a 1-output NOR circuit.
FIG. 4 is a circuit diagram showing one embodiment of a flip-flop circuit according to the present invention using a multi-output NOR circuit, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. T _r1 , T _r2 , T _r3 ...input transistor, T _r4 , T _r5
...output transistor, EF1, EF2...emitter follower, G ₁₁ , G ₁₂ , G ₁₃ , G ₂₁ ... multi-output NOR
circuit.

Claims (1)

[Claims] 1. An input stage comprising at least one input transistor and forming an output to the collector of the input transistor; and an output transistor having a base connected to the output of the input stage and an emitter connected to a first connection point. and an emitter follower including an output transistor, the base of which is connected to the output of the input stage and the emitter of which is connected to a second connection point;
an input stage including an input transistor and a second input transistor whose base is connected to the second input point and whose collector and emitter are connected in parallel with the collector and emitter of the first input transistor; an emitter follower including an output transistor connected to the collector of the input transistor and whose emitter is connected to a first output point; and an output transistor whose base is connected to the collectors of the first and second input transistors and whose emitter is connected to the second output point. first, second, and third NOR circuits each having at least an emitter follower including an emitter follower, and a first input point of the first NOR circuit and the second NOR circuit is commonly connected and serves as an input terminal for inputting a data signal. The second input point of the first NOR circuit is an input terminal for inputting a clock signal, and the second input point of the second NOR circuit and the third NOR circuit are connected to each other.
A first input point of the circuit is commonly connected to the first connection point, a second input point of the third NOR circuit is an input terminal for inputting a clock signal having a phase opposite to the clock signal, and The first output points of the first to third NOR circuits are commonly connected to serve as the first output terminals of the flip-flop circuit, the second output points of the first to third NOR circuits are commonly connected to the input of the logic circuit, and the second output points of the first to third NOR circuits are commonly connected to the input of the logic circuit. The connection point is the second one of the flip-flop circuit.
A flip-flop circuit characterized by being used as an output terminal.