JPH0352688B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit composed of bipolar transistors, and more particularly to a flip-flop circuit formed by a master slicing method using a non-shocked logic circuit as a basic circuit.

Logic LSI formed by master slicing method
(hereinafter referred to as a master slice LSI), for example, an emitter pull logic circuit (hereinafter referred to as an ECL circuit) as shown in Figure 1, or a non-shock pull logic circuit as shown in Figure 2. logic circuit (hereinafter referred to as NTL circuit)
There is.

The ECL circuit can output OR output and NOR output. On the other hand, since NTL circuits do not have a threshold voltage, they have the advantage of faster operating speed than ECL circuits. However, conventional
As shown in Figure 2, the NTL circuit had only one output (NOR), so it had the disadvantage of having fewer functions than the E and CL circuits.

Accordingly, flip-flop circuits constructed of NTL circuits have increased the number of circuit stages, and have been unable to take full advantage of the NTL circuit's characteristics of high operating speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flip-flop circuit using an NTL circuit that has a small number of circuit stages and is capable of high-speed operation.

The present invention will be explained below based on the drawings.

FIG. 3 shows a diagram for easy understanding of the present invention.
This shows a 3-input, 2-output NOR circuit consisting of an NTL circuit.

3 input transistors in parallel
The collectors and emitters of T _r1 , T _r2 , and T _r3 are connected to each other, and the input transistor
A resistor _R1 is connected between the collectors of T _r1 to T _r3 and the ground point (GND) of the circuit. In addition, the emitters of input transistors T _r1 to T _r3 and the power supply voltage V _EE
A resistor _R2 is connected between. The input transistors T _r1 to _{T r3} and the resistors R ₁ and R ₂ constitute an input stage. The output stage of the NTL circuit is not particularly limited, but includes two emitter follower EFs.
1, EF2, and the input transistor T _r1 ~
The potential of the connection node _n1 between the collector of T _r3 and the resistor R ₁ is supplied to the bases of output transistors T _r4 and T _r5 constituting the emitter followers EF1 and EF2.

The above NTL circuit uses input signals V _io1 to _{V io3} as follows:
When at least one of them is set to high level, the input transistor to which the high level input signal is supplied is turned on, and current flows through resistor _R1 . Then,
Node _n1 is brought to a low level, which causes output transistor T _r4 , which constitutes an emitter follower,
Both outputs are changed to low level through T _r5 .

Further, when the input signals V _io1 to V _io3 are all set to low level, all the input transistors T _r1 to _{T r3} are turned off, and the node n ₁ is set to high level.
Therefore, through the output transistors T _r4 and T _r5 ,
2 outputs are changed to high level.

In this way, the NTL circuit of FIG. 3 is operated as a 3-input, 2-output NOR circuit.

In the multi-output NOR circuit configured as described above, since the output impedance of the emitter followers EF1 and EF2 is low, wired OR can be performed by tying the output lines of the plurality of multi-output NOR circuits together.

The clock-synchronized set/reset flip-flop circuit of the embodiment shown in FIG. 5 is composed of a combination of multi-output NOR circuits as described above. That is, the flip-flop circuit is composed of first to fourth NOR circuits as described below.

The first NOR circuit is located at the upper left corner of the drawing.
It is an input NOR circuit, and receives the data signal D, clock signal, and set signal as its inputs.

The second NOR circuit is a 3-input NOR circuit located at the center left side of the drawing, and inputs the clock signal, the set signal S, and the 2-input NOR circuit (the
4NOR circuit) is used as its input.

The third NOR circuit is located at the bottom left corner of the drawing.
This is an input NOR circuit, and its inputs are the clock signal CK whose phase is opposite to the clock signal, the set signal S, and one of the outputs of the fourth NOR circuit.

The fourth NOR circuit receives at its input the reset signal R and the wired OR output of one of the outputs of the first to third NOR circuits.

The wired OR outputs of the other outputs of the first to third NOR circuits are used as inverted outputs of the flip-flop circuit, and the other output of the fourth NOR circuit is used as the non-inverted output Q of the flip-flop circuit.

As is clear from the comparison with the conventional flip-flop circuit shown in FIG. 4, the flip-flop circuit of the embodiment shown in FIG. 5 has a reduced number of circuit stages and is therefore capable of high-speed operation.

That is, in the case of FIG. 4, as shown in the figure, there are two outputs consisting of three 3-input NOR circuits and one 2-input NOR circuit, as well as a gate circuit with a 1-input configuration to form the output Q. A buffer circuit is provided. In Figure 4, such 2
The two output buffer circuits have three three-input NOR
It acts so as not to affect the so-called internal circuit loop constituted by the circuit and one two-input NOR circuit. This allows good operation of the internal circuit loop regardless of external load capacitance.

However, in the flip-flop circuit of FIG. 4, depending on the settings of the output buffer circuit,
Obviously, the number of circuit stages increases, which becomes an obstacle to high-speed operation of the circuit.

On the other hand, in the case of the embodiment shown in FIG.
By configuring the NOR circuit as a multiple-output type as shown in Figure 3, it is possible to create two Two outputs Q and Q can be obtained.

In the circuit of FIG. 3, as shown by the broken line A, by connecting the output nodes N ₁ and N ₂ of the two emitter followers EF1 and EF2,
The load driving ability of the circuit can be doubled.

In other words, if output nodes _N1 and _N2 are connected by wiring, the output stage (emitter follower)
Since the resistors R ₃ and R ₄ are connected in parallel, the resistance value is changed by half. Therefore, the current I _EF flowing through the output stage is doubled, and the rate at which stray capacitances and the like on the wiring connected to the output side are charged and discharged becomes faster, and the signal load lag is reduced.

As a result, the operating speed of the entire circuit is improved.

In the reference example in Figure 3 above, as an example, 3 inputs 2
Although the output NOR circuit has been described, by changing the number of input transistors, a 2-input or 4-input or more NOR circuit can be configured. Also,
By connecting three or more emitter followers to the input stage node _n1 , it is possible to configure the system so that even more NOR outputs can be taken out, thereby strengthening the logic function. Moreover, even when three or more emitter followers are provided, the load driving ability can be improved by selectively connecting the output nodes of each emitter follower.

In particular, in master slice LSIs, the wiring connecting the output node and the next stage circuit is often relatively long. In such cases,
By forming the basic circuit of the master slice LSI in advance as a multi-output type NTL circuit as shown in FIG. 3, it is possible to strengthen the logic function of each gate circuit. Moreover, in NTL circuits where the wiring on the output side is long, when forming the master slice aluminum wiring, as mentioned above, the output nodes of each emitter follower in the output stage are selectively connected to increase the load driving ability. By increasing it, the load lag can be reduced. This shortens the signal delay time in each gate circuit, improves the operating speed of the entire master slice circuit, and in conjunction with the high-speed operating characteristics of the NTL circuit, makes it possible to realize a high-speed logic LSI. Moreover, according to the circuit of the above embodiment, the operating speed of the circuit can be improved with relatively low power.

As explained above, according to this invention, NTL
Since a flip-flop circuit is constructed from a circuit in which a plurality of emitter followers are provided in the output stage of the circuit, it is possible to obtain a flip-flop circuit that fully takes advantage of the high-speed characteristics characteristic of the NTL circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a known ECL circuit.
Figure 2 is a circuit diagram showing an example of a known NTL circuit.
Figure 3 is a circuit diagram of a multi-output NOR circuit as a reference example.
FIG. 4 is a circuit diagram showing an example of a flip-flop constructed using a conventional single-output NOR circuit, and FIG. 5 is a circuit diagram showing an example of a flip-flop constructed using a multi-output NOR circuit according to an embodiment of the present invention. FIG. T _r1 , T _r2 , T _r3 ...input transistor, T _r4 ,
T _r5 ... Output transistor, EF1, EF2 ... Emitter follower, N ₁ , N ₂ ... Output node.

Claims (1)

[Claims] 1. A plurality of outputs each having an output commonly connected to a first wired-OR connection point and an output commonly connected to a second wired-OR connection point.
a second NOR circuit having at least an input connected to the first wired-OR connection point, an output coupled to a desired input of the plurality of first NOR circuits, and another output. The output is obtained from the second wired-OR connection point and the other output, and each of the first and second NOR circuits includes a plurality of input transistors arranged in parallel with each other.
It consists of an input stage consisting of an NTL circuit, and a plurality of emitter follower circuits including a plurality of output transistors whose bases receive the same potential supplied from this input stage, and a plurality of outputs are formed by the plurality of emitter follower circuits. A flip-flop circuit characterized in that: