JP2856171B2 - Clock distribution circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit, and more particularly to a clock distribution circuit in which clock skew caused by wiring and the like is reduced so that transition edges of clocks are aligned.

[0002]

2. Description of the Related Art In recent years, with the increasing integration and density of semiconductor integrated circuits, D-type flip-flops (hereinafter referred to as "DF /
F "), the scale of a circuit block configured by using a large number of circuits that require input of a clock signal increases, and accordingly, a large number of clocks are generated in synchronization with the input clock signal. The role of the clock distribution circuit has become important.

FIG. 7 shows an example of the configuration of a conventional clock distribution circuit. This conventional clock distribution circuit 10 is called a "tree type" (tree structure type). In the configuration example shown in FIG. 7, one input clock signal (CLK) is converted into 16 output signals (C1 to C1). C16). That is,
One clock signal (CLK) is divided into two (two branches), and each of the two branched signals is sequentially divided into two, and this is repeated to obtain a large number of clock signals. (The configuration of FIG. 7 has four stages).

In the conventional tree-type clock distribution circuit shown in FIG. 7, an inverter is arranged at a branch point to increase the driving capability (drive capability) for the next stage.

Further, in the tree-type clock distribution circuit shown in FIG. 7, wirings from the branch point to the individual inverters are arranged to be equal. Here, tpd from the input terminal CLK to the output nodes C1 to C6 are all equal.

In the configuration shown in FIG.
Nine of the clock signals C1 to C16 distributed to the book are connected to the respective DF / F clock input terminals of the block 0 composed of nine DF / Fs at the next stage.

[0007]

As shown in FIG. 7, the conventional distribution circuit having a tree structure has a maximum of 16 (= 2 ⁴ ) in order to obtain nine necessary clock signals. The clock signal must be distributed, resulting in a useless circuit, an increase in the area occupied by the distribution circuit, and wasteful consumption of power.

[0008] The skew variation is caused by making all wirings from the branch point of the same number of stages to the next stage equal.
Certainly, it is theoretically suppressed, and forcible placement and wiring suppresses a certain degree of variation, but in the actual manufacturing process, variation in the wiring occurs, which causes skew. Is difficult to nullify.

Moreover, the forced placement and wiring are very troublesome operations, require a large number of man-hours, require a certain occupied area, and ultimately reduce the degree of freedom of design and reduce the flexibility. It will not be.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to eliminate useless circuits such as the tree-type structure described above, reduce the circuit area,
It is an object of the present invention to provide a clock distribution circuit which can distribute a required number of clocks while reducing power consumption, and which is flexible in arrangement and wiring.

[0011]

To achieve the above object, according to an aspect of, the clock distributing circuit of the present invention is to distribute one of the clock signal inputted, double that require a clock signal input
A clock distributing circuit for supplying to a circuit having a first level shift circuit to output to the line by a clock signal the input to the small amplitude, parallel to each other against the said line
A plurality of second level shift circuit that will be connected to a column form,
Wherein the plurality of second level shift circuits are respectively
Output from the first level shift circuit to the line.
Returning the input small-amplitude clock signal to the original amplitude,
The clock signal returned to the original amplitude is referred to as the clock signal.
Output as a clock signal to circuits that require input.
That, characterized in that.

In the present invention, preferably, the first
Means for raising the potential of the line to a power supply potential after the potential of the line reaches a predetermined precharge level, and the threshold voltage of a transistor constituting the second level shift circuit is The precharge level is set higher than the precharge level.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a clock distribution circuit according to an embodiment of the present invention.

Referring to FIG. 1, in the embodiment of the present invention, an input clock signal CLK is input to a first level shift circuit H1, and an output of the first level shift circuit H1 is connected to a line L. A plurality of second level shift circuits S1, S2, S connected in parallel to each other through a wiring including
3, ... are input.

Second level shift circuits S1, S2, S
3,... Are provided in the same number as the required number of clocks.
Of the level shift circuits S1, S2, S3,... Are supplied to a circuit block 20 that requires the input of a clock signal.

In the embodiment of the present invention, as in the prior art shown in FIG. 7, when distributing to nine clocks, the line L is provided with nine second level shift circuits S
1, S2, S3, S4,..., S9 are connected.

The operating principle of the embodiment of the present invention is as follows.
The input clock signal having a large amplitude is operated by the first level shift circuit H1 as if it were made to have a small amplitude, and propagated through the line L with skew reduction and high speed.
It is distributed by the number of clocks. The divided signals are respectively supplied to the second level shift circuits S1,
Are converted to the original large amplitude by S2, S3,...

Next, as an embodiment of the present invention, the first and second level shifts H1, S1, S2, S3,.
Will be described in detail.

FIG. 2 is a block diagram showing an example of the configuration of the first level shift circuit H1 shown in FIG. Referring to FIG. 2, clock signal CLK is input to precharge circuit 3 and delay circuit 5 via inverter 1. The output of the precharge circuit 3 is connected to a line L, and the line L is connected to a power supply line VCC via a P-type MOS transistor 7 functioning as a switch.
Output is connected.

FIG. 3 is a diagram showing an example of the configuration of the delay circuit 5 in the first level shift circuit H1 shown in FIG. An even number of inverters can be connected between the node (input terminal) N3 and the node (output terminal) N4, or the wiring can be lengthened to delay the desired time. In the delay circuit 5, the desired time corresponds to t4 (see the timing waveform of the line L) in the timing chart shown in FIG. 6, and is the time when the line L has settled to the precharge level Vr.

FIG. 4 is a diagram showing an example of the configuration of the precharge circuit 3 in the first level shift circuit H1 shown in FIG. Referring to FIG. 4, input terminal N1 of precharge circuit 3 is connected to the gate of P-type MOS transistor 31 and N
The drain of the P-type MOS transistor 31 is connected to the anode of a diode 34,
Is connected to the anode of a diode 35, and the cathode of the diode 35 is connected to an N-type MOS transistor 32.
And the output terminal N2, which is connected to the line L.

FIG. 5 is a diagram showing an example of the configuration of the second level shift circuit S1 shown in FIG. All of the second level shift circuits S1, S2, S3,... Have the same configuration. As shown in FIG. 5A, the second level shift circuit S1 is configured by connecting inverters 41 and 42 in two stages in series.

FIG. 5B is a diagram showing the circuit configuration of the second level shift circuit S1 shown in FIG. 5A at the transistor level. Inverter 41 located at input section
Is configured using a transistor whose threshold voltage is slightly higher than the precharge level (this threshold voltage is
th).

FIG. 6 is a timing waveform chart for explaining the operation of one embodiment of the present invention.

When the clock signal is at a low level, the nodes N1 and N3 are at a high level. At this time, the level of the node N2 output through the precharge circuit 3 is low, and the level of the line L is also low.
Then, since the level of the node N4 output through the delay circuit 5 is at the high level, the P-type MOS transistor 7 is off, and the level of the line L is kept at the low level.

When the clock signal changes from low level to high level, the nodes N1 and N3 change from high level to low level, and the output node N2 of the precharge circuit 3
Becomes the precharge level Vr which is two steps lower than the power supply potential VCC, the diodes 34 and 35, and the line L also becomes the precharge level Vr.

Output node N4 of delay circuit 5 is connected to node N
3 after a delay time t4 from the transition edge to the low level,
Change from high level to low level. Then, when the node N4 goes low, P serving as a switch function
The MOS transistor 7 is turned on, and the line L is raised to the power supply potential VCC level.

When the line L changes from the precharge level Vr to the power supply potential Vcc level, the second level shift circuits S1, S2,.
The outputs C1 to C9 rise from a low level to a high level.

The P-type MOS transistor 7 in the first level shift circuit H1 has a large size to drive the line L.

When the clock signal changes from the high level to the low level, the high level of the line L is gradually lowered by the precharge circuit 3 to the low level. After a lapse of t6 by the delay circuit 5, the P-type MOS transistor is turned off, and the line L is completely pulled down to the low level.

As can be seen from the above description of the operation, the skew difference from the input clock signal to the nodes C1 to C9 is determined by the fact that the level of the line L is equal to the precharge level Vr.
To the threshold voltage Vth of the second level shift circuits S1, S2,...

That is, at the output stage of the first level shift circuit H1, a P-type MO operating as a switch function
The second level shift circuit S1 closest to the S transistor 7 has the shortest time t5, and the second level shift circuit S1
The time t5 in the level shift circuit Sn becomes the longest. Although this difference causes a skew, in this embodiment, the line L is precharged, and the operation by the transition from the precharge level Vr to the VCC level has the same function as the operation with the small amplitude. The skew is small, high speed is obtained, and the difference in t5 between the second level shift circuits S1 and Sn (farthest from the P-type MOS transistor 7) is very small.

Therefore, in the conventional clock distribution circuit having the tree structure, the skew depends on all the wirings from the input to the output, but in the clock distribution circuit according to the embodiment of the present invention, only the line L is mainly used. It does not depend and operates at the same high speed as the small amplitude operation, so that the skew between clocks is reduced.

Further, in the conventional clock distribution circuit having a tree structure, it is necessary to increase the area because the equal distribution and the equal wiring are performed in consideration of the branch points in the next and subsequent stages. However, the clock distribution circuit according to the present embodiment is suitable for miniaturization (compactization), and has the advantage of increasing the degree of freedom in layout design.

Further, when distributing clocks to, for example, nine clocks, a clock distribution circuit having a conventional tree structure causes useless circuits. However, according to the clock distribution circuit according to the present embodiment, there is no waste. There is no unnecessary circuit, so that unnecessary power is not consumed.

In this embodiment, the number of clocks to be distributed can be arbitrarily set by increasing the number of the second level shift circuits.

Also, the P-type MOS transistor 7 in the first level shift circuit H1 is changed to an N-type MOS transistor, and one of the diodes constituting the precharge circuit 3 is omitted. It can be achieved by obtaining various functions and effects.

Although the embodiment of the present invention has been described above, the embodiment shown here is merely an example, and the present invention is not limited to the above-described embodiment, and the scope according to the principle of the present invention is not limited thereto. Of course, various changes and improvements are included.

[0039]

As described above, according to the present invention,
A skew can be reduced by providing a precharge circuit, making the clock signal once small in amplitude, and distributing the clock via a second level shift circuit according to the required number of clocks. Can be
It is possible to suppress the increase in the area, to distribute clocks to an arbitrary number without consuming unnecessary power, and to achieve an arrangement wiring with a high degree of freedom.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a clock distribution circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a first level shift circuit H1 according to one embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a delay circuit in a first level shift circuit H1 according to one embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a precharge circuit in the first level shift circuit H1 according to one embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a second level shift circuit S1 according to one embodiment of the present invention.

FIG. 6 is a diagram showing timing waveforms for explaining the operation of one embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional tree-type clock distribution circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 inverter 3 precharge circuit 5 delay circuit 7 P-type MOS transistor 10 clock distribution circuit 20 block diagram 31 P-type MOS transistor 32 N-type MOS transistor 34, 35 diode 41, 42 inverter C1 to C16 clock output node CLK clock input terminal H1 First level shift circuit L line S1 to S9 Second level shift circuit

Claims (4)

(57) [Claims] 1. A distributes one of the clock signal input,
Connecting a clock distributing circuit for supplying a plurality of circuits, the first level shift circuit to output to the line by a clock signal the input to the small amplitude, in a parallel configuration with each other for the lines that require a clock signal input and a plurality of second level shift circuit that will be, the plurality of second level shift circuits, respectively, the
Output on the line from the first level shift circuit
The small amplitude clock signal is returned to the original amplitude, and the original amplitude is restored.
The clock signal whose width has been returned must be
A clock distribution circuit for outputting a clock signal to a required circuit. 2. The transistor constituting the second level shift circuit, wherein the first level shift circuit includes means for raising the potential of the line to a power supply potential after the potential of the line reaches a predetermined precharge level. 2. The clock distribution circuit according to claim 1, wherein the threshold voltage is set higher than the precharge level. 3. The means for pre-charging the line to a predetermined potential (hereinafter referred to as "pre-charge potential") in response to a predetermined transition of the input clock signal; 2. The clock distribution circuit according to claim 1, further comprising: means for setting the potential of the line to a power supply potential after reaching the predetermined precharge potential. 4. The second level shift circuit includes a buffer circuit to which a signal on the line is input, and a threshold voltage of a transistor constituting the buffer circuit is set to a value exceeding the precharge potential. The clock distribution circuit according to claim 1, wherein the clock distribution circuit is set.