JPS644340B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array type master slice integrated circuit, and particularly to an output emitter follower circuit thereof.

Figure 1 is a circuit diagram showing an example of such a logic circuit, which has an emitter follower circuit in its output circuit.
This shows a CML (Current mode logic) circuit. In the figure, 1a, 1b and 1c are transistors that constitute this, 2 is a common emitter resistance, 3 is a common collector resistance of transistors 1a and 1b, 4 is a collector resistance of transistor 1c, 5 is an emitter follower transistor, and 6 is a common emitter resistance. Its emitter resistors, 7a and 7b are logic input terminals connected to the bases of transistors 1a and 1b, respectively, 8 is a reference voltage input terminal connected to the base of transistor 1c, 9 is a collector voltage V _CC supply terminal, and 10 is an emitter resistor. The voltage V _EE supply terminal 11 is an emitter follower output terminal, and since the logic operation of this circuit is well known, the explanation will be omitted.

By the way, in the conventional gate array type integrated circuit, the value of the emitter resistor 6 of the emitter follower circuit is constant and the current drive capability is constant, so the operation delay time of this logic circuit depends on the capacitance value of the load circuit. This caused a difference in logic design, which caused problems in logical design. It is possible to create several types of logic circuits with different current drive capabilities in advance and use them in appropriate combinations, but depending on the type of circuits that are incorporated, this may result in waste or lack of capacity. There were flaws.

This invention was made in view of the above points, and the basic gate circuits themselves are the same, and the resistance value of the emitter follower circuit section is changed through the wiring process, so that the load can be improved. The object of the present invention is to obtain a gate array type integrated circuit that can reduce variations in operation delay time by making it possible to change the current value of an emitter follower circuit depending on the capacitance value of the circuit.

FIG. 2 is a circuit diagram showing an embodiment of this invention.
Portions equivalent to those in the conventional example are indicated by the same reference numerals, and their explanation will be omitted. The emitter resistance of the emitter follower circuit section as an output stage is divided into three parts 6A, 6B and 6C, and the terminal 12 is connected from the bottom end of each part.
A, 12B and 12C are drawn out and the emitter resistance value can be changed by connecting them to a terminal 13 connected to an emitter power supply terminal 10.

FIG. 3 is a circuit diagram showing an embodiment of the present invention. In this embodiment, the emitter resistors of the emitter follower circuit are composed of mutually independent resistors 6α, 6β and 6γ, and terminals 12α and 12β are connected from the lower ends of each.
and 12γ, and by selecting which resistor depending on the connection with the terminal 13, and by combining parallel connections, various emitter resistance values can be obtained.

Therefore, in each of the above embodiments, the emitter resistance value may be set to be small or large depending on whether the capacitance value of the load circuit connected to the output terminal 11 is large or small.

In addition, in the above explanation, we talked about a CML circuit that has an emitter follower circuit in the output circuit, but CML
There is no reason to limit the present invention to circuits, and the present invention can be widely applied to logic circuits having emitter follower circuits in their output circuits. Further, although an example has been shown in which the emitter resistor is divided into three parts, it is obvious that this number of divisions is not limited to three parts.

As explained above, in the logic circuit according to the present invention, the emitter resistance of the emitter follower circuit constituting the output circuit is divided into a plurality of parts, and the emitter resistance value is adjusted according to the capacitance value of the load circuit depending on the wiring. Since it is possible to set the delay time of the circuit, it is possible to reduce the variation in the operation delay time of the circuit, making logic design easier.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional logic circuit; Figure 2 is a circuit diagram showing an example of a conventional logic circuit;
The figure is a circuit diagram showing one embodiment of the invention, and FIG. 3 is a circuit diagram showing another embodiment of the invention. In the figure, 5 is an emitter follower transistor, 6A, 6B, 6C, 6α, 6β, 6γ are partial resistors constituting the emitter resistor, 12A, 12B,
12C, 12α, 12β, and 12γ are terminals, and 13 is an emitter voltage supply line terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A gate array type master slice integrated circuit that is formed in common up to the process excluding the wiring process and that configures various logic circuits by changing only the wiring process, and the logic gates are composed of CML circuits. In a gate array type master slice integrated circuit having a switching section and an emitter follower section as an output stage, the emitter resistor of the emitter follower section is composed of a plurality of partial resistors, and the wiring pattern is changed in the wiring process to achieve the above A gate array type master slice integrated circuit characterized in that the current in an emitter follower section can be changed.