JPS5811135B2 - Frequency divider circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a frequency dividing circuit.

The 1/2 frequency divider circuit, which is the smallest unit of a frequency divider circuit, is usually composed of about 6 gates, but in order to reduce power consumption and increase the degree of integration, it has been specially devised to consist of 4 gates. is also possible.

An example is shown in FIG.

That is, the circuit basically consists of four gates 01 to G4, but there are delay elements D1. Inserting D2 enables frequency division operation.

Clock pulse CP of the frequency divider circuit in Fig. 1 and each gate) G1
-The output waveform of G4 is shown in FIG.

In the case of this frequency divider circuit, the gate output pulse changes at three locations during the period (3).

Furthermore, the gates G2 and G3 have delay elements D1 and D1, respectively, at their output ends. Since it includes D2, the time required for change is longer than other gates.

This means that in order for the frequency divider circuit of FIG. 1 to operate normally, these three changes must be completed within a half period of the clock pulse CP.

Therefore, in order to operate reliably when this frequency divider circuit is operated at a low current, in other words, even when the output pulse change time of each gate becomes long, the period of ■ should be longer than the period of It is desired that the lock pulse is as follows.

However, even if the first-stage clock pulse satisfies the above-mentioned conditions, if the frequency divider circuit shown in FIG. 1 is connected in multiple stages, the output waveform of gate G3 shown in FIG. As you can see, from the second stage onwards, the period of ■ and ■
The periods become equal.

Normally, in order to minimize power consumption in the entire circuit, 1
When several stages of /2 frequency divider circuits are connected, the current supplied to each stage is reduced in proportion to the frequency.

For example, if the current supplied to the first stage is 1, the current supplied to the second stage is 1/2.
The third stage reduces the current by (1/2)2.

In order to reduce power consumption in this way, it is desirable to have a circuit configuration in which the period (2) is longer than the period (2) no matter how many stages are connected.

This invention has been made in view of the above points, and provides a frequency divider circuit that is basically composed of four NAND or NOR gates and can operate with low power even when connected in multiple stages. It is something.

A third embodiment of this invention using a Nant gate is described below.
As shown in the figure.

That is, it is composed of first to fourth Nant gates G, 1 to G14, and first and second gates G11 . The outputs of G12 are respectively connected to the second and first gates G12. G11, and the outputs of the third and fourth gates G13-Gl4 are fed back to the fourth and third gates G14. It is fed back to the input of G13.

Then, the output of the first gate G11 is transmitted to the third and fourth gates G13 . G14, and the output of the fourth gate G14 is fed back to the first gate G11.
Gate G11. A first clock pulse CP is input to G12, and a clock pulse CP having a partially opposite phase is input to the fourth gate G14.

Note that a delay element Dll? is provided at the output terminals of the second gate G12 and the third gate G13. D12 is provided.

These delay elements D11. D12 is for making the delay in the output change of the second gate G12 larger than that of the first gate Gll, and the delay in the output change of the third gate cts larger than that of the fourth gate G14. It is.

In this case, the function of the delay element DtttD12 is to change the gate output from a high level (logic "1") to a low level (logic "1").
It is only necessary to delay the time when changing from a low level to a high level (0''), and there is no need to delay the time when changing from a low level to a high level.

However, when configured with NOR gates, this relationship is reversed.In order to operate the frequency divider circuit configured in this way stably, clock pulses cp and cp must both be at low levels, as shown in Figure 4. It is important to create a system so that this does not happen.

However, when configured with Noah gates, make sure that both levels do not become high.

A specific operation timing chart of the frequency dividing circuit shown in FIG. 3 is shown in FIG.

The order of changes in the output pulses of the gates G11 to G14 is the same as that of the conventional frequency divider circuit shown in FIG. The output of G14, that is, Q, has the same time relationship as the clock pulses cp and cp.

In other words, the Q and Q outputs are used as the clock pulses cp and cp of the next stage.
By doing so, this relationship is maintained no matter how many stages are connected, and therefore it is possible to operate with lower power than conventional frequency divider circuits.

Next, an example using I2L as a logic element will be described.

■2L was the first to be developed, and it is the 6th in terms of circuits.
As shown in the figure, there is an NPN) transistor T1 for the inverter, and a PNP) transistor T1 for the injector, whose collector is connected to the base of this transistor T1 and whose base is connected to the emitter.
It consists of 2.

The inverter transistor T1 is composed of a so-called reverse structure particle transistor in which the emitter and collector of a normal planar transistor are reversed, and the injector transistor T2 has a collector and a base that are shared with the base and emitter of the inverter transistor T1, respectively. It is configured as a lateral structure transistor.

An external power supply vEE is applied to the emitter of the injector transistor T2, and a charge is supplied to the base of the inverter transistor T1 via this transistor T2, thereby performing a logic operation.

In the example shown in FIG. 6, the inverter transistor T1 is of a multi-collector type, and three output terminals 0UT1 to 0UT3 are provided, and three input terminals IN1 to ■N3 are provided.
In the following explanation, the symbol of the Nant gate based on 2L will be expressed as shown in FIG. 7.

FIG. 8 shows a frequency dividing circuit corresponding to FIG. 3 when such I2L is used.

That is, the first to fourth Nantes gates G21 using I2L
~ Consists of G24.

In this configuration, the slow element D11eD12 shown in FIG. 3 is omitted, and this point will be explained as follows.

When using I2L, the main point for normal operation is that the first
, second gate G21. By making the first gate G21 reach the high level earlier than the second gate G21 when the potential at the input part of G22 is controlled and simultaneously rises from a low level to a high level. be.

Similarly, the third and fourth gates G23. Regarding the G24 as well,
The rise time of the third gate G24 when the suppression by the output of the first gate G21 is removed is set to be shorter than that of the third gate G24.

That is, the one that reaches a high level earlier suppresses the other to a low level, resulting in the same effect as when delay elements are inserted into the outputs of the second and third gates G22G23.

Specifically, differentiating the rise times of the gate input sections can be easily achieved by changing the shape of the injector transistor.

For example, the second and third gates G22. The current supplied by the injector transistor G23 is supplied to the first and fourth gates G21. It is set to about 1/2 of that of G24.

This causes the second and third gates G22. The time required for the input potential of G23 to change from a low level to a high level is approximately twice that of the first and fourth gates G21tG24, allowing stable frequency division operation.

As a means for making a difference in the rise time of the gate input part, for example, a capacitor may be attached to make a difference in the size of the capacitance of the gate input part without changing the shape of the injector.

However, in order to reduce power consumption as much as possible, it is preferable to reduce the current supplied by the injector and replace it with a delay element.The measurement results of the frequency and minimum power consumption of the frequency divider circuit shown in FIG. 8 are shown in FIG.

FIG. 9 shows, as a conventional example, the measurement results of a frequency dividing circuit corresponding to FIG. 1 which is also constructed using the I2 hole.

As is clear from the measurement results, the frequency divider circuit according to the present invention operates at a higher frequency than the conventional circuit, and consumes less power when compared at the same frequency.

The examples used for measurement were the first and fourth games (G2).
1-G24 injector current flows through the second and third gates G
22. I set it to flow twice as much as the G23, but it worked even if this difference was a little smaller.

However, if the difference is smaller than 1.3 times, it becomes unstable.On the other hand, if the difference is made larger, the operation is stable, but about 2.
If it exceeds 5 times, the operating frequency will decrease, which is not preferable.

In this case, since the stability varies depending on the operating frequency, for example, when the operating frequency is high, measures such as increasing the supply current ratio may be taken.

In order to change the contents of the frequency divider circuit according to the present invention, it is sufficient to provide it with set and reset functions.

FIGS. 10 to 12 are examples thereof.

In the example shown in FIG. 10, the set signal S and reset signal R are input to the third and fourth gates G23 and G24, respectively, via the inverter 115I2.

In the example shown in FIGS. 11 and 12, the Nant gate G uses the I2 hole.

1°Go2 is provided, and its output controls the gates G21 to G24.

There are several ways to set and reset, so you can use them depending on your purpose.

As described above, according to the present invention, it is possible to operate with a small number of elements and low power consumption even when connected in multiple stages.
Therefore, it is possible to provide a frequency dividing circuit that can improve the degree of integration.

Note that the above explanation has focused on an embodiment using a multi-output NAND gate using an I2 hole, but this is a preferred embodiment, and the frequency dividing circuit according to the present invention is suitable for CM
It can also be configured with a Nant gate using O8 or TTL.

Furthermore, when operating with negative logic, a NOR gate may be used instead of a Nant gate.

Furthermore, when the I2 hole is used, due to its nature, a means of cutting off the supply current from the injector may be used to output a low level.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a conventional frequency dividing circuit, Fig. 2 is an operation timing chart thereof, Fig. 3 is a diagram showing an example of a frequency dividing circuit according to the present invention, and Fig. 4 is a diagram showing an example of the frequency dividing circuit. 5 is an operation timing chart of the frequency dividing circuit, FIG. 6 is an equivalent circuit diagram of the I2 hole, No. 71 is a diagram showing the Nantes Gate symbol using the I2 hole, and FIG. FIG. 8 is a diagram showing an example of a frequency dividing circuit according to the present invention configured using an I2 hole, FIG. 9 is a diagram showing measurement results regarding the frequency and minimum power consumption in comparison with a conventional example, and FIGS. Figure 12 shows the frequency divider circuit shown in Figure 8 set up.
It is a figure showing an example provided with a reset function. G11. G21...First Nantes Gate, G1
2°G22...Second Nantes Gate, G13.
G23...Third Nantes Gate, G14. G2
4...Fourth Nantes Gate, D11tD12・
・Delay element.

Claims (1)

[Claims] 1. Constructed using four NAND or NOR gates, the outputs of the second and first gates are fed back to the inputs of the first and second gates, respectively, and the outputs of the third and fourth gates are fed back to the inputs of the first and second gates, respectively. Feedback the outputs of the fourth and third gates to the inputs, input the outputs of the first gate to the third and fourth gates, and input the outputs of the fourth gate to the inputs of the first gate. The first clock pulse is fed back to the first and second gates, the second clock pulse having a partially opposite phase is input to the fourth gate, and the first to fourth gates In the case of a NAND gate, the first and second clock pulses do not become logic "0" at the same time, and when the first to fourth gates are NOR gates, the first and second clock pulses become logic "0" at the same time. 1", and the delay in the output change of the second gate is greater than that of the first gate, and the delay in the output change of the third gate is greater than that of the fourth gate. 2. Each of the first to fourth gates is a logic circuit consisting of an inverter transistor, and a complementary injector transistor with a collector connected to the base of this transistor and a base connected to the emitter. The device is configured to have a potential rise time of the first gate input section shorter than that of the second gate, and a potential rise time of the fourth gate input section shorter than that of the third gate. 3. The frequency divider circuit according to claim 1. 3. As a means for making a difference in the rise time of the potential of the gate input part, it is possible to make a difference in the current supplied by the injector transistor or to make a difference in the rise time of the potential of the gate input part. 3. The frequency dividing circuit according to claim 2, wherein the difference in capacitance is increased.