JPS5915529B2 - logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit that operates similar to a D-type flip-flop circuit.

The conventionally known synchronous D-type flip-flop circuit (
The FF (hereinafter abbreviated as FF) is generally configured as shown in FIG. 1 or 2.

FIG. 1 shows an example using six Nant gates, which operate in response to a clock pulse CP to obtain an output Q which is an input signal delayed by one clock pulse time.

q is an output that is in opposite phase to the output Q.

FIG. 2 shows an example using eight Nant gates, which are operated by a clock pulse CP and a clock pulse CP having an opposite phase.

In order to integrate such a curved FF, it goes without saying that a circuit configuration with as few elements and wires as possible is desired from the viewpoint of power consumption and degree of integration.

This invention reduces the number of gates through which pulses pass and appropriately sets the time delay of pulses passing through the gates, thereby reducing the number of wires and creating a logic circuit that enables low-power operation and improved integration. This is what we provide.

The basic logic circuit of this invention is composed of four Nant gates or four Nor gates.

FIG. 3 shows the basic configuration when using a Nant gate.

That is, the first and second Nantes gates G1. G2 feed back one output to the other input, and similarly connect the third and fourth Nant gates G3 . Regarding G4, one output is fed back to the other input, and the output of the first NAND gate G4 is input to the third and fourth NAND gates G3 and G4.

Then, the first and second gates G1. The first clock pulse CP is commonly input to G2, the second clock pulse O having the opposite phase is input to the fourth gate G4, the signal is input to the first gate, and the third and third clock pulses are inputted to the fourth gate G4. Output Q from gate 4.

Q' is obtained.

Here, the second and third gates G2. Delay elements DL1. DL2 is provided.

In this way, delay element DL1. By inserting DL2, the second and third gates G2. The delay in the output change of G3 is the first and fourth game respectively) G12 Thicker than that of G4 (
As a result, it is possible to perform a desired logical operation without using the b input.

The operation timing chart is shown in FIG.

In this case, delay element DL1. As for the function of DL2, it is only necessary to delay the time when the gate output changes from a high level to a low level, and there is no need to delay the time when the gate output changes from a low level to a high level.

However, when using the Noah gate, this relationship is reversed.

The logic circuit according to the present invention has I 2L as a logic element.
(Integrated Injection Log
ic) is particularly effective.

I2L is a recently developed logic element, and its equivalent circuit is shown in FIG.

That is, it is composed of an inverter NPNI transistor T1 and an injector PNP transistor T2 whose collector is connected to the base of this transistor T1 and whose base is connected to the emitter.

The inverter transistor T1 is composed of a so-called reverse structure particle transistor in which the emitter and collector of a normal planar transistor are reversed, and the injector transistor T2 has a collector and a base that are shared with the base emitter of the inverter transistor T□. It is configured as a lateral structure transistor.

Logic operation is performed by applying an external power supply VEE to the emitter of the injector transistor T2 and supplying charges to the base of the inverter transistor T1 via the transistor T2.

In the example shown in FIG. 5, the inverter transistor T1 is of a multi-collector type, and two output terminals 0UT1 and 0UT2 are provided, and three input terminals IN1 to 1N3 are provided.
The symbol for I2L will be expressed as shown in FIG. 6 in the following explanation.

FIG. 7 shows a logic circuit corresponding to FIG. 3 when such 2L is used.

They are basically the same in that they are composed of four gates G11 to G14 and operate with only one input.

Game)G.

1. Go2 is for transmitting clock pulses.

Although the delay elements shown in FIG. 3 are omitted in FIG. 7, this is because gates G1. This is because by selecting the shape of ~G14, it has the same function as adding a delay element.

That is, in the configuration of FIG. 7, the second and third games) G12
, the shape of the injector transistor in G13 is changed from that of the other gates, and the supply current is set to be smaller than that of the other gates.

As a result, the rise times of the input parts of the second and third gates G12 t G13 are the same as those of the first and fourth gates G11, respectively.
longer than that of

In this way, when the clock pulse CP changes from a low level to a high level, if the D input is at a high level, the potential at the input of the first gate G11 will rise before that of the second gate G1□. level, causing the potential at the input portion of the second gate G12 connected to the output of the first gate G11 to become low level.

Conversely, if the D input is at a low level, the input part of the first gate G1□ cannot go to a high level, the potential at the input part of the second gate G1□ becomes a high level, and the potential of the input part of the second gate G1□ becomes high level. The potential at the input portion of the first gate G1 connected to the output is suppressed to a low level.

As described above, when the D input is at a high level or a low level and the clock pulse CP goes from a low level to a high level, the potentials at the input parts of the first and second gates G11° and G1° are shown in FIG. It is uniquely determined, as is the case when a delay element is included as shown in .

Third and fourth gates G13. The relationship between G14 is also the first and second
Gate G11. The relationship is similar to that of G12.

In this way, eliminating the need for the b input simplifies wiring and greatly contributes to improving the degree of integration when considering the case where several stages of this type of logic circuit are connected in cascade to form a counting circuit, etc. .

In addition, in a counting circuit, etc., two gates can be connected from the output of one gate to the input stage.
In order to take out two feedback loops, an extra gate must be added in the conventional type that requires D and D inputs, but if the logic circuit according to the present invention is used, such an extra gate is not necessary. .

As a clock pulse for driving the logic circuit shown in FIG. 7, for example, one shown in FIG. 8 is preferable.

That is, it is a pulse with a duty cycle of 50% in which CP and σ change simultaneously.

Such lock pulses cp, cp can be easily created using a linear circuit.

(2) In the case of 2L, the pulse transmission delay can be controlled by appropriately selecting the positional relationship between the injector and collector, the injector current, etc.

Clock pulse CP used in the circuit of FIG.

The CP may be as shown in FIG. 9.

Such lock pulses cp, cp can be created by the gate configuration shown in FIG.

It is also possible to use clock pulses CP, CP, which have a long overlapping time at a low level, as shown in FIG.

As shown in Fig. 12, the first method for outputting the output is
Used by connecting the outputs of the fourth gate Gll and G14.
But that's fine.

Also, as shown in Fig. 13, there is a gate on the output side.
If a latch circuit consisting of te is provided, a complete complementary output Q
, Q can be obtained.

FIG. 14 is an example of a synchronous ternary counting circuit constructed using the logic circuit according to the present invention.

That is, a similar logic circuit consisting of gates G2□ to G24 is connected to a basic logic circuit consisting of gates G11 to G14,
The output of gate G24 is input to the D input of gate G1□, and outputs Q, Q2 are taken out from gates G137 and G23, respectively.

The operation timing chart is shown in FIG.

To change the contents of the logic circuit according to this invention, set,
A reset terminal may be provided.

Examples are shown in FIGS. 16 and 17.

In these circuits, gates Gs and GR are for transmitting signals from set terminal S and reset terminal R.

Note that some set and reset signal lines can be omitted depending on the purpose.

Although a few examples have been given above, we have also experimentally confirmed what degree of difference is preferable when making a difference in the current supplied by the gate injector.

As a result, it was found that when the ratio of supply currents is less than 1.3, the operation becomes unstable, and when it exceeds 2.5, the operating frequency becomes undesirably low.

In this case, since the stability varies depending on the operating frequency, measures such as increasing the supply current ratio depending on the operating frequency may be taken.

Note that instead of changing the shape of the injector to vary the supply current as a means of increasing the difference in the rise time of the gate input section, for example, a capacitor may be provided at the gate input section to create a difference in the size of the capacitance. .

As explained in detail above, the logic circuit according to the present invention has a small number of elements (and the number of wiring can be reduced by appropriately setting the time delay of the pulse passing through the gate).
Low power operation and higher integration density can be achieved.

In the above description, the embodiment was mainly based on a multi-output NAND gate using 2L, but the logic circuit according to the present invention can also be constructed with a NAND gate using CMO8 or TTL.

Further, when configured with negative logic, a NOR gate may be used instead of a Nant gate.

Furthermore, when using 2L, due to its nature, a method of cutting off the supply current from the injector may be used to output a low level.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Brief explanation of drawings]

1 and 2 are diagrams showing conventional synchronous type FF,
Fig. 3 is a diagram showing a logic circuit using four Nant gates which is the basis of this invention, Fig. 4 is its operation timing chart, Fig. 5 is an equivalent circuit diagram of I2L, and Fig. 6 is a diagram using ■2L. A diagram showing a Nant gate symbol, FIG. 7 is a diagram showing an example of a logic circuit according to the present invention configured using I2L,
8 and 9 are diagrams showing an example of the waveform of the clock pulse used in the circuit of FIG. 7, FIG. 10 is a diagram showing an example of the circuit configuration for obtaining the clock pulse of FIG. 9, and FIG. Figure 12 shows another clock pulse waveform example used in the circuit of
13 and 13 are diagrams showing a modified example of how the output of the circuit shown in FIG. 7 is taken out, and FIG. 15
The figure shows its operation timing chart, Figure 16 and Figure 1.
FIG. 7 is a diagram showing an embodiment in which the logic circuit according to the present invention is provided with set and reset functions. G1. GH...First Nantes Gate, G2゜G
1□・・・Second Nantes Gate, G3. G13・
...Third Nantes Gate, G4. G14...
...Fourth Nantes Gate, DLI, DL2...
・Delay element.

Claims (1)

[Claims] 1. Constructed using four NAND or NOR gates, the outputs of the second and first gates are fed back to the inputs of the first and second gates, respectively, and the outputs of the third and fourth gates are fed back to the inputs of the first and second gates, respectively. The fourth and third outputs are fed back to the inputs, respectively, and the delay in output change of the second and third gates is set to be larger than that of the first and fourth gates, respectively. The first clock pulse is input to the second gate, and the second clock pulse having the opposite phase is input to the fourth gate, and the first clock pulse is input to the fourth gate.
1. A logic circuit characterized in that a logic operation similar to a D-type flip-flop is performed by supplying an input signal to the gate of the first gate and inputting the output of the first gate to the third and fourth gates. 2. Each of the first to fourth gates is composed of a logic element consisting of an inverter transistor and a complementary injector transistor with a collector connected to the base of this transistor and a base connected to the emitter. Third
2. The logic circuit according to claim 1, wherein the rise time of the gate input section of the gate is set to be longer than that of the first and fourth gates.