JPS5811133B2 - flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit that uses four logic gates to operate with only one input line and one output line.

Conventionally, masterslave type flip-flop circuits have been known for use in binary counters and frequency divider circuits.

As shown in FIG. 1, this flip-flop circuit (hereinafter referred to as FF circuit) has a first R-
8-FF circuit 1 and a second R- having gates G, ~G8
8-FF circuit 2 is combined.

The control clock pulse CP is supplied to the first OFF circuit 1, and the control clock pulse CP is supplied to the second FF circuit 2, respectively, and the output signal Q2. Q2 is obtained from gates G8 and G7, respectively.

Considering clock pulses CP and CP as input signals, when CP is at a high level, CP is at a low level, and when CP is at a low level, CP is at a high level.

In the first step, if the output Q2 is at a high level vH, when CP becomes a high level vH, the input control gate G1. G2 is opened and the output Q of the first FF circuit 1 becomes vH.

Since CP becomes low level vL in the second step,
Control gate G1. G2 closes.

Since CP becomes vH, the FF circuit 20 input control gate G5. G6 opens.

Therefore, the FF circuit 2 is inverted, and its output Q2 is v
It becomes L.

In the third step, CP becomes vL, so control games )G, , G6 are closed.

In this way, clock pulses cp and cp are alternately applied to VH.
By becoming 2VL, the state of vH changes to FF circuit 1,
It is alternately exchanged between 2.

In other words, until CP becomes vH twice, output Q2 becomes VH only once.
takes the state of

The drawbacks of the master-slave type FF circuit described above are as follows.

That is, since there are eight logic gates and two input lines and two output lines are required, it is difficult to construct as many FF circuits as possible using high-density integrated circuits.

Furthermore, since there must not be a period in which both the CP and CP waveforms are at vH, there is a drawback that the clock pulse waveform is restricted.

An object of the present invention is to provide a flip-flop circuit that achieves the functions of the flip-flop circuit shown in FIG. 1 by using four logic gates and one input line and one output line.

According to the present invention, the number of logic generators can be reduced and the number of input and output signal lines can be reduced to 1/2 compared to the conventional example shown in FIG. In this case, the integration density can be increased and the upper limit of the operating frequency can be increased.

Also, the number of logic gates can be reduced.

Therefore, high speed operation is possible with low power consumption.

The details of the present invention will be explained below with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention, FIG. 3 shows a circuit embodying the same in IIL, and FIG. 4 is a plan view of the same when it is further integrated into an integrated circuit.

In this embodiment, the flip-flop circuit is composed of first, second, third, and fourth NAND gates A, BC, and D.

These NAND gates are IIL (Integr
ated InjectionLogic).

That is, NAND game) A, B, C, D NPN transistors TR.

TR2, TR3, and TR4 have first and second output terminals AI, A2, Bl, B2, CI, C2, DI, and D2, respectively, and their emitters are commonly grounded.

PNP injection transistor TR,, TRa,
TR? , TR8 are connected to the base and emitter of the corresponding NPN transistor, respectively, and the emitters are commonly connected to the power supply VEE.

The first output terminal A1 of the gate A is connected to the base of the gate B, the first output B1 of the gate B is connected to the base of the gate A, the first output C1 of the gate C is connected to the base of the gate D, The first outputs D1 of the gates D are connected to the bases of the gates C, respectively.

The base of G)A and the base of G)B are connected through the first diode 3 which is in the forward direction from gate A to gate B, and the base of G)D and the base of gate C are connected. It is connected to the base via a second diode 4 which is in the forward direction from the gate D to the gate C.

A second output terminal D2 of gate D is connected to the base of gate A.

The input signal NB is supplied to the base of the gate B, and the output signal Q is taken out from the second output terminal C2 of the gate C.

In FIG. 4, each part is given a reference numeral corresponding to that in FIG. 3, and a description thereof will be omitted.

As can be seen from FIG. 4, the emitter region 5 provided commonly to the injection transistors TR5, TR6, TR7°TR8 is of P type, and this region 5 has a stripe shape, and the injector source voltage VEE
is applied.

Output terminals B, , B2 of gate B are provided.

The output area (NPN) (N area of the transistor) and the output area N, in which the output terminals C1 and C2 of the gate C are provided, is configured at right angles to the stripe 5, and
Output terminals A, , A2 and output terminals of game) D, , D2
The output area (N area) where is provided is configured parallel to the stripe 5.

For this purpose, N from the PNP injector transistor is
The current supplied to the PN transistor is higher for gate A than for gate B, and higher for gate D than for gate C.

Therefore, the input current supplied to gate A is higher than gate A)
The input current supplied to gate D rises earlier than the input current supplied to gate C, and the input current supplied to gate D rises earlier than the input current supplied to gate C.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIGS. 5 and 6.

The input signal CP (clock pulse) (see Figure 6) to the third gate of FF in all previous stages is in the initial state (first step).
Assume that the current level is VL (low level).

At this time, the logic values of the A and H input lines are vH, respectively.
(high level) VL (low level) or either vL or VH, but let us now assume that it is VH2vL.

In this case, the level of the voltage at the input terminal of gates C and B is respectively vL.

Strictly speaking, the level of the input terminal voltage of gate D is higher than the level of the input terminal voltage of gate C by the forward voltage drop VF of diode 4, but the input terminal voltage level of gate D is a logical value. It is vL.

Although it is preferable to use Schottky diodes as the diodes 3 and 4, ordinary pN junction diodes may also be used.

In this case, the concentration of the PN region is set to 10'7ato, for example.
It is desirable that the concentration be approximately ms/crA.

In this first step, the output Q of gate C is at the level of VH.

Next, in the second step, the level of the input signal CP is vL
Suppose that there is a change from vH to vH.

Then, the input terminal voltages of game) A and H both become vL.

The input terminal voltage of game) A shows a level of vF, but its logic level is vL.

Then, the output side A1 of game) A. A2 and the output terminal B1. B2 now has a high impedance to ground.

As a result, the voltage at the input terminal of one of gates C and D is vH1 and the other is vL, but the input terminal voltage of gate D is higher than the input terminal voltage of gate C due to the forward voltage drop of diode 4. Because the injector current to gate D is higher than the injector current to gate C as already explained in FIG. Therefore, the input terminal voltage of gate C becomes VL.

Therefore, the level of output Q is maintained at VH.

In the third step, CP becomes vL again.

However, the output terminal D1 of gate D. Since the voltage of D2 is VL, the input terminal voltage of gate A is held at vL, and the input terminal voltage of gate B becomes VHH.

Therefore, the voltage at the output terminals B, , B2 of the gate H becomes VL, the input terminal voltage of the gate D becomes VL, and the input terminal voltage of the gate C becomes VH.

Therefore, the level of output Q becomes vL.

In the fourth step, the level of input signal CP is set to VH again.
become.

Gate A when scolded. The input terminal voltages of B are both vL.

The input terminal voltage of the gate A has the forward drop level VF of the diode 3, but the logic level is VL.

However, the input terminal voltages of gates C and D maintain the state of the third step.

The input terminal voltage level of gate D has VF equal to the positive voltage drop of diode 4, but is still at the level of vL.

Since the input terminal voltage of gate C is VH, the level of output Q is maintained at the level of vL at the third step.

In the fifth step, the input signal CP changes again to vL.

This time, the output terminal D1 of gate D. Since the voltage of D2 is vH, the input terminal voltage of G-A becomes vH, and the input terminal voltage of G-A becomes vL.

Therefore, the output Q is at the level of vH.

In the fifth step, the state returns to the first step (initial state).

From the above explanation, in order for the input signal CP to become vL twice, (
1st step, 3rd step) Output terminal C1 of game C,
It can be understood that the voltage of C2, that is, the output Q becomes VH only once.

In Figure 4, output terminals B1゜B2AC of game) B and C
1 and C2 do not necessarily have to be orthogonal to the wiring 5, but may be parallel to the wiring 5 as shown in FIG.

FIG. 8 shows a modification of FIG. 2.

In this modification, a transistor 8 is inserted between the input terminal of gate B and the cathode of diode 3, and a transistor 9 is inserted between the input terminal of gate C and the cathode terminal of diode 4.

These transistors 8 and 9 are delay transistors for intentionally lengthening the rise time of the currents supplied to the input terminals of the gates B and C, respectively, to prevent malfunctions of the F and F circuits.

A plan view when the F and F circuits shown in FIG. 8 are integrated using IIL is shown in FIG. 9, and the circuit corresponding to FIG. 9 is shown in FIG. 10.

Regarding FIG. 10, the reference numerals corresponding to FIG. 3 are attached and the explanation is omitted. For FIG. 9, the reference numerals corresponding to FIG. 10 are attached and the explanation is omitted. Corresponding symbols are attached and explanations are omitted.

The present invention is not simply applied to F, F circuits using IIL.

TTL
It is also applied to F and F circuits using Logic).

FIG. 11 shows an example of an F, F circuit using TTL.

Transistor TR constituting F, F circuit using TTL
0, TR1o.

Both TR11 and TR12 have multiple inputs and one output.

Logic gate A is transistor TR9, base input resistor R
1. Inverter TR13, inverter collector resistance R
It consists of 2.

Another logic gate B. C and D also have the same configuration as logic game A, so their explanation will be omitted.

Diode 3 connects one input terminal of gate A and gate B
is connected to one input terminal of the
An input signal NB is supplied to the one input terminal of the gate B.

Diode 4 is coupled between one input terminal of gate C and one input terminal of gate D with the polarity shown.

An inverter transistor TR is connected to the bases of the transistors TR9, TR1o, TR11 and TR12 via a resistor R1.3. TRI4. TE10. A drive voltage VCC is coupled to the collector of TR16 via a resistor R2.

Output Q is derived from the collector of inverter transistor TR15.

According to the present invention described in detail above, a flip-flop can be realized with an extremely simple configuration, and when integrated into an integrated circuit, the integration density can be dramatically improved because the number of gates and wires is small. Their small number allows operation at high frequencies.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional master-slave type flip-flop logic circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is an embodiment of the embodiment of FIG. 2. FIG. 4 is a plan view of the integrated circuit using IIL, FIG. 5 is a timing chart for explaining the operating principle of the circuit in FIG. 2, and FIG. 2 is a circuit diagram used to explain the operating principle of the circuit, FIG. 7 is a plan view showing a modification of the circuit in FIG. 3, FIG. 8 is a circuit diagram showing another embodiment of the present invention, and FIG. FIG. 10 is a plan view showing an example of the circuit when it is integrated, FIG. 10 is a circuit diagram specifically showing the configuration of the circuit shown in FIG. 9, and FIG. 11 is a circuit diagram showing still another embodiment of the present invention. be. A, B, C, D...Gate, 3, 4...
diode.

Claims (1)

[Claims] 1 comprises four gates that perform the negation of AND, the first output terminal of the first gate is connected to the input terminal of the second gate,
A first output end of the second gate is connected to an input end of the first gate, and a first output end of the third gate is connected to an input end of the fourth gate. a first output end of the gate is connected to an input end of the third gate;
A second output of the first gate is connected to an input of a third gate, a second output of the second gate is connected to an input of a fourth gate, and the fourth a first diode such that a second output terminal of the gate is connected to an input terminal of the first gate, and a forward direction is from the input terminal of the first gate toward the input terminal of the second gate; is connected, and a second diode is connected in a forward direction from the input end of the fourth gate to the input end of the third gate, and the input signal is input to the input end of the second gate. A flip-flop circuit, characterized in that the flip-flop circuit is configured to supply an output signal and take out an output signal from a second output terminal of the third gate.