JPS5828775B2 - Multi-stage frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit, and in particular to an I2L circuit as a logic element.
(Integrated Injection Log
ic).

2L is a recently developed logic element, and its equivalent circuit is shown in FIG.

That is, an inverter NPN transistor T1 and an injector PNP l-transistor T2 whose collector is connected to the base of this transistor T1 and whose base is connected to the emitter.
It consists of

Specifically, the inverter transistor T1 is constituted by a so-called reverse structure particle transistor in which the emitter and collector of a normal planar transistor are reversed, and the injector transistor T2 has its collector and base connected to the inverter transistor T1.
It is configured as a lateral structure transistor with the base and emitter shared.

Then, an external power supply (+VEE) is applied to the emitter of the injector transistor T2, and this transistor T
Logic operation is performed by supplying charge to the base of the inverter transistor T1 via the inverter transistor T1.

In the example shown in Fig. 1, the inverter transistor T1 is of a multi-collector type and the two signal output terminals 0UT1, 0
UT2 is provided, and three signal input terminals IN1--N3 are provided, and in the following explanation, such 2L will be represented by the logic symbol in FIG. 2.

In such an integrated circuit using 2L, a frequency divider circuit is often used.

Figures 3 and 4 show a conventionally known frequency divider circuit for I2.
An example configured with L is shown below.

In both cases, an output Q of the H frequency of the input clock pulse CP is obtained.

The circuit of FIG. 3 uses six gates 01 to G6, while the circuit of FIG. 4 has four gates of 01□ to G140, which is superior in terms of integration.

However, in the circuit shown in FIG. 4, the voltage rise time at the gate input section is set so that G11 is shorter than G1, and G14 is shorter than G03.

By cascading multiple stages of the above-described X frequency divider circuits, high frequency pulses can be made into low frequency pulses.

For example, in the case of integrated circuits for watches, most of them are 32.768K.
IH2 pulses are obtained by using Hz as a reference frequency and connecting 15 stages of X frequency divider circuits.

When using such a multi-stage frequency divider circuit, especially in something like a wristwatch, it is important to increase the integration density and at the same time reduce power consumption as much as possible. Attempts have been made to control the supplied current.

This invention was made in view of the above points, and I2L
The present invention provides a multi-stage frequency divider circuit that uses low power consumption and can be highly integrated.

The multi-stage frequency divider circuit according to the present invention is obtained by connecting multiple stages of frequency divider circuits each consisting of gates using 2L. A feature is that the X frequency divider circuits used in subsequent stages have a different configuration.

That is, the first frequency divider circuit used in the first stage or the first several stages uses the first to fourth gates, and inputs the outputs of the second and first gates to the inputs of the first and second gates, respectively. feeding back the outputs of the fourth and third gates to the inputs of the third and fourth gates, respectively, and inputting the outputs of the first and second gates to the third and fourth gates, respectively; and third and fourth
The output of the 0 gate is fed back to the input of the second and first gates, respectively, and the clock pulses input to the first and second gates and the clock pulses input to the third and fourth gates are reversed. It operates as a phase.

In addition, the second frequency dividing circuit used in the subsequent stages is the fifth to
Using the eighth gate, the outputs of the sixth and fifth gates are fed back to the inputs of the fifth and sixth gates, respectively.
The outputs of the 8th and 7th gates are fed back to the inputs of the gates, respectively, the outputs of the 5th gate are inputted to the 7th and 8th gates, and the outputs of the 8th gate are fed back to the inputs of the 5th gates. The rise times of the fifth and eighth gate input sections are set to be shorter than the rise times of the sixth and seventh gate input sections, respectively.

Although the first frequency divider circuit has a larger number of wires than the second frequency divider circuit, it consumes less power than the second frequency divider circuit when compared at the same operating frequency.

The reason is as follows.

(2) As mentioned above, the rise time, that is, the operating speed of the 2L gate is determined by the current supplied by the injector, and the operating speed becomes faster by increasing the supplied current.

By the way, the operating speed of a logic circuit using 2L gates is determined by the slower operating speed of its constituent gates.

Therefore, if we compare a first X frequency divider circuit that uses the same gates for all gates and a second X frequency divider circuit that uses different gate rise times to operate at the same speed, the second , the supply current of the gate with a slow rise must be the same as that of the first frequency divider circuit, and the supply currents of the other gates must be set larger than these to differentiate the rise times.

In other words, the second X frequency divider circuit must consume less power than the first X frequency divider circuit configuration at the cost of reducing the number of wires.

Examples of the present invention will be described in detail below.

FIG. 5 is an example of the first frequency dividing circuit, in which the first gate G2
1, a second gate G2□, a third gate G23, and a fourth gate G24.

Clock pulses CP, CP having opposite phases to each other are supplied to gates G26. It is input via G25.

The pulse waveform of each gate input section is as shown in FIG.

This frequency divider circuit has the advantage of operating with power consumption of about H compared to conventional circuits of the same type.

However, if you try to connect multiple stages of frequency divider circuits to this,
The following problems arise.

That is, as is clear from the pulse waveform in FIG.
Fourth gate G23. The output of G24 cannot be used as it is as the clock pulses CP and CP of the next stage.

Therefore, for example, the output of the first gate G21 is the output of the fourth gate G24, and the output of the second gate G2□ is the output of the third gate G24.
By connecting each to the output of gate G23 of
Change the pulse waveform.

If the frequency dividing circuits are connected in cascade to the first circuit in this way, a configuration as shown in FIG. 7 will be obtained, and the number of wiring lines will be extremely large.

Therefore, the first frequency divider circuit is used in the first stage or the first several stages of the multistage frequency divider circuit, which have a high frequency and a large power consumption.

In the latter stage, where the frequency is low and power consumption is not much of a problem, a second frequency divider circuit is used, which consumes more power than the first frequency divider circuit, but whose wiring is very simple.

An example of the second frequency dividing circuit is shown in FIG.

This is a slightly modified circuit of FIG. 4, with a fifth gate G31, a sixth gate G3□, and a seventh gate G3.
3. Consisting of the eighth gate G34.

As in the case of FIG. 4, the rise time of the gate input section is set so that the rise time of the fifth gate G31 is shorter than that of the sixth gate G32, and that of the eighth gate G34 is shorter than that of the seventh gate G33. It is.

The clock pulse CP is sent to the eighth gate G34 via the gate G26, and the clock pulse CP having the opposite phase is sent to the eighth gate G34 via the gate G26.
-035 to the fifth and sixth gates G3□ and G3□.

In order for this second X frequency divider circuit to operate normally, there must be a relationship between clock pulses CP and CP as shown in FIG. 9, that is, a state in which both clock pulses are at a low level.

The period when the clock pulse is at a high level is shorter than the time when it is at a low level, and power consumption is lower when the clock pulse is at a lower level.

This means that the output Q of the first X frequency divider circuit explained earlier,
The clock pulses CP and C of the second frequency dividing circuit are
This means that it is very advantageous to use it as P.

FIG. 10 shows an embodiment in which the first X frequency divider circuit shown in FIG. 5 is used in the first stage, and the second X frequency divider circuit shown in FIG. 8 is connected thereafter.

With this configuration, as is clear from the previous explanation, the overall power consumption can be kept low by using the first X divider circuit that operates with low power in the first stage with a high operating frequency. Furthermore, by using the second frequency divider circuit in the second and subsequent stages, the number of wiring lines is greatly reduced compared to that in FIG. 7, and high-density integration is possible.

Therefore, this multistage frequency divider circuit is very useful especially as an integrated circuit for wristwatches.

In the above embodiment, the example shown in FIG. 8 was used as the second X frequency dividing circuit.

On the other hand, it is also effective to use the circuit shown in FIG. 4 as the second X frequency dividing circuit, although the power consumption increases slightly.

The pulse waveform of FIG. 6 is also advantageous for the circuit of FIG. 4 in terms of reducing power consumption.

FIG. 11 shows an example in which the first X frequency divider circuit in FIG. 5 is used as the first stage, and the second frequency divider circuit in FIG. 4 is used as the second frequency divider circuit in the second and subsequent stages.

In addition, the present invention can be modified in various ways without departing from its spirit.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of ■2L, Figure 2 is a diagram showing gate logic symbols using I2, and Figures 3 and 4 are ■2L.
A diagram showing an example of the configuration of an X frequency divider circuit using gates, FIG. 5 is a diagram showing an example configuration of the first frequency divider circuit used in an embodiment of the present invention, and FIG. 7 is a diagram showing a frequency dividing circuit in which the frequency dividing circuits shown in FIG. 5 are connected in multiple stages; FIG. Figure 9 shows the clock pulse waveform.
FIG. 10 is a diagram showing a multi-stage frequency divider circuit according to one embodiment of the present invention, and FIG. 11 is a diagram showing a multi-stage frequency divider circuit according to another embodiment. G21...First gate, G2゜...
Second gate, G23...Third gate, G2
4...Fourth gate, G3,...Fifth
Gate, G3□・・・6th gate, G33・
...7th gate, G34...8th gate.

Claims (1)

[Claims] 1 A frequency dividing circuit is connected in multiple stages, consisting of an inverter transistor, a gate using a logic element consisting of an inverter transistor, a collector connected to the base of this transistor, and a complementary injector transistor with the base connected to the emitter. In a multi-stage frequency divider circuit, the first frequency divider circuit is
~Using the fourth gate, the outputs of the second and first gates are fed back to the inputs of the eleventh and second gates, respectively, and the outputs of the fourth and third gates are fed back to the inputs of the third and fourth gates, respectively. At the same time, the output of the 11th second gate is input to the third and fourth gates, and the outputs of the third and fourth gates are input to the second and first gates, respectively. The clock pulse that is fed back and input to the first and second gates and the third
, the clock pulses input to the fourth gate are operated with opposite phases to each other, and the second frequency dividing circuit operates as the clock pulse input to the fourth gate.
~Using the eighth gate, the outputs of the sixth and fifth gates are fed back to the inputs of the fifth and sixth gates, respectively, and the outputs of the eighth and seventh gates are fed back to the inputs of the seventh and eighth gates, respectively. The output of the gate is fed back, the output of the fifth gate is inputted to the seventh and eighth gates, and the output of the eighth gate is fed back to the input of the fifth gate. The rise time of the gate input section is set to be shorter than the rise time of the sixth and seventh gate input sections, respectively, and the first H frequency divider circuit is used in the first stage or the first several stages. , a multi-stage frequency divider circuit characterized in that a second frequency divider circuit is used in subsequent stages.