JPS626535A - Counter circuit - Google Patents

Abstract

PURPOSE:To constitute a counter circuit by applying the information of the counter of pre-stage to a carry control circuit of the next stage via an AND circuit constituting a carry control circuit without increasing the fan-out umber of the counter. CONSTITUTION:Outputs QA, QA of a counter 71 of the 1st stage are fed only to a carry control circuit 101, and the outputs of AND circuits 111, 112 constituting the carry control circuit 101 are inputted respectively to AND circuts 113, 114 of the carry control circuit 102. Through the constitution above, the input number inputted to the AND circuits constituting the carry control circuit of the final stage is only the output of the counter of the pre-stage, the output of the carry control circuit of the pre-stage and a clock and the input signal number of the carry control circuit of the final stage is only the output of the counter of the pre-stage, the output of the carry control circuit of the pre- stage and a signal having a number added to a clock signal to them. Thus, even when the counter is constituted by multi-stage, the increase in the input number of the carry control circuit is suppressed and said circuit is suited for integrated circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a counter circuit.
integrated injection logic
) The present invention relates to a counter circuit suitable for integration when configured as a circuit.

[Summary of the invention]

In this invention, for example, as shown in FIG. 11, a carry control circuit 10. The clock CK is input to the husbands of the AND gates 111 and 112, and the positive phase output of the counter 71,
Input the reverse phase output respectively. In this case, the above AND circuit 11
The logical sum of the outputs of 1 and 112 is used as a clock for the counter 7□ and as a clock for the carry control circuit 102 at the primary stage, and the outputs of the AND circuits 111 and 112 are used for the carry control circuit 102 at the next stage. Let them input.

As a result, the carry control circuit can have the same circuit configuration except for the final stage, and a counter circuit suitable for the 12L configuration can be provided.

[Technical background of the invention and its problems]

The general K12L circuit is attracting attention as an LSI technology because it operates at low voltage, has low power consumption, and can coexist with bipolar circuits. Second
The figure is a circuit diagram showing the basic circuit of l2L.
It is an NP transistor. The injector current IEP to the transistor Qp is supplied from an external source to the stabilizing resistor R9.
The entirety of the voltage is supplied to the emitter electrode of the transistor Q. Since the base of transistor Q is grounded, the collector current ICp of transistor Q is connected to input terminal B.
When Cr51 . Cnz,C
Both ns become conductive.

Next, input terminal B is grounded, and collector current I of transistor Qp. , to the ground, no base current is supplied to the transistor Qn, so that the transistors Cnl, Cn2 . Cn3 blocks. In this case, the operating speed of the circuit is determined by the injector current supplied to the emitter electrode of the transistor Qp.

determined by

FIG. 3 is a circuit diagram showing a conventional counter circuit, for example, an up/down counter circuit used for accumulation. In the figure, a clock CK is applied to terminal 1,
An up/down control signal is applied to terminal 2. The signals applied to these terminals 1 and 2 are applied to a clock control circuit 3, which outputs an up-count clock and a down-count clock to its output terminals 4.5, respectively.

Both count clocks mentioned above are carried by the carry control circuit 61 r
62+63, respectively, and the carry control circuits 61,
The outputs of 6□ and 63 are respectively T-type flip-flops 71.7
The clock CK input to the terminal 1 is applied to the clock terminal of the T-type 7 lip-flop 71.

As can be seen from the timing chart shown in Figure G4, the counting operation for the above counter is based on the clock C applied to terminal 1 when terminal 2 is at a high level (Figure 4(b)).
K (FIG. 4(a)) is counted up, and conversely, when the level of the terminal 2 is low, it is counted down. Since the clock CK (Fig. 4(a)) is simply applied to the first-stage T-type flip-flop 71 constituting the counter, its output QA (terminal 81) is as shown in (Fig. 4(C)). As the output waveform becomes The signals (QB, QB) at the output end of 7□ are applied to the next stage carry control circuit 73, and the output terminal 83 of the third stage flip-flop 73 has the output shown in FIG. 4(e). Similarly, the final stage 7 lip-flop 74 obtains the output shown in Figure 4 (0).

Incidentally, FIG. 4 (ω, (h)) shows an up-count clock and a down-count clock derived from terminals 4 and 5, respectively.

In the conventional counter circuit with the above configuration, the fine-out number of the first-stage counter and the fan-out number of the second-stage counter are different, and the current consumed by the output of the first-stage counter is higher than that of the second-stage counter. This makes it difficult to connect counters in multiple stages.

Furthermore, when the number of input terminals of each of the carry control circuits 61, 62, and 63 differs depending on the number of stages, and an n-stage counter circuit is configured, the AND circuit constituting the carry control circuit connected to the final stage is The number of inputs is ((n-1)+1)=4, which is the sum of the number of outputs (n-1) from the counter at the previous stage and the number of inputs (1) for introducing the clock CK. Therefore, a problem arises in that the number of inputs to the carry control circuit in the subsequent stage increases. Therefore, there is a problem that the chip area increases when integrated. Also,
The conventional counter circuit described above is unsuitable for the I''L configuration.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a counter circuit suitable for integration and also suitable for IZL.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the present invention, and shows an example of a counter circuit in a TTL configuration. Note that parts corresponding to those in FIG. 3 are designated by the same reference numerals, and their explanations will be omitted.

In the circuit shown in FIG. 5, the output (QA, QA) of the first stage counter 71 is applied only to the carry control circuit 10. Further, the outputs of the AND circuits ill and 112 constituting the carry control circuit 101 are respectively input to the AND circuits 113 and 114 of the carry control circuit 102 in the next stage.In this way, the output of the flip 70 is input to the carry control circuit in the next stage. The configuration is such that it is supplied only to the circuit.

That is, the information of the counter in the previous stage is supplied to the carry control circuit in the next stage via the AND circuit in the carry control circuit. With this configuration, the information from the counter in the previous stage is input to the AND circuit in the carry control circuit in the final stage. The only inputs are the output of the counter in the previous stage, the output of the carry control circuit in the previous stage, and the clock.

The number of input signals for the carry control circuit at the final stage is n when the counter circuit is conventionally configured with n stages of counters. It is only necessary to add the output of the control circuit, a clock signal thereto, and a signal indicating the number of runs. Therefore, even when the counter is configured in multiple stages, an increase in the number of inputs to the carry control circuit is suppressed, making it suitable for integration.

Further, regarding the carry control circuit, except for the final stage, the cell configuration is similar, and this aspect is also suitable for integration. That is, since the output of the counter constituting the counter circuit is not wired beyond the next-stage counter, the noise generation is less affected by noise.

FIG. 6 shows an example of a circuit in which the circuit shown in FIG. 5 has an I2L configuration, and parts corresponding to those in FIG. 5 are given the same reference numerals.

In the case of the I2L configuration shown in FIG.
Since the basic unit configuration of I2L is essentially an inverter, it is formed by a circuit including a plurality of inverters. In addition, the symbols corresponding to those in FIG. 5 are attached.
, the number of input terminals of M2R can be reduced compared to conventional counter circuits, and the number of fan-outs for LSB can be reduced.

Furthermore, the carry control circuits 101.10□ can have the same configuration, and when integrated, they can be formed with the same pattern configuration.

That is, in the embodiment of the counter circuit with the I2L configuration shown in FIG. 6, when a one-stage flip-flop, for example, a T-type 7 flip-flop, is configured, the carry control circuit of the (n-1) portion is configured with the same circuit configuration. obtain. Also, the seventh
The figure shows the circuit configuration of a flip-flop forming the counter circuit shown in FIG.

In this case, it is composed of I2L and is formed by a combination K of inverters.

FIG. 8 is a circuit diagram showing another embodiment of the present invention.
An example of a circuit configured with 2L is shown. The embodiment shown in FIG. 8 is basically equivalent to the embodiment shown in FIG.
In this embodiment, the flip-flop constituting the counter circuit is a flip-flop that changes at the rising edge of the clock.

That is, in FIG. 8, the flip-flops 71, 7□7
is formed with the I2L configuration shown in No. 91, and each flip-flop has a circuit configuration in which the state changes at the rising edge of the clock.

Even in this case, the carry control circuit 101.10□ can have the same circuit configuration, and the number of gun-outs for the first stage counter can be reduced. [Effects of the Invention] As described above, this According to the counter circuit according to the invention, the counter circuit can be constructed without increasing the fan-out number of the counter, and when integrated, the chip area can be reduced.

For example, when a counter circuit is configured with an n-stage counter, the carry control circuit can have the same circuit configuration for (n-2) stages excluding the final stage, and when integrated, the same circuit configuration can be used. It can be formed into a cell shape. This eliminates the need for unnecessary routing of wiring, and prevents the influence of unnecessary signal noise on circuit mounting.

The counter circuit according to the invention is also suitable for an I2L configuration.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the outline of this invention, Figure 2 is an I2L
3 is a circuit diagram showing a conventional counter circuit, FIG. 4 is a timing chart for explaining the operation of FIG. 3, and FIGS. The circuit diagrams illustrating examples, FIG. 71 and FIG. 9 are circuit diagrams showing counters constituting the counter circuit. 71.7□t73-74...Counter, 108.10
□、・】0. ...Carry control circuit. (LSB) (MSB) Fig. 1 P Rp (LSB) (MSB) 3rd
Figure @4 Figure b Prisoner (n-+) Figure 6 Figure 8

Claims (1)

[Claims] A plurality of clock terminals each having a clock terminal and a positive phase output terminal and a negative phase output terminal.
a value counter; and a plurality of carries, the outputs of which are applied to respective clock terminals of these counters, the positive phase output and negative phase output of the preceding counter are input, and first and second clocks are applied. A control circuit, and a signal obtained by logically processing the positive phase and negative phase outputs of the counter input to the carry control circuit using the first and second clocks is input to the next stage carry control circuit, and the signal is input to the next stage carry control circuit. A counter circuit characterized in that a carry control circuit except for 1 has the same circuit configuration.