JP2001264345A - Rotation sensor signal processing ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To scale down the internal circuit of a rotation sensor signal processing IC capable of dividing a pulse signal from a rotation sensor by a plurality of numbers of division including numbers of division except the n-th power of 2. SOLUTION: The IC 31 comprises three flip-flops (F1-F3, hereafter) and is provided with a binary counter 35 with a pulse signal from the rotation sensor 3 as a clock, output terminals P1-P5 for outputting signals obtained by dividing the pulse signal by the numbers of division of 2-8, and means 41 and 45 to reset the F1-F3 at the next rising of the pulse signal when HIGH is inputted to a terminal PR from one of the output terminals P1-P5. The levels of the output terminals P2-P5 corresponding to the numbers of division except the n-th order of 2 are set in such a way as to become high for the first time when the pulse signal rises by the number smaller by one than the number of division of the output terminal after the reset of the F1-F3. A corresponding dividing signal is outputted from the output terminal of the IC 31 when any output terminal is connected to the terminal PR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotation sensor signal processing IC mounted on an electronic control unit for a vehicle together with a microcomputer, for dividing a pulse signal from a rotation sensor and outputting the divided signal to the microcomputer. is there.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, an electronic control unit (vehicle electronic control unit) 1 mounted on a vehicle has a pulse output from a rotation sensor 3 such as a transmission rotation sensor or a vehicle speed sensor. The signals are waveform-shaped by the signal processing circuit 5 and input to the microcomputer 7, and various other signals are also input to the microcomputer 7 via the input circuit 9. The microcomputer 7 performs various electric loads 11 based on the pulse signal from the rotation sensor 3 and other various signals.
And outputs a control signal for energizing the drive circuit.
When the corresponding electric load 11 is energized in accordance with a control signal from the microcomputer 7, transmission control, engine control, and cruise control (constant speed traveling control) are performed.
And so on.

Here, generally, a rotation sensor 3 such as a transmission rotation sensor or a vehicle speed sensor is a rotating body to be detected (specifically, in the case of a transmission rotation sensor, a gear or a power shaft in a transmission, etc.
A pulse-shaped signal is output each time a wheel or a wheel shaft of a vehicle speed sensor rotates by a predetermined angle, and the signal output from the rotation sensor 3 (that is, the pulse signal) is output. The frequency is proportional to the rotation speed of the rotating body.

Then, in the vehicle electronic control unit 1,
The microcomputer 7 executes an interrupt process every time a pulse signal input from the rotation sensor 3 via the signal processing circuit 5 rises or falls, and determines the number of rotations to be detected (in the case of a vehicle speed sensor, the vehicle speed). ) Is calculated. More specifically, in the interrupt processing started at the rising edge or the falling edge of the pulse signal, the time at that time is stored, and the period of the pulse signal is calculated from the difference between the currently stored time and the previously stored time. By multiplying the cycle by a constant set based on the wheel diameter, gear ratio, etc.
It calculates the vehicle speed and the gear speed of the transmission.

In such a vehicle electronic control unit 1, generally, it is necessary to ensure high controllability by quickly and accurately detecting the vehicle speed and the transmission gear rotation speed from a low point in time. For this purpose, it is preferable that the rotation sensor 3 has a large number of pulses output per rotation of the rotating body (hereinafter referred to as an output pulse number).

That is, as shown in FIGS. 6A and 6B, when the rotation speed of the rotating body is the same, the rotation speed calculation in the microcomputer 7 becomes more significant when a rotation sensor having a larger number of output pulses is used. The timing interval, that is, the rotation speed determination time TH until the latest rotation speed can be ascertained, is shortened. As a result, precise control can be performed from the time when the rotation speed is low. Note that the calculation of the vehicle speed is still the same as the calculation of the rotation speed of a rotating body such as a wheel or a wheel axle. This is the same in the following description.

However, when a rotation sensor having a large number of output pulses is used, in a region where the number of rotations is high, the microcomputer 7 is not used.
Interrupts occur frequently, and the execution speed of other control processing is reduced. That is, as shown in FIGS. 7A and 7B, if the number of output pulses of the rotation sensor is the same, the higher the number of rotations, the shorter the interval of the interrupt processing timing in the microcomputer 7 becomes. The ratio of the execution time of the interrupt processing to the processing time (interrupt processing time / overall processing time) increases, so that there is less room to perform other control processing.

Therefore, conventionally, in the case of a vehicle that emphasizes controllability when the rotation speed (vehicle speed or transmission gear rotation speed) is high, a rotation sensor having a small number of output pulses may be used as the rotation sensor 3, In the signal processing circuit 5 shown in FIG. 5, a frequency dividing circuit for dividing the frequency of the pulse signal from the rotation sensor 3 and outputting it to the microcomputer 7 is provided to reduce the frequency of activation of the interrupt processing in the microcomputer 7. . Then, in the case of a vehicle that emphasizes controllability at a higher rotation speed, the frequency division number (frequency division ratio) by the frequency dividing circuit is set to a larger value accordingly.

That is, in the vehicle electronic control unit 1, the rotation sensor 3 itself is changed between the vehicle that emphasizes the controllability at the time of high rotation and the vehicle that emphasizes the controllability at the time of low rotation, or the signal processing circuit 5 For example, the frequency division number (frequency division ratio) for the pulse signal was changed.

[0010]

By the way, if the number of output pulses of the rotation sensor is changed for each type of vehicle,
The number of types of rotation sensors increases, and it becomes impossible to achieve cost reduction by mass production.

Further, instead of always using the same type of rotation sensor, if the frequency division number for the pulse signal in the signal processing circuit 5 is changed for each type of vehicle, the electronic control device 1 can be downsized. The signal processing circuit 5 is connected to an IC
In the case of a (semiconductor integrated circuit), various types of ICs must be manufactured and managed, leading to an increase in cost.

Therefore, a signal processing circuit 5 having a frequency dividing function
The problem described above can be avoided if an IC used as is configured in advance so that the pulse signal can be frequency-divided with a plurality of frequency division numbers as illustrated in FIG. However, in consideration of such an IC, the number of division of 2 n such as division of 2, 4, and 8 can be realized by a binary counter composed of multi-stage flip-flops. In order to realize the above frequency division number, a frequency dividing circuit for each frequency division number is built in the IC, and the internal circuit of the IC cannot be downsized.

More specifically, FIG. 8 shows a waveform of a pulse signal from the rotation sensor 3 which is shaped and the pulse signal after the waveform shaping can be divided by 7 to 2 division numbers. This is a configuration example of the sensor signal processing IC. In such a general circuit configuration, apart from the binary counter 21 composed of three flip-flops, two for dividing by three is used.
A three-divider circuit 23 having three flip-flops is required, and a five-divider circuit 25 and a six-divider circuit 2 each having three flip-flops are used for 5, 6, and 7 frequency division.
The 7 and 7 frequency dividing circuits 29 are required, and a total of 14 flip-flops are required.

The present invention has been made in view of such a problem, and divides a pulse signal from a rotation sensor by any one of a plurality of frequency division numbers including a frequency division number other than 2 n. Another object of the present invention is to reduce the size of an internal circuit of a rotation sensor signal processing IC for outputting to a microcomputer.

[0015]

According to a first aspect of the present invention, there is provided a rotation sensor signal processing IC which is used in an electronic control unit mounted on a vehicle and has a predetermined rotation. A pulse signal having a frequency proportional to the number of rotations of the body is input from a rotation sensor, and a frequency-divided signal obtained by dividing the pulse signal is output to a microcomputer in the electronic control unit.

Here, the rotation sensor signal processing IC according to the first aspect of the present invention divides the pulse signal by a plurality of division numbers including a division number other than 2 n (where n is a positive integer). A plurality of output terminals for outputting each of the frequency-divided signals, a reset input terminal connected to any of the output terminals outside the IC, and a plurality of flip-flops. And a binary counter to which the pulse signal is input as a clock signal at a clock terminal of the loop.

In this rotation sensor signal processing IC, the signal supply means outputs the output of one of the flip-flops constituting the binary counter or the output of two or more of the flip-flops constituting the binary counter. By supplying a signal obtained by combining the logics of the two terminals to each of the output terminals, the level of each output terminal becomes equal to the clock signal (that is, the first stage) after all the flip-flops constituting the binary counter are simultaneously reset. Is changed to a specific level only when the pulse signal input to the clock terminal of the flip-flop rises one less number of times than the frequency division number assigned to the output terminal.

Further, in the rotation sensor signal processing IC according to the first aspect, one of the output terminals is connected to the reset input terminal, and the signal of the specific level is input from the output terminal to the reset input terminal. Reset means gives a reset signal to reset terminals of all flip-flops constituting a binary counter for a time shorter than the shortest cycle of the pulse signal at the next timing when the clock signal rises, Reset the loop.

For this reason, in the rotation sensor signal processing IC according to the first aspect of the invention, if any of the output terminals is connected to the reset input terminal, the output terminal receives the signal from the rotation sensor at a frequency corresponding to the output terminal. A frequency-divided signal obtained by dividing the pulse signal is output. If the configuration of claim 1 is adopted, for example, if the number of flip-flops constituting the binary counter is three, the frequency division number other than 2 n raised to the frequency division of 3, 5, 6, 7 , And all three flip-flops. That is, assuming that the number of flip-flops constituting the binary counter is X, it is possible to realize all frequency division numbers (however, integers) other than 2 to the X power and other than 2 to the n power.

A rotation sensor signal processing IC according to claim 1
In the case where the output of one of the flip-flops constituting the binary counter is supplied as it is to any of the output terminals, if the output terminal is not connected to the reset input terminal, two If the output terminal is connected to the reset input terminal, a divided signal having a division number other than 2 n is output from the output terminal. Is output. In other words, in this case, one output terminal can output a frequency-divided signal having two frequency division numbers.

From this, when the configuration of claim 1 is adopted, if the number of flip-flops constituting the binary counter is X, the frequency division number is an X2 power or less (however, an integer).
, And a plurality of frequency division numbers including frequency division numbers other than 2 n can be realized with a very small circuit configuration.

Next, the rotation sensor signal processing IC according to claim 2 is also used in an electronic control device mounted on a vehicle,
A pulse signal having a frequency proportional to the rotation speed of a predetermined rotating body is input from the rotation sensor, and a frequency-divided signal obtained by dividing the pulse signal is output to a microcomputer in the electronic control unit. .

Here, the rotation sensor signal processing IC according to claim 2 includes a plurality of output terminals for respectively outputting divided signals obtained by dividing the pulse signal by a plurality of division numbers, and A reset input terminal connected to one of the output terminals and the outside of the IC, and the pulse signal or a signal obtained by dividing the pulse signal includes a plurality of flip-flops input as a clock signal to a clock terminal. And a shift register in which a high-level signal is input to the data terminal of the first-stage flip-flop.

In this rotation sensor signal processing IC, the signal supply means supplies the outputs of the same number of flip-flops as the output terminals among the flip-flops constituting the shift register to each of the output terminals. By doing so, the level of each output terminal becomes different from the number of times the clock signal (ie, the signal input to the clock terminal of each flip-flop) changes after the flip-flops constituting the shift register are simultaneously reset. Only when it starts up, it changes to a specific level for the first time.

Further, in the rotation sensor signal processing IC according to the second aspect, one of the output terminals is connected to the reset input terminal, and the signal of the specific level is input from the output terminal to the reset input terminal. And reset means, at the next timing when the clock signal rises, applies a reset signal to the reset terminals of all flip-flops constituting the shift register for a time shorter than the shortest period of the pulse signal, Reset the loop.

Therefore, in the rotation sensor signal processing IC according to the second aspect, if any one of the output terminals is connected to the reset input terminal, a frequency-divided signal obtained by dividing the pulse signal from the rotation sensor is output from the output terminal. The frequency division signals are output, and the frequency division signals having different frequency division numbers are output for each output terminal.

According to the second aspect of the present invention, for example, the number of flip-flops constituting the shift register and the number of output terminals are both seven, and the pulse signal from the rotation sensor is supplied to each flip-flop. If a clock signal is input to the clock input terminal of
Seven frequency division numbers such as 2, 3, 4, 5, 6, 7, and 8 can be realized by the seven flip-flops. That is, assuming that the number of flip-flops constituting the shift register is Y, it is possible to realize all integer division numbers equal to or less than (Y + 1).

Further, for example, the number of flip-flops and the number of output terminals constituting the shift register are both seven, and a signal obtained by dividing the pulse signal from the rotation sensor by two is applied to the clock input terminal of each flip-flop. If input as a clock signal, 4, 6, 8, 10,
Seven frequency division numbers such as 12, 14, and 16 can be realized by the seven flip-flops.

Therefore, even with the rotation sensor signal processing IC according to the second aspect, a plurality of frequency division numbers including frequency division numbers other than 2 n can be realized with a small-scale circuit configuration.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A rotation sensor signal processing IC according to an embodiment of the present invention will be described below with reference to the drawings. The rotation sensor signal processing IC according to the present embodiment includes:
In the vehicle electronic control device 1 having the configuration illustrated in FIG.
It is used as a signal processing circuit 5 for shaping the waveform of the pulse signal from the rotation sensor 3, further dividing the frequency, and outputting it to the microcomputer 7.

FIG. 1 is a circuit diagram showing a configuration of a rotation sensor signal processing IC 31 according to a first embodiment to which the invention of claim 1 is applied. As shown in FIG. 1, the rotation sensor signal processing IC 31 of the first embodiment includes a pair of signal input terminals P + and P− to which a pulse signal from the rotation sensor 3 is input.
And the IC 31 via the signal input terminals P + and P-.
A waveform shaping circuit 33 that shapes and outputs a pulse signal taken into the device into a rectangular pulse signal, and a pulse signal S that has been waveform-shaped by the waveform shaping circuit 33 is divided by a plurality of frequency division numbers. It comprises five output terminals P1 to P5 for outputting the divided signals to the microcomputer 7 and a reset input terminal PR connected to any of the output terminals P1 to P5 outside the IC 31. ing.

In this embodiment, the rotation sensor 3
Each time a rotating body to be detected such as a vehicle wheel or a transmission gear rotates by a predetermined angle, the potential of one output terminal NT- with respect to the other output terminal NT + changes in a pulsed manner. The output terminals NT + and NT− of the rotation sensor 3 are electrically connected to the signal input terminals P + and P− of the IC 31, respectively.
One output terminal NT- of the rotation sensor 3 is connected to the IC 31
Is connected to the ground potential (ground) inside.

The waveform shaping circuit 33 divides the power supply voltage supplied to the comparator 33a and the IC 31 and applies the divided voltage to a non-inverting input terminal (+ terminal) of the comparator 33a. And the voltage dividing resistors Ra and Rb which are input as the following. In the waveform shaping circuit 33, the comparator 33a outputs a high-level signal when the potential of the signal input terminal P + connected to the output terminal NT + of the rotation sensor 3 is lower than the threshold voltage Vth. Thereby, the pulse signal from the rotation sensor 3 is shaped into a rectangular pulse signal. That is,
The pulse signal S after the waveform shaping is output from the comparator 33a.

On the other hand, in the rotation sensor signal processing IC 31 of the first embodiment, the pulse signal from the rotation sensor
It is configured so that the frequency is divided by eight different frequency division numbers. The output terminal P1 is a terminal for outputting a frequency-divided signal obtained by dividing the pulse signal by two, and the output terminal P2 is for outputting either the frequency-divided signal or the frequency-divided signal. The output terminal P3 is a terminal for outputting either the divide-by-8 signal or the divide-by-5 signal, and the output terminal P4 is a terminal for outputting the divide-by-6 signal. The output terminal P5 is a terminal for outputting a divide-by-7 signal.

Next, the rotation sensor signal processing IC 31 of the first embodiment includes three flip-flops (specifically, D-type flip-flops with reset terminals) F1 to F3.
A binary counter 35, an AND gate 37 to which the Q output (output of the Q terminal) of both the first stage (first stage) and the third stage flip-flops F1 and F3 of the binary counter 35 are input, and a binary counter 35 second stage and 3
And an AND gate 39 to which each Q output of both flip-flops F2 and F3 of the stage is input. The binary counter 35 sets the flip-flops F1 to F3 having the data terminal (D) and the Q-bar terminal connected to each other, and the Q-bar terminal of the preceding flip-flop to the clock terminal (CK) of the next-stage flip-flop. It is intended to be connected.

The pulse signal S after waveform shaping is input as a clock signal to the clock terminal of the flip-flop F1 at the first stage of the binary counter 35. Also,
The Q terminal of the first-stage flip-flop F1 is connected to the output terminal P1 by internal wiring, the Q terminal of the second-stage flip-flop F2 is connected to the output terminal P2 by internal wiring, and the Q terminal of the third-stage flip-flop F3. The terminal is connected to the output terminal P3 by internal wiring. Further, the output terminal of the AND gate 37 is connected to the output terminal P4 by internal wiring.
And the output terminal of the AND gate 39 is connected to the output terminal P5 by an internal wiring. In the first embodiment, each of the internal wirings and the AND gates 37 and 39 correspond to a signal supply unit.

Further, the rotation sensor signal processing IC 31 of the first embodiment includes a flip-flop 41 having a data terminal connected to a reset input terminal PR, and a reset input terminal P
R and a resistor 43 for pulling down the data terminal of the flip-flop 41 to the ground potential;
A delay circuit 45 is provided which delays the bar output (output of the Q bar terminal) by a predetermined delay time T shorter than the shortest cycle of the pulse signal from the rotation sensor 3 and provides the result to the reset terminal of the flip-flop 41. .

The pulse signal S after waveform shaping is input to the clock terminal of the flip-flop 41 as a clock signal, and the Q bar terminal of the flip-flop 41 is connected to all the flip-flops F1 constituting the binary counter 35. To F3 reset terminals.
In the first embodiment, the flip-flops 41,
The resistor 43 and the delay circuit 45 correspond to the reset unit according to the first aspect.

Next, the operation of the rotation sensor signal processing IC 31 configured as described above will be described. First, when the reset input terminal PR is not connected to any of the output terminals P1 to P5 and is in an open state, from the output terminal P1,
As shown in FIG. 2A, a signal obtained by dividing the pulse signal S after the waveform shaping by 2 (divided by 2 signal) is output, and is output from the output terminal P2.
A signal (frequency-divided signal) obtained by dividing the pulse signal S by 4 as shown in FIG. 2B is output, and a signal (frequency-divided by 8) obtained by dividing the pulse signal S by 8 as shown in FIG. Frequency signal) is output. This is due to the original operation of the binary counter 35.

On the other hand, for example, if the output terminal P2 is connected to the reset input terminal PR, the output terminal P2 outputs a signal obtained by dividing the pulse signal S by three as shown in FIG. Signal) is output. More specifically, first, the level of the output terminal P2 is set to all flip-flops F1 to F3 constituting the binary counter 35.
Is reset to the high level as the specific level only when the pulse signal S input as the clock signal to the clock terminal of the first-stage flip-flop F1 rises twice after resetting. This is because the Q output of the second-stage flip-flop F2 is supplied to the output terminal P2.

When a high level signal is input from the output terminal P2 to the reset input terminal PR, the pulse signal S
The next time it starts up, flip-flop 4
The Q bar output of 1 becomes low level, all the flip-flops F1 to F3 constituting the binary counter 35 are reset, and accordingly, the output terminal P2 returns from high level to low level. Then, thereafter, the delay circuit 45
When the delay time T has elapsed, the flip-flop 41 is reset by the output of the delay circuit 45, and the Q-bar output of the flip-flop 41 returns to the high level, whereby the reset of the flip-flops F1 to F3 is released. You.

That is, if the output terminal P2 is connected to the reset input terminal PR, as shown in FIG. 2D, when the output terminal P2 goes to a high level, the delay time T after the next rise of the pulse signal S is reached. While the Q of the flip-flop 41
The bar output becomes low level as a reset signal for the binary counter 35, and the flip-flop F1
To F3 are reset, whereby the output terminal P2 returns to a low level.

When the pulse signal S rises twice after the reset of the flip-flops F1 to F3 is released, the output terminal P2 changes to the high level again, and at the next timing when the pulse signal S rises, By the operation of the flip-flop 41 and the delay circuit 45, the flip-flops F1 to F3 are reset again and the output terminal P
2 returns to the low level.

By repeating such an operation, the level of the output terminal P2 rises once every three rises of the pulse signal S. As a result, a three-frequency-divided signal is output from the output terminal P2. It is. next,
When the output terminal P3 is connected to the reset input terminal PR, the output terminal P3 outputs the pulse signal S as shown in FIG.
Is output as a signal (divided by 5).

That is, since the Q output of the third-stage flip-flop F3 is supplied to the output terminal P3, the level of the output terminal P3 becomes the pulse signal S after the flip-flops F1 to F3 are reset. When it rises four times, it changes from a low level to a high level. And
When a high-level signal is input from the output terminal P3 to the reset input terminal PR, the flip-flop is turned on at the next rising edge of the pulse signal S, just as when the output terminal P2 is connected to the reset input terminal PR. 41
And the operation of the delay circuit 45, the flip-flop F1
To F3 are reset, and the output terminal P3 returns to the low level. Thereafter, when the pulse signal S rises four times after the flip-flops F1 to F3 are reset, the output terminal P3 changes to high level, and at the next rising timing of the pulse signal S, the flip-flops F1 to F3 are reset and the output terminal By repeating such an operation that P3 returns to the low level, a divide-by-5 signal is output from the output terminal P3.

Next, the output terminal P4 is connected to the reset input terminal P
R, the output terminal P4 of FIG.
As a result, a signal obtained by dividing the pulse signal S by 6 (divided by 6 signal) is output. That is, the Q of the first-stage flip-flop F1 is connected to the output terminal P4 by the AND gate 37.
Since the AND signal of the output and the Q output of the third-stage flip-flop F3 is supplied, the level of the output terminal P4 of the pulse signal S rises five times since the flip-flops F1 to F3 were reset. Sometimes, it changes from a low level to a high level. Therefore, when the output terminal P4 is connected to the reset input terminal PR, the pulse signal S becomes 5 after the flip-flops F1 to F3 are reset.
When the pulse signal S rises, the output terminal P4 changes to the high level, and at the next rising timing of the pulse signal S, the flip-flops F1 to F3 are reset and the output terminal P4 returns to the low level.
The output terminal P4 outputs a divide-by-6 signal.

The output terminal P5 is connected to the reset input terminal P
If it is connected to R, its output terminal P5 will
As a result, a signal obtained by dividing the pulse signal S by 7 (divided by 7 signal) is output. That is, since the AND signal of the Q output of the second-stage flip-flop F2 and the Q output of the third-stage flip-flop F3 is supplied to the output terminal P5 by the AND gate 39, the output terminal P5 Changes from a low level to a high level when the pulse signal S rises six times after the flip-flops F1 to F3 are reset. Therefore, when the output terminal P5 is connected to the reset input terminal PR, when the pulse signal S rises six times after the flip-flops F1 to F3 are reset, the output terminal P5 changes to a high level,
The operation of resetting the flip-flops F1 to F3 at the next rising timing of the pulse signal S and returning the output terminal P5 to the low level is repeated, so that a six-divided signal is output from the output terminal P5.

It is desired that the pulse signal from the rotation sensor 3 be divided by any one of 2, 4, and 8 by the rotation sensor signal processing IC 31 of the first embodiment and input to the microcomputer 7. In such a case, the reset input terminal PR is opened, and among the output terminals P1, P2, and P3,
An output terminal corresponding to a desired frequency division number may be connected to an input port of the microcomputer 7.

Further, the pulse signal from the rotation sensor 3 is divided by any one of 3, 5, 6, and 7 to divide
In order to input to the reset terminal PR, the output terminal corresponding to the desired frequency division number among the output terminals P2 to P5 is connected to the reset input terminal PR, and the output terminal connected to the reset input terminal PR is connected to the microcomputer. 7 input port.

According to the rotation sensor signal processing IC 31 of the first embodiment, three flip-flops F1 to F1
By using the binary counter 35 composed of F3, all seven frequency division numbers equal to or smaller than 2 3 can be realized.
The circuit scale can be made very small as compared with the circuit configuration shown in FIG.

According to the rotation sensor signal processing IC 31 of the first embodiment, it is not necessary to provide a logic circuit for switching the frequency division number. In particular, a logic circuit that internally switches the frequency division number tends to be complicated, but such a logic circuit is unnecessary, which is particularly advantageous in terms of reducing the circuit scale.

Furthermore, in the rotation sensor signal processing IC 31 of the first embodiment, only one reset input terminal PR is required for switching the frequency division number, and an increase in the number of terminals is minimized. Can be. In the rotation sensor signal processing IC 31 of the first embodiment, the output terminal P1
Is connected to the reset input terminal PR, the output terminal P
1 outputs a frequency-divided signal. This is the output terminal P
1, the Q output of the first-stage flip-flop F1 is supplied. The level of the output terminal P1 of the flip-flop F1 changes from 1 after the flip-flops F1 to F3 are reset.
This is because, when it rises once, it changes from a low level to a high level.

Incidentally, the rotation sensor signal processing IC 31 of the first embodiment includes, for example, the following (1-1) to (1-
It can also be modified as in 3). (1-1): The Q bar terminal of the flip-flop F1 is connected to the output terminal P1, the Q bar terminal of the flip-flop F2 is connected to the output terminal P2, and the Q bar terminal of the flip-flop F3 is connected to the output terminal P3. .

(1-2): The AND gates 37 and 39 are replaced with NAND gates, or the AND gates 37 and 39 are replaced.
Is replaced by an OR gate that receives the output of each Q bar of both the first and third flip-flops F1 and F3, and the AND gate 39 is replaced with each Q of the second and third flip-flops F2 and F3. Replace with an OR gate with bar output as input.

(1-3): One end of the resistor 43 is connected not to the ground potential but to the power supply voltage. That is, the reset input terminal PR and the data terminal of the flip-flop 41 are pulled up to a high level by the resistor 43. Then, an inverter for inverting the level of the reset input terminal PR and inputting the inverted signal to the data terminal of the flip-flop 41 is provided in a signal path between the resistor 43 and the data terminal of the flip-flop 41.

With such a modification, each of the output terminals P1 to P1
The level of P5 is set after all flip-flops F1 to F3 constituting the binary counter 35 are reset.
The pulse signal S changes to the low level only when it rises one less number of times than the frequency division number assigned to its output terminal.
1 to F3 are reset by the Q bar output of the flip-flop 41 at the timing when the pulse signal S rises next after a low-level signal is input to the reset input terminal PR from any of the output terminals P1 to P5. It will be. That is, in this case, the specific level becomes the low level.

Even with such a configuration, the level of each frequency-divided signal (the level of each output terminal P1 to P5) shown in FIG.
The same effect as that of the embodiment 31 can be obtained. On the other hand, in the IC 31 of the first embodiment, the AND gate 37 is replaced with a NOR gate which receives the output of each Q bar of the first and third flip-flops F1 and F3, and the AND gate 39 is replaced by two stages. The second and third stage flip-flops F
Alternatively, it may be replaced with a NOR gate having the Q bar outputs of F2 and F3 as inputs.

On the other hand, in the first embodiment and its modifications, the number of output terminals need not be five. For example, if the frequency-divided signals of 2, 3, and 4 are unnecessary, the output terminals P1 and P2 can be deleted. If the frequency-divided signal of 7 is unnecessary, the output terminal P5 and the AND gate 39 are deleted. be able to.

The number of flip-flops constituting the binary counter may be other than three. For example, in the IC 31 of the first embodiment, if a frequency-divided signal of 9 or more is required, the number of flip-flops and the number of output terminals constituting the binary counter 35 are increased, and the same as described above. Based on the concept, the configuration may be such that the necessary divided signal is output from the added output terminal. To give a specific example, if a 15-frequency-divided signal can be output, the binary counter 35 is composed of four flip-flops, and the binary counter 35 has three flip-flops at the second, third, and fourth stages. If the AND signal of each Q output is supplied to any one of the output terminals, the output terminal and the reset input terminal P
By connecting R to the outside, 1
The divide-by-5 signal is output.

Next, a rotation sensor signal processing IC according to a second embodiment of the present invention will be described with reference to FIGS. First, FIG. 3 is a circuit diagram showing a configuration of the rotation sensor signal processing IC 51 of the second embodiment.
In FIG. 3, the same components as those of the rotation sensor signal processing IC 31 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 3, the rotation sensor signal processing IC 51 of the second embodiment has a pair of signal input terminals P + to which a pulse signal from the rotation sensor 3 is input, similarly to the IC 31 of the first embodiment. , P- and their signal input terminals P
And a waveform shaping circuit 33 for shaping and outputting a pulse signal taken in from + and P-.

The rotation sensor signal processing IC 51 of the second embodiment sends to the microcomputer 7 the divided signals obtained by dividing the pulse signal S after the waveform shaping by the waveform shaping circuit 33 by a plurality of frequency division numbers. Output terminals P1 for outputting
To P7, and a shift register 55 including seven flip-flops F11 to F17.

Incidentally, the rotation sensor signal processing IC 51 of the second embodiment also divides the pulse signal from the rotation sensor 3 by seven divisions of 2 to 8 like the IC 31 of the first embodiment. It is configured as follows. The output terminal P1 is a terminal for outputting a frequency-divided signal obtained by dividing the pulse signal by two, the output terminal P2 is a terminal for outputting a frequency-divided signal, and the output terminal P3 is provided. Is a terminal for outputting a divide-by-4 signal, and an output terminal P4
Is a terminal for outputting a divide-by-5 signal, an output terminal P5 is a terminal for outputting a divide-by-6 signal, and an output terminal P6 is a terminal for outputting a divide-by-7 signal. The output terminal P7 is a terminal for outputting a divide-by-8 signal.

The shift register 55 includes a plurality of flip-flops F11 to F11 to which clock terminals are commonly connected.
17, the Q terminal of the preceding flip-flop is connected to the data terminal of the next flip-flop. In the rotation sensor signal processing IC 51 of the second embodiment, the pulse signal S after the waveform shaping is input as a clock signal to the clock terminals of the flip-flops F11 to F17 included in the shift register 55. The data terminal of the first-stage flip-flop F11 is connected to the power supply voltage. That is, a high-level signal is always input to the data terminal of the first-stage flip-flop F11.

Further, the Q terminals of the flip-flops F11 to F17 constituting the shift register 55 are connected to the output terminals P1 to P7 by internal wiring in order from the Q terminal of the first-stage flip-flop F11. Therefore, the Q outputs of the flip-flops F11 to F17 in the first to seventh stages are supplied to the output terminals P1 to P7, respectively.

The rotation sensor signal processing IC 51 of the second embodiment also has, like the IC 31 of the first embodiment, a reset input terminal PR connected to any one of the output terminals P1 to P7 outside the IC 51. A flip-flop 41 having a data terminal connected to the reset input terminal PR, a resistor 43 for pulling down the reset input terminal PR and the data terminal of the flip-flop 41 to ground potential, and a Q bar output of the flip-flop 41 from the rotation sensor 3 And a delay circuit 45 which delays the signal by a predetermined delay time T shorter than the shortest period of the pulse signal and supplies the delayed signal to the reset terminal of the flip-flop 41.

The pulse signal S after waveform shaping is input to the clock terminal of the flip-flop 41 as a clock signal. In addition, the flip-flop 41
Are connected to the reset terminals of all the flip-flops F11 to F17 constituting the shift register 55.

In the second embodiment, the internal wiring connecting the Q terminals of the flip-flops F11 to F17 and the output terminals P1 to P7 respectively corresponds to the signal supply means of the present invention. In addition, the flip-flop 41, the resistor 43, and the delay circuit 45 correspond to a reset unit according to a second aspect.

Next, the operation of the rotation sensor signal processing IC 51 configured as described above will be described. First, if the output terminal P1 is connected to the reset input terminal PR, the pulse signal S is output from the output terminal P1 as shown in FIG.
The divided signal (divided-by-2 signal) is output.

That is, since the Q output of the first-stage flip-flop F11 is supplied to the output terminal P1, the level of the output terminal P1 is set to the flip-flops F11 to F11.
When the pulse signal S rises once after resetting the signal 17, the signal changes from a low level to a high level as a specific level. Then, when a high-level signal is input from the output terminal P1 to the reset input terminal PR, the flip-flop 41 is output at the next rising timing of the pulse signal S just like the case of the IC 31 of the first embodiment described above. The operation of the delay circuit 45 resets the flip-flops F11 to F17 and returns the output terminal P1 to the low level. Thereafter, the flip-flop F
When the pulse signal S rises once after the reset of F11 to F17, the output terminal P1 changes to high level, and at the next rising timing of the pulse signal S, the flip-flops F11 to F17 are reset and the output terminal P1 changes to low level. By repeating the operation of returning, the frequency-divided-by-2 signal is output from the output terminal P1.

The output terminal P2 is connected to the reset input terminal P
R, the output terminal P2 of FIG.
As a result, a signal obtained by dividing the pulse signal S by 3 (divided-by-3 signal) is output. That is, since the Q output of the second-stage flip-flop F12 is supplied to the output terminal P2, the level of the output terminal P2 becomes 2 after the flip-flops F11 to F17 are reset.
When it rises once, it changes from low level to high level. Therefore, the output terminal P2 is connected to the reset input terminal PR
To the flip-flops F11 to F17
When the pulse signal S rises twice after resetting, the output terminal P2 changes to the high level, and the flip-flops F11 to F11 at the next rising timing of the pulse signal S
By repeating the operation of resetting the output terminal 17 and returning the output terminal P2 to the low level, a divide-by-3 signal is output from the output terminal P2.

Similarly, when the output terminal P3 is connected to the reset input terminal PR, a signal obtained by dividing the pulse signal S by 4 (fourth divided signal) as shown in FIG. 4C is output from the output terminal P3. Output, output terminal P4 is reset to input terminal P
If it is connected to R, its output terminal P4 will
A signal obtained by dividing the pulse signal S by 5 (divided by 5 signal) is output. Further, the output terminal P5 is connected to the reset input terminal P
If it is connected to R, its output terminal P5 will output from FIG.
When the output terminal P6 is connected to the reset input terminal PR, a signal obtained by dividing the pulse signal S by 6 as shown in FIG. 4 is output from the output terminal P6 as shown in FIG. A signal obtained by dividing S by 7 (divided by 7 signal) is output. Further, if the output terminal P7 is connected to the reset input terminal PR, a signal obtained by dividing the pulse signal S by 8 (8-divided signal) is output from the output terminal P7 as shown in FIG.

This is because the Q outputs of the flip-flops F11 to F17 constituting the shift register 55 are supplied to the output terminals P1 to P17, respectively. The number of rises of the pulse signal S until the levels of P1 to P7 change to the high level depends on the output terminals P1 to P7.
This is because the number of times differs for each P7 and the number of times is one less than the frequency division number assigned to each of the output terminals P1 to P7.

It is desired that the pulse signal from the rotation sensor 3 be divided by any one of 2 to 8 by the rotation sensor signal processing IC 51 of the second embodiment and input to the microcomputer 7. In this case, among the output terminals P1 to P7, the output terminal corresponding to the desired frequency division number is connected to the reset input terminal PR, and the output terminal connected to the reset input terminal PR is connected to the input port of the microcomputer 7. Just connect to it.

According to the rotation sensor signal processing IC 51 of the second embodiment, the seven flip-flops F11
By using the shift register 55 composed of F17 to F17, all seven divisions of eight or less can be realized, and the circuit scale can be made very small as compared with the circuit configuration shown in FIG.

Also, the rotation sensor signal processing IC 51 of the second embodiment does not need to internally provide a logic circuit for switching the frequency division number, which is advantageous in terms of reducing the circuit scale. Furthermore, only one reset input terminal PR is required for switching the frequency division number, and an increase in the number of terminals can be minimized.

By the way, the rotation sensor signal processing IC 51 of the above-described second embodiment includes, for example, the following (2-1) and (2)
It can also be modified as in -2). (2-1): The Q-bar terminals of the flip-flops F11 to F17 constituting the shift register 55 are sequentially connected to the Q-terminals of the first-stage flip-flop F11, respectively.
1 to P7.

(2-2): One end of the resistor 43 is connected not to the ground potential but to the power supply voltage. That is, the reset input terminal PR and the data terminal of the flip-flop 41 are pulled up to a high level by the resistor 43. Then, an inverter for inverting the level of the reset input terminal PR and inputting the inverted signal to the data terminal of the flip-flop 41 is provided in a signal path between the resistor 43 and the data terminal of the flip-flop 41.

With such a modification, each of the output terminals P1 to P1
The level of P7 goes to a low level only when the pulse signal S rises by one less than the frequency division number assigned to its output terminal after all flip-flops F11 to F17 constituting the shift register 55 are reset. In addition, the flip-flops F11 to F17 output the low-level signal from one of the output terminals P1 to P7 to the reset input terminal PR, and the pulse signal S rises next time.
It is reset by the Q-bar output of the flip-flop 41. That is, in this case, the specific level becomes the low level.

Even with such a configuration, the level of each frequency-divided signal (the level of each output terminal P1 to P7) shown in FIG.
The same effect as 51 can be obtained. On the other hand, in the second embodiment and its modification, the shift register F11
To the clock terminals of F17 and F41, not the pulse signal S after the waveform shaping, but a signal obtained by dividing the frequency of the pulse signal S.
You may comprise so that it may input.

For example, the pulse signal S from the waveform shaping circuit 33 is frequency-divided by a binary counter comprising one flip-flop, and the frequency-divided signal is clocked to the clock terminals of the shift registers F11 to F17, 41. If it is configured to input as a signal, the output terminal P1
4,6,8,10,12,14,16 from each of ~ P7
7 can be output.

In the second embodiment and its modifications, the number of output terminals does not necessarily have to be the same as the number of flip-flops constituting shift register 55. For example, if the divide-by-3 signal is unnecessary, the output terminal P2 can be deleted. If the divide-by-5 signal is unnecessary, the output terminal P4 can be deleted.

The number of flip-flops constituting shift register 55 may be other than seven. For example, in the IC 51 of the second embodiment, if it is possible to further output a 9-frequency-divided signal, one output terminal is added, and the shift register 55 is composed of eight flip-flops. If the Q output of the flip-flop of the stage is configured to be supplied to the added output terminal, by connecting the output terminal and the reset input terminal PR externally, the 9-divided signal is output from the output terminal. Will be done.

As described above, one embodiment of the present invention has been described, but it goes without saying that the present invention can take various forms. For example, in the rotation sensor signal processing ICs 31 and 51 of the above embodiments, the rotation sensor 3 outputs a rectangular pulse signal, or a circuit having the same function as the waveform shaping circuit 33 is provided on the circuit board of the electronic control device 1. If it is assumed that the waveform shaping circuit 33 is provided in
It is not necessary to incorporate them in 31, 31.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a rotation sensor signal processing IC according to a first embodiment.

FIG. 2 is a time chart illustrating an operation of the rotation sensor signal processing IC according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a configuration of a rotation sensor signal processing IC according to a second embodiment.

FIG. 4 is a time chart illustrating an operation of the rotation sensor signal processing IC according to the second embodiment.

FIG. 5 is a block diagram illustrating a basic configuration of a vehicle electronic control device.

FIG. 6 is an explanatory diagram for explaining advantageous points when a rotation sensor having a large number of output pulses is used.

FIG. 7 is an explanatory diagram illustrating disadvantages when a rotation sensor having a large number of output pulses is used.

FIG. 8 is a circuit diagram illustrating a conventional configuration example of a rotation sensor signal processing IC.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Electronic control apparatus for vehicles, 3 ... Rotation sensor, 7 ... Microcomputer, 31, 51 ... Rotation sensor signal processing IC, 33 ... Waveform shaping circuit, 35 ... Binary counter, 37, 39 ... AND gate, F1-F3, F11 F17, 41: flip-flop, 43: resistor, 45: delay circuit, 55: shift register, P1 to P7: output terminal, PR: reset input terminal

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yukihide Niimi 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 2F077 AA28 AA37 AA43 TT32 TT51

Claims (2)

[Claims] 1. A pulse signal having a frequency proportional to the number of rotations of a predetermined rotating body is input from a rotation sensor, and a frequency-divided signal obtained by dividing the pulse signal is used in an electronic control device mounted on a vehicle. A rotation sensor signal processing IC that outputs the pulse signal to a microcomputer in the electronic control unit, wherein the pulse signal includes a plurality of frequency division numbers including frequency division numbers other than 2 n (where n is a positive integer). A plurality of output terminals for outputting the respective frequency-divided signals, and a plurality of flip-flops, and a binary signal in which the pulse signal is input as a clock signal to a clock terminal of the first-stage flip-flop. A counter and the output of any one of the flip-flops constituting the binary counter, or the output of two or more of the flip-flops constituting the binary counter By supplying a combined signal to each of the output terminals, the level of each of the output terminals is changed to a level at which all the flip-flops constituting the binary counter are reset at the same time. Signal supply means for changing to a specific level for the first time when the frequency rises by one less than the assigned frequency division number; a reset input terminal connected to one of the output terminals and the outside of the IC; When the signal of the specific level is input to the reset input terminal from any of the output terminals, at the timing when the clock signal rises next, the reset terminals of all the flip-flops have the reset signal of the shortest period of the pulse signal. Reset means for giving a reset signal only for a short time. When the reset input terminal is connected, a frequency-divided signal obtained by dividing the pulse signal at a frequency corresponding to the output terminal is output from an output terminal connected to the reset input terminal. A rotation sensor signal processing IC. 2. A pulse signal having a frequency proportional to the number of rotations of a predetermined rotating body is input from a rotation sensor, and a frequency-divided signal obtained by dividing the pulse signal is used in an electronic control device mounted on a vehicle. A rotation sensor signal processing IC for outputting to a microcomputer in the electronic control device, a plurality of output terminals for respectively outputting divided signals obtained by dividing the pulse signal by a plurality of division numbers. And the pulse signal or a signal obtained by dividing the pulse signal is
A shift register including a plurality of flip-flops input to a clock terminal as a clock signal, and a high-level signal input to a data terminal of a first-stage flip-flop; and a flip-flop included in the shift register.
The outputs of the same number of flip-flops as the output terminals
By supplying to each of the output terminals, the level of each of the output terminals becomes a specific level only when the clock signal rises a different number of times after all flip-flops constituting the shift register are simultaneously reset. A signal supply means for changing to a level, a reset input terminal connected to one of the output terminals and the outside of the IC, and a signal of the specific level from any of the output terminals to the reset input terminal. Reset means for applying a reset signal to reset terminals of all of the flip-flops for a time shorter than the shortest period of the pulse signal at the next timing when the clock signal rises. A frequency-divided signal obtained by dividing the pulse signal is output from an output terminal connected to the terminal. Rutotomoni its each output terminal, the rotational sensor signal processing IC, wherein, that the frequency division number is different with respect to the pulse signal.