JPH0338752A - Storage device - Google Patents

Abstract

PURPOSE:To attain the output of the correct unit data even when 2 or more error bits are included in the entire data by detecting the output errors of the 1st and 2nd storage circuits having the same storage contents at every unit data with a check bit and selecting the correct unit data. CONSTITUTION:The checking circuits 4 and 5 detect the errors of the unit data read out of 1st and 2nd storage circuits 1 and 2 with the address received from an address register 3 for each data with a check bit. A deciding circuit 6 decides the wrong one of both unit data with a checking signal and outputs a decision signal, and the selection circuits 7 - 10 select the correct unit data based on the decision signal. Consequently, even 2 or more error bits of the entire data can be corrected and the output of the storage circuit can be turned into the valid data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and particularly to a storage device for an information processing system.

[Conventional technology]

Conventional storage devices add check pits to the data stored in the memory circuit, and check the data with the check pits at the time of output to determine the validity of the data. The output data was corrected when there was only one bit in total.

[Problem to be solved by the invention]

The conventional storage device described above performs correction only when the error bit is 1 bit in the entire data, so if there are 2 or more error bits in the entire data, it cannot be corrected, so the output of the storage circuit is This has the disadvantage that the data becomes invalid.

[Means to solve the problem]

The storage device of the present invention includes: a first storage circuit that stores at each address at least one unit data with a check pit added to each unit data; a second storage circuit that has the same storage content in the first storage circuit; an address register that holds an address common to the first memory circuit and the second memory circuit; and an address register that holds an address common to the first memory circuit and the second memory circuit; On the other hand, a first check circuit and a second check circuit detect errors using check pits for each unit data and generate a check signal, and which unit data of the first storage circuit and the second storage circuit is detected as an error. a determination circuit that determines whether each unit data is correct based on a check signal received from the first check circuit and the second check circuit and outputs a determination signal; and a determination circuit that selects each correct unit data based on the determination signal of the determination circuit. and a selection circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the storage device of the present invention.

As shown in FIG. 1, the storage device of this embodiment has the same storage content in the first storage circuit 1 which stores a plurality of unit data with check pits added to each unit data at each address. a second memory circuit 2 that stores the address 101 of the first memory circuit 1 and the second memory circuit 2; and an address register 3 that supplies the address 101 of the first memory circuit 1 and the second memory circuit 2; 201. The first check circuit 4 performs a check using a check pit every 204 times, and the unit data 301 . ~304
A second check circuit 5 performs a check using a check pit every time, and a check signal 401 . -404 and check signals 501.about.504, a judgment circuit 6 determines which unit data in the first storage circuit 1 and the second storage circuit 2 is incorrect, and a judgment signal 601. . . . 604. The selection circuit 7, .about.10 selects each correct unit data by .about.604.

Then, the address register 3 sends the address 101 to the first memory circuit 1 and the second memory circuit 2, so the first memory circuit 1 receives the unit data with check pits added by the address 101 output from the address register 3. 2
01. ~204 to the first check circuit 4 and the selection circuit 7
．． .about.10, and the second storage circuit 2 outputs the unit data 301. 304 to the second check circuit 5 and the selection circuit 7. ~10.

The first check circuit 4 also receives the unit data 201. output from the first storage circuit 1-. .about.204 are checked using a check pit added to each unit data, and a check signal 401. ~404 to the determination circuit 6, the second check circuit 5 checks the unit data 301 and ~304 output from the second storage circuit 2 using a check pit added to each unit data, and outputs a check signal 501. ．． ~504 is sent to the determination circuit 6.

Therefore, the determination circuit 6 uses the check signal 401. ~404
and check signal 501. - 504, it is determined for each unit data which unit data in the first memory circuit 1 or the second memory circuit 2 is incorrect, and the selection circuit 7. to 10 determination signal 601. ~604 is sent.

Note that the determination circuit 6 includes a first memory circuit 1 and a second memory circuit 2.
When an error is simultaneously detected in the corresponding unit data, a selection disable signal 701 is output.

In addition, the selection circuit 7. .about.10 is the determination signal 601. ~60
4, the correct unit data for each unit data is output data 801. ~ Output as 804.

Next, a read operation for the storage device of this embodiment will be explained.

First, the first memory circuit 1 and the second memory circuit 2 are operated by the read address 101 output from the address register 3.
Unit data 201 to 204 of the first storage circuit 1 and unit data 301 of the second storage circuit 2. .about.304, the first check circuit 4, the second check circuit 5, and the selection circuit 7. ~10 respectively.

Then, the first check circuit 4 and the second check circuit 5
is the unit data 201. ~204 and unit data 30
1. -304 are checked using check pits added to each unit data.

Then, unit data 201. When there is no error in the check signals 401. When each of unit data 201. to 404 is set to '0' and an error is detected in any of the unit data 201. to 204, a check signal 401. to 404 corresponding to the error detection is generated.
Set only 04 to l.

Also, unit data 301. When there is no error in the check signals 501. When each of unit data 301. to 504 is set to 0'' and an error is detected in any of the unit data 301. to 304, a check signal 501. to 504 corresponding to the error detection is generated.
Set only "1'".

Then, the corresponding unit data of the first storage circuit 1 and the second storage circuit 2, that is, the unit data 201 and the unit data 301. Unit data 202 and unit data 30
2. Unit data 203 and unit data 303. When there is no error in each of the unit data 204 and the unit data 304, or when an error is detected only in the unit data of the second storage circuit 20, the determination circuit 6 outputs the determination signal 601. -604 are set to "0°".At this time, the selection circuits 7.-10 select the determination signals 601, -604.
is "0", the output of the first memory circuit l is selected, and the unit data 201. ~204 as output data 801. ~80
Set it to 4.

Further, when an error is detected in the unit data of the first storage circuit 1, the determination signals 601, 604 of the corresponding unit data
to II I II. At this time, selection circuit 7. ~10
is the determination signal 601. ~604 is II II II, so the output of the second memory circuit 2 is selected and the unit data 30
1. ~304 are output data 801 and ~804. As shown above, errors are determined for each unit data, and the determination signal 601. ~604, the selection circuit 7. Select valid unit data in ~10.

However, if the determination circuit 6 simultaneously detects an error in the corresponding unit data of the first storage circuit 1 and the second storage circuit 2,
The undeterminable signal 701 is set to 1'' to indicate that selection is impossible.At this time, the output data 8 of the selection circuits 7. to 10
01. ~804 is invalid.

[Effects of the Invention] As explained above, the storage device of the present invention detects errors in the output of the first storage circuit and the second storage circuit, which have the same storage content, using check pits added to each unit of data. ,
By selecting the correct unit data, even when there are two or more error bits in the entire read address data, each correct unit data can be output and the output data can be made valid data. are doing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the storage device of the present invention. 1...First memory circuit, 2...Second memory circuit, 3...Address register, 4...
・First check circuit, 5... Second check circuit, 6... Judgment circuit, 7, ~10... Selection circuit, 101... Address, 201, ~20
4,301. ~304...Unit data, 401
．． ~404,501. ~504...Check signal, 601. ~604...Judgment signal, 70.1.
...Selectable signal, 801. ~804...Output data.

Claims (1)

[Claims] a first memory circuit that stores at least one unit data with a check bit added to each unit data at each address; a second memory circuit that has the same memory content in the first memory circuit; the first memory circuit and the An address register that holds a common address in a second memory circuit, and an address received from the address register to check each unit data read from the first memory circuit and the second memory circuit, respectively. A first check circuit and a second check circuit detect bit errors and generate check signals, and the first check circuit determines which unit data of the first memory circuit and the second memory circuit is incorrect. A determination circuit that determines each unit data based on a check signal received from the circuit and the second check circuit and outputs a determination signal, and a selection circuit that selects each correct unit data based on the determination signal of the determination circuit. A storage device characterized by: