JPH0338734A - Evaluation chip - Google Patents

Abstract

PURPOSE:To shorten the test time of a micro-RAM by using a built-in program counter to produce the address of an area where the data are stored or read at write or read of data. CONSTITUTION:The data corresponding to the value of a program counter 3 is inputted via an external terminal 31 synchronously with a clock signal and in accordance with the increment of the value of the counter 3. Then a microwrite signal is set at '1' via an external terminal 33 and data are written into a micro-RAM 4. The counter 3 performs an increment action synchronously with the clock signal, and a microread signal is set at '1' via an external terminal 34. A comparator 71 compares the data received from the terminal 31 with the data read out of the micro-RAM 4. Thus an address is decided for the micro-RAM 4 in a short time, therefore the test time of the micro-RAM 4 can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an variation chip, and more particularly to a test method for an variation chip in which the memory for storing a microprogram is a RAM.

[Conventional technology]

FIG. 5 is a block diagram showing a debugging state using a conventional EVA chip (hereinafter referred to as EVA chip). In the figure, when "1" is input through the micro access signal line 21, the micro load circuit 65 connects the micro data bus 65, the micro address bus 66, the clock signal line 20, the micro ride signal line 22, and the micro read signal. The microprogram is read from and written to the micro RAM in the evaluation chip 60 using the line 23.

On the other hand, if "rO" is input through the micro access signal line 21, the EV chip 60 will be activated by the memory address bus 63.
The memory data bus 64 is used to fetch instructions from the program memory 61 and execute the instructions.

FIG. 6 shows a block diagram of an example of the Eva chip 60 shown in FIG. This Eva chip includes an arithmetic circuit 1, a system control circuit 2 that generates a system clock inside the Eva chip 60, a program counter 3, a micro RAM 4 that stores micro programs, and this micro RAM.
A microdecoder 5 that decodes the output of M4 to generate a control signal, an 8-bit wide internal data bus 9, an 8-bit wide address bus 10, a program address bus 57, a program data bus 58, and an instruction latch. 53
, a read/write buffer 8, a selector 54, an inverting gate 59, and external terminals 30-34, 38-40.

A micro access signal is sent to the external terminal 32 to put the Eva chip 60 into the micro program read/write mode.
The signal is inputted from the input signal and supplied to the read/write buffer 8, five inverting gates and 1, and the selector 4. When the micro access signal is "0", the read/write buffer 8 is disabled, the micro decoder 5 is activated, and the selector 54 selects the output data of the instruction latch 53 and outputs it to the address decoder 6. . Furthermore, when the micro access signal is "1", the read/write buffer 8 is enabled, the micro decoder 5 is disabled, and the selector 54 selects the address on the address bus 10 and outputs it to the address decoder 6. do.

A clock signal for generating a system clock for the evaluation chip 60 is inputted from the external terminal 30 and supplied to the system control circuit 2.

A microride signal for writing a microprogram to the microRAM 4 is inputted from an external terminal 33 and supplied to the microRAM4, and a microread signal for reading the microprogram is inputted from an external terminal 34 and supplied to the microRAM4.

Next, a case will be described in which the evaluation chip 60 performs a normal instruction execution operation.

First, a micro access signal "0" is input from the external terminal 32. Since the micro access signal is "0", the read/write buffer 8 is disabled, the micro decoder 5 is enabled, and the selector 54 is set to the instruction latch 53.
The selected output is input to the address decoder 6. The value of the program counter 3 is output to the outside of the EV chip 60 through the program address bus 57 and three external terminals. The evaluation chip 60 sends a command using the value of the program counter 3 as an address to the external terminal 40 and the program data bus 5.
8 and stored in the instruction latch 53. The selector 54 selects the output data of the instruction latch 53 and outputs it to the address decoder 6. The address decoder 6 specifies the memory cell of the micro RAM 4 corresponding to the input data, and the micro decoder 5 decodes the output data of the specified memory cell of the micro RAM 4.

Next, we will explain how to test the micro RAM 4 in Figure 7 (a).
) and (b).

When a micro access signal "1" is input from the external terminal 32, the read/write buffer 8 becomes operational, the micro decoder 5 is disabled, and the selector 54 selects an address on the address bus 10 and sends it to the address decoder 6. Output.

First, the case of writing 5AH to address n, 96H to address n+1, and A5H to address n+2 of the micro RAM 4 will be explained with reference to FIG. 7(a).

Here, it is assumed that the micro RAM 4 is a memory in which 8-bit width data can be read and written, and can store 256 bytes of data from address OOH to address FFH. Address n is input from external terminal 38 and data 5AH is input from external terminal 31. Since the address is input through the external terminal 38, the microride signal is set to "1" through the external terminal 33 one clock after the clock signal, taking into consideration the address confirmation time to avoid writing to the wrong address in the micro RAM 4. do. Microride signal is "1"
5AH is written to address n of the micro RAM 4 through the internal data bus 9 and the read/write buffer 8. Similarly, if address n+1 is input from the external terminal 38 and data 96H is input from the external terminal 31, and the microride signal is set to "1" through the external terminal 33, the micro RA
Write 968 to address n+1 of M4.

Similarly, when address n+2 is input from the external terminal 38 and data 96H is input from the external terminal 31, and the microride signal is set to "1" through the external terminal 33, the micro RAM
Write A5H to address n+2 of 4.

Next, address n, n+1, n+2 of micro RAM 4
The case of reading data from an address will be explained with reference to FIG. 7(b).

Address n is input from external terminal 38. Micro RA
As in the case of writing to M4, the micro read signal is set to rlJ through the external terminal 34 one clock clock after inputting the address n. This micro read signal "1" causes the data at address n of the micro RAM 4 to be output to the external terminal 31 through the read/write buffer 8 and the internal data bus 9. Similarly, when address n+1 is input from the external terminal 38 and the micro read signal "l" is made through the external terminal 34, n+ of the micro RAM 4 is input.
The data at address 1 is output to the external terminal 31. Similarly, when address n+2 is input from the external terminal 38 and the micro read signal is set to "1" through the external terminal 34, the micro RA
The data at address n+2 of M4 is output to the external terminal 31.

Therefore, by writing the microdata of the target microcomputer from the OOH address to the FFH address of the micro RAM 4, and then outputting the data stored from the OOH address to the FFH address to the external terminal 31, the data can be written to the micro RAM 4. You can test whether you can make a single stroke correctly.

[Problem to be solved by the invention]

In the conventional Eva chip mentioned above, in order to test whether data can be written correctly to the micro RAM 4,
When writing data to micro RAM 4, the address of the address to store the write data must be input from the outside, and when reading data from micro RAM 4, the address of the address from which the data is to be read must be input from the outside. It takes one clock time to confirm, so it takes two clocks to write and read the micro RAM.
The disadvantage is that it takes a long time to check M.

The purpose of the present invention is to eliminate such drawbacks and to improve microRA
When testing whether data can be written correctly to M, the program counter built into the evaluation chip generates the address at which data is to be stored or read when writing or reading data from the micro RAM. To provide an evaluation chip which shortens the time required to determine an address, performs write and read operations to and from a micro RAM in one clock, and shortens the time required to test the micro RAM.

[Means to solve the problem]

The configuration of the present invention is an memory system that includes a central processing unit, a microRAM that stores a microprogram for the central processing unit, a test circuit that tests the microRAM, and an interface circuit that emulates these circuits. In the variation chip, each output of the instruction latch and program counter in the central processing unit is input, and when the micro access signal input from the external terminal is "1", the output of the program counter is selected and the output of the micro RAM is selected. The present invention is characterized in that it includes a selector for specifying an address, and this selector has a function of accessing the micro RAM.

Further, the present invention adds a comparison circuit that compares the data on the internal data 0 bus in the central processing unit and the data read from the micro RAM, and outputs a match signal to the external output terminal when these data match. I can do it.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, this embodiment includes an arithmetic circuit 1 and a system control circuit 2.
, program counter 3 , micro RAM 4 , micro decoder 5 , internal data bus 9 , address decoder 6 , selector 54 , instruction latch 53 , program address bus 57 , and program data bus 58
, an inversion gate 59 , and an external terminal 30 . ．． 31,32゜33.34. ．． 39 and 40, and the clock signal, microride signal, and microread signal are the same as those shown in FIG. 6, so their explanation will be omitted.

In contrast to FIG. 5 of the conventional example, FIG. 1 shows a write buffer 70.
In addition, a comparator circuit 71 and external terminals 35 and 36 are added, the address bus 10 is removed from the input of the selector 54, and the program address bus 57 is input to the selector 54.

This evaluation chip inputs a microaccess signal for setting the microprogram read/write mode from the external terminal 32 and supplies it to the write buffer 70, comparison circuit 71, selector 54, and inverting gate 59. When the micro access signal r Q is 1, the write buffer 70 and comparison circuit 71 are disabled, the micro decoder 5 is activated, and the selector 54 is activated by the instruction latch 53.
output data is selected and output to the address decoder 6.

When the micro access signal is 1.1, the write buffer 70 and comparison circuit 71 are activated, the micro decoder 5 is disabled, and the selector 54 selects the data on the program address bus 57 and sends it to the address decoder 6. Output.

The comparison circuit 71 is a circuit that compares whether the data input from the internal data bus 9 and the data read from the micro RAM 4 match. If they match, it outputs a match signal to the outside of the EV chip 60 through the external terminal 36. do.

A reset signal for initializing the program counter 3 is input from the external terminal 35 and supplied to the program counter 3. The program counter 3 has a reset signal of “1”.
” to “0”, OOH is synchronized with the clock signal.
Increment operation is performed from

The case where the evaluation chip 60 performs a normal instruction execution operation is the same as that shown in FIG. 6, so a description thereof will be omitted.

Next, a method for testing the micro RAM 4 will be explained using the timing charts shown in FIGS. 2(a) and 2(b).

First, as shown in FIG. 2(a), when the reset signal is changed from "1" to "0" through the external terminal 35, the program counter 3 performs an increment operation from OOH in synchronization with the clock signal. When the value of the 30 gram counter 3 is OOH, inputting 5AH from the external terminal 31 and setting the microride signal to "1" through the external terminal 33 writes 5AH to the OOH address of the micro RAM 4.

Similarly, when the value of the program counter 3 is 01H, inputting 968 from the external terminal 31 and setting the microride signal to "1" through the external terminal 33 writes 96H to the OIH address of the micro RAM 4.

Similarly, in synchronization with the clock signal, Progera 11 counter 3
By inputting data corresponding to the value of the program counter 3 from the external terminal 31 and setting the microride signal to "1" through the external terminal 33 as Write data.

Next, as shown in FIG. 2(b), when the reset signal r 1 + is set to "0" through the external terminal 35, the program counter 3 performs an increment operation from OOH in synchronization with the clock signal. Pro 4- When crumb counter 3 is OOH, external terminal 31 to 5
Input AH and set the microleat signal to "1" through the external terminal 34. 7 Comparison circuit 71 compares data 5AH input from external terminal 31 with data read from OOH address of micro R, AM 4, and sends a match signal "1j" since the outside of Eva chip 60 does not know that they match. is output to the external terminal 36.Similarly, when the program counter 3 is OIH, 968 is input from the external terminal 31, and the micro read signal is outputted through the external terminal 34.
1, the comparator circuit 71 compares the human data 96H with the data read from addresses O] and H of the micro RAM 4, and outputs a match signal "]" to the external terminal 36.

The above operation is performed until the value of program counter 3 changes from OOH to F.
By performing up to FH, it is possible to perform steps 1 to 1 to determine whether data can be correctly written to the micro RAM 4.

FIG. 3 is a block diagram of a second embodiment of the invention. System control circuit 2 and program counter 3 of this embodiment
, micro RAM 4, micro decoder 5, internal data bus 9, address decoder 6, program address bus 57, program data bus 58, write buffer 70, comparison circuit 71, inverting gate 59, and selector. 54, instruction latch 53 and external terminal 30°3
1.32, 33, 34, 35, 36, 39°40, a match signal, a microride signal, a microread signal, and a clock signal are the same as in FIG.

In this embodiment, selectors 55 and 56 are added to FIG. A micro access signal inputted from the external terminal 32 is supplied to the arithmetic port li+81 and the selectors 55 and 56.

The selector 55 selects the data on the internal data bus 9 when the micro access signal is "OJ", and selects the upper 8 bits of the program address bus 57 when the micro access signal is "1" and outputs it to the arithmetic circuit 1. When the micro access signal is rQJ, the selector 56 selects the data on the internal data bus 9, and when the micro access signal is "1", the selector 56 selects the data on the internal data bus 9.
”, the lower 8 bits of the program address bus 57 are selected and output to the arithmetic circuit 1.

The arithmetic circuit 1 executes an arithmetic operation according to the output signal of the micro decoder 5 when the micro access signal is rQJ, and executes addition and outputs it to the internal data bus 9 when the micro access signal is "1".

When the evaluation chip 60 performs normal instruction execution operation,
Since it is the same as that in FIG. 6, it will be omitted.

Figure 4 (a) regarding the test method for micro RAM4.
This will be explained using the timing chart in (b).

The micro access signal is set to "1" through the external terminal 32. When this micro access signal is "1", the write buffer 70 and comparison circuit 71 are activated, the micro decoder 7-5 is prohibited from operating, and the selector 54 selects the data on the program address bus 57 to write the address. Output to decoder 6. The selector 55 selects the upper 8 bits of the program address bus 57 and outputs it to the arithmetic circuit 1, the selector 56 selects the lower 8 bits of the program address bus 57 and outputs it to the arithmetic circuit 1, and the arithmetic circuit 1
and the outputs of 56 are added and output to the internal data bus 9.

First, as shown in FIG. 4(a), when the reset signal is changed from "1-1" to "O" through the external terminal 35, the program counter 3 performs an increment operation from 0000H in synchronization with the clock signal. Program counter 3 is 0O
At the time of OOH, the microride signal is set to "1" through the external terminal 33 in synchronization with the clock signal. Since the upper 8 bits and lower 8 bits of the program counter 3 are both OOH, the result of addition in the arithmetic circuit 1 is 00H, which is sent to the micro RAM via the internal data bus 9 and the write buffer 70.
Write to OOH address 4. Furthermore, program counter 3 is incremented to 8-0001H. Similarly, the microride signal is set to "1" through the external terminal 33 in synchronization with the clock signal. Since the upper 8 bits of the program counter 3 are OOH and the lower 8 bits are OIH, the result of addition in the arithmetic circuit 1, 01H, is written to the OIH address of the micro RAM 4 through the internal data bus 9 and the write buffer 70. Similarly, as the program counter 3 increments, the microride signal is sent to "1" through the external terminal 33.
'', data from 03H to FFH can be written to addresses 03H to FFH of the micro RAM 4, respectively.

Next, as shown in FIG. 4(b), when the reset signal is changed from "1" to "0" through the external terminal 35, the program counter 3 performs an increment operation from 0OOOH in synchronization with the clock signal again. Program counter 3 is 0
When it is OOOH, the micro read signal is set to "1-1" through the external terminal 34 in synchronization with the clock signal. Both the upper 8 bits and lower 8 bits of the program counter 3 are OO.
Since the signal is H, the arithmetic circuit 1 adds the result and outputs 00H to the internal data bus 9. The comparison circuit 71 compares the data on the internal data bus 9 with the data read from the OOH address of the micro RAM 4, and sends a match signal "1" to the external terminal 36.
The program counter 3 is further incremented to 0OOIH.

Similarly, the microread signal is set to "1" through the external terminal 34 in synchronization with the clock signal. The upper 8 bits of program counter 3 are OOH and the lower 8 bits are 01.
Since the signal is H, the arithmetic circuit 1 adds the result 01H and outputs it to the internal data bus 9. The comparison circuit 71 compares the data on the internal data bus 9 with the data read from the OIH address of the micro RAM 4, and sends a match signal "1" to the external terminal 3.
Output to 6.

Similarly, by setting the micro read signal to "1" through the external terminal 34 as the program counter 3 increments, it is confirmed that the data from address 03H to FFH of the micro RAM 4 matches the data from write 1. can be confirmed.

As described above, by adding the data of the program counter 3 using the arithmetic circuit 1 to create write data to the micro RAM 4, it is no longer necessary to input write data to the micro RAM 4 from the external terminal 31. By combining the upper 8 bits and lower 8 bits of the program counter 3, various data can be used as write data to the micro RAM 4, which has the effect of allowing a large number of data to be written and checked. .

〔Effect of the invention〕

As explained above, in the present invention, when writing data to the micro RAM, the address of the address to store the write data, and when reading the data of the micro RAM, the address of the address to read the data are generated by the program counter built in the evaluation chip. This shortens the time it takes for an address to be determined on the micro RAM, and the write and read operations to the micro RAM 1M can be performed in one clock, greatly reducing the micro RAM check time. It has the effect of being able to For example, if one machine cycle takes 1 μsec, the time can be reduced by 50% from 8 m5 ec to 4 m5 ec with a 2 kilobyte micro RAM capacity.

Furthermore, it is equipped with a comparison circuit that determines whether the write data and read data of the micro RAM match, and a match signal is output from the comparison circuit to the outside of the EV chip, so there is no need for comparison processing in the micro load circuit outside the EV chip. It has the effect of becoming

[Brief explanation of drawings]

FIG. 1 shows the variation bench according to the first embodiment of the present invention.
27, FIGS. 2(a) and 2(b) are timing diagrams explaining the operation of the variation chip in FIG. 1,
FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 4 (
a) and (b) are timing diagrams explaining the operation of Fig. 22, Fig. 5 is a block diagram showing the configuration when depacking using a conventional variation chip, and Fig. 6 is an example of a conventional variation chip. The block diagram of FIG. 7A and FIG. 7B are timing diagrams explaining the operation of FIG. 1... Arithmetic circuit, 2... System control circuit, 3...
・Program counter, 4...Micro RAM, 5.
・Micro decoder, 6...Address decoder, 8・
... Read/write buffer, 9... Internal data bus, 10... Address bus, 20... Clock signal line, 21... Micro access signal line, 22... Micro ride signal line, 23...・Micro lead signal line,
30~40 External terminal, 53... Instruction latch, 54~
56... Selector, 57... Program address bus, 58... Program data bus, 59... Inversion gate, 60. Eva chip, 61... Program memory, 62... Microload circuit, 63. ...Memory address bus, 64...Memory data bus, 65...
・Micro data bus, 66...Micro address bus.

Claims (2)

[Claims] (1) In an variation chip that has a central processing unit, a microRAM that stores a microprogram for the central processing unit, a test circuit that tests the microRAM, and an interface circuit that emulates these circuits. , inputs each output of an instruction latch and a program counter in the central processing unit,
The micro access signal input from the external terminal is “1”
An variation chip comprising: a selector that selects the output of the program counter and specifies an address of the micro RAM when , the selector having a function of accessing the micro RAM. (2) Claim (1) further comprising a comparison circuit that compares the data on the internal data bus in the central processing unit and the data read from the micro RAM, and outputs a match signal to the external output terminal when these data match. ) Variation chips listed.