JPS59166880A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a self-testing mechanism for deciding a quality of an integrated circuit device by providing a counting circuit on the inside of the integrated circuit device, also generating a testing data and an address signal by working its output signal, writing them temporarily in a storing circuit, and comparing them with its output. CONSTITUTION:A storing circuit 200 is set to a write mode by inputting a ''1'' level signal to a mode switching terminal T and an R/W terminal. When a write pulse is inputted to a WE terminal, an operation of a counting circuit 500 is started. An address signal generating circuit 300 generates a testing address signal. In the same way, a testing data signal is generated by a data signal generating circuit 400. The testing data signal is written in a designated address of the storing circuit 200, and also outputted through an output signal line group 708. When the write pulse goes to ''0'' level state, a comparing circuit 600 compares it with the previous testing data signal, and the result is outputted to an output terminal 801. In this way, provision of an expensive testing machine is made unnecessary.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an integrated circuit device having a self-testing mechanism within the integrated circuit device. For example, a memory circuit only had a memory function. For this reason, IC requires an expensive testing machine in order to perform a quality determination test on this type of integrated circuit device. Also, the prepared test data.

It is necessary to apply the voltage to the input side of the integrated circuit device and then use a testing machine to determine whether the test results are good or bad based on the result outputted from the output side, resulting in a problem that the testing process is complicated.

[Purpose of the invention]

The present invention has been proposed in view of the above points, and a counter circuit is provided inside the integrated circuit device, and the output signal is processed to generate test data and address signals.
At the same time, the test data and the prescribed storage circuit are stored once! It is an object of the present invention to provide an integrated circuit device equipped with a test mechanism that determines the quality of the integrated circuit device by comparing the output of the test data that has been loaded.

[Structure of the invention]

The present invention includes a terminal that enables circuit operation to be switched between a normal mode and a test mode using an external signal, a memory circuit that stores predetermined data, a counter circuit that performs a counter operation in a test mode, and a terminal that performs a counter operation in a test mode. An address signal generation/selection circuit that generates and outputs all test address signals based on the output sound of the circuit and also outputs an external address signal inputted from the address terminal to Vc in the normal mode as it is, and the counter in the test mode. A data signal generation/selection circuit that generates and outputs a test data signal based on the output of the circuit, and that inputs it from a data terminal in normal mode and outputs the external data signal as it is; The data signal of the generation/selection circuit is compared with the signal output after the data signal is addressed by the address signal and once stored in the storage circuit to determine whether or not each of these signals is the same. It is composed of a comparison circuit that outputs an output, and a status display terminal that outputs the comparison result.

〔Example〕

1 is a schematic configuration diagram of a device 100. FIG. This is a terminal that allows the circuit operation to be switched between normal mode and test mode by an external signal, and is a memory circuit that stores 200i of data. This is a counter circuit that counts the total number of pulses of the write signal input from the WE terminal when the test mode is switched to the test mode from the 500 mode switching terminal Trc, and displays the count. ) 300 is a mode switching terminal T (when the mode is switched to the test mode, a test address signal is created and output based on the output signal of the pseudo-random bang generation circuit 500, and the mode is switched to the normal mode. 400 is an address signal generation/selection circuit that directly outputs the external address signal input from the address terminal when 600 is a data signal generation/selection circuit that creates and outputs a data signal and outputs the external address signal input from the data input terminal as it is when switched to the normal mode. 400 and this data is applied to the test address signal Vc.
Then, it is temporarily stored in the memory circuit 200.

A circuit 0501 which is a circuit for all comparisons with the output data is an AND gate circuit and selectively transmits a write signal inputted from the WE terminal only in the test mode to the counter circuit 5001C. 502 is an inverter circuit which causes the comparison circuit 600 to perform a comparison operation when the write signal is inverted to an "O" level after the "L" level state of the write signal is transmitted to the pseudo-random bang generation circuit 500. be.

In addition, a group of address signal lines input from outside the 700H,
701i Data signal line group that can be input from outside, 7021
'lJ Normal mode and test mode switching signal line, 703 Write signal line, 704 Read/write switching signal line, 7051' 1m counter circuit output signal line, 706
Address signal line group 707 output from the H address signal generation/selection circuit 300, data signal line group 7081-! output from the data signal generation/selection circuit 7081-! Memory circuit 2
The data signal line group output from 00 is a signal line group that outputs the comparison result of the 709μ comparison circuit 600, and the output terminal 8
Output from 01 to the outside. In addition, “&”UA in Figure 1
ND symbol, “○” (circle mark) is a symbol indicating a bald tongue foot.

5 is a diagram illustrating an example of the configuration of a counter circuit 500. FIG.

This is a 511i incremental counting circuit, and is initialized when an MR large input "0" level signal is input. When the mode switching signal goes to the "L" level, it becomes possible to count, and when a large CK write pulse is input through the signal line 710, the number is counted, and the count is displayed as S,R2<. When R1 and R2 are all “1”, the signal line 51
A carry signal is output from the flip-flop circuit 512 and input as a clock pulse. This ff,
J:f) Flip-flop circuit 512UD input to II
ll' level signal is input, and a 1'' level signal is output from the Q output to the signal line 711 to notify that the self-test cycle has ended. , an address signal selection circuit 32 that selectively outputs an address signal in the test mode or an address signal in the normal mode according to the mode switching signal.
0 is the address signal that is finally transmitted, and is appropriately switched to the test mode address signal or the normal mode address signal by the mode switching signal.

It is a diagram showing a configuration example of a Sea data signal generation/selection circuit 400, in which a test data signal generation circuit 410 and a mode switching signal selectively output a data signal in a test mode or a data signal in a normal mode. It is composed of a data signal selection circuit 420, a delay circuit 430, and a VC. The circuit configuration of test data signal generation circuit 410 is similar to that of test address signal generation circuit 13310, and the circuit configuration of data signal selection circuit 4200 is similar to address signal selection circuit 320. This is the data signal that is finally transmitted to the delay path 200.

The data signal for the test mode is appropriately switched to the data signal for the normal mode by the mode switching signal.

t is a diagram showing an example of the configuration of the comparator circuit 600, and in the diagram, X OR"U is an exclusive OR symbol.

Next, the operation of the present invention (a related embodiment) will be explained with reference to the drawings. (1) Operation in normal mode In normal mode vCrl: mode switching terminal TVc "0" signal generation circuit 310 and test data signal light selection circuit 3
2JP evening signal selection circuit 420.

Line group 701'e is selected. Therefore, in this mode, reading and writing operations as a normal memory circuit are possible.

(2) Operator in test mode Please also refer to this signal timing chart for explaining the circuit operation in test mode. ] Mote switching terminal TIC “1” level signal input
C"/W terminal "1" level signal is input to the memory circuit 200.
Set to write mode.

When the next [-9 input pulse is input to the WE terminal, the counter circuit 500 starts operating. (Note: Mode switching terminal T
The counter circuit 500 is initialized in a state where the "0" level signal is input to the counter circuit 500. ) Test address signal generation circuit 3107-ff Generates a test address signal based on the output signal of the counter circuit 500. This signal is selected by address signal selection circuit 320 and transmitted to storage circuit 200. Similarly, a test data signal is generated by the test data signal generation circuit 4101C,
The signal is output from the data signal selection circuit 420 after being delayed for a predetermined time by the delay circuit 430T/c. In this way,
The test data signal is the address v of the storage circuit 2000.
r- is written and output via the output signal line group 708.

When the write pulse becomes “0” level, the comparator circuit 6
00, the comparison operation is enabled, and each of the original test data signals is compared with the V3 answer of the data signal stored in the storage circuit 200 and output. This result is output signal line group 7
09 to the output terminal 8011' (outputted, i.e.,
If they do not match, an "L" level signal is output, and if they match, a "0#" level signal is output.

This operation is repeated and the counter circuit 500 is all "1".
One cycle of self-examination ends. At this time, a steady signal " is sent to the status display terminal 801 via the signal line 7Jl"i.
l'' is output to notify the self-test completion status.

In the embodiment, the bit width of the counter circuit is made small to simplify the explanation. [Effects of the Invention] As described above, the present invention provides a self-testing mechanism within the integrated circuit device, so there is no need to provide a separate expensive testing machine. ``Since there is no need to prepare a large amount of test data at the time of testing, the testing process is greatly simplified and work efficiency is also improved.

The cause of false theft is a diagram showing an example of a counter circuit, and a third signal timing chart diagram.

200... Memory circuit % 300... Address signal generation/selection circuit, 310... Address signal generation circuit for test, 320... Address signal selection circuit, 400...
Data signal generation/selection circuit, 410... test data signal generation circuit, 420... data signal selection circuit.

430...Delay circuit, 500...Counter circuit, 5
11... Incremental counting circuit, 512... 7 lip flora 1 circuit, 600... Comparison circuit, 700-709...
・Signal line or signal line group, 800...Mode switching terminal, 801...Status display terminal.

Malaya eyes 4th concave Figure 5

Claims (1)

[Claims:] A terminal that allows circuit operation to be switched between a normal mode and a test mode by an external signal. and a memory circuit that stores predetermined data. A counter circuit that operates as a counter in test mode. an address signal generation/selection circuit that adds the outputs of the counter circuits in a test mode to generate and output a test address signal; and in a normal mode, VC is input from an address terminal and outputs a friend external address signal as it is; . A data signal generation/selection circuit that generates and outputs a test data signal based on the output of the counter circuit in the test mode, and outputs the external data signal input from the data terminal as it is in the normal mode. and. In a test mode, a data signal outputted from the data signal generation/selection circuit is compared with a signal outputted after the data signal is addressed by the address signal and once stored in the storage circuit. An integrated circuit device comprising: a comparison circuit that outputs whether or not the contents of these signals are identical; and a status display terminal that outputs the comparison result.