JPH0337732B2 - - Google Patents
Info
- Publication number
- JPH0337732B2 JPH0337732B2 JP56209548A JP20954881A JPH0337732B2 JP H0337732 B2 JPH0337732 B2 JP H0337732B2 JP 56209548 A JP56209548 A JP 56209548A JP 20954881 A JP20954881 A JP 20954881A JP H0337732 B2 JPH0337732 B2 JP H0337732B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- semiconductor layer
- recess
- insulating film
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 18
- 238000000137 annealing Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 125000004437 phosphorous atom Chemical group 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- MUJOIMFVNIBMKC-UHFFFAOYSA-N fludioxonil Chemical compound C=12OC(F)(F)OC2=CC=CC=1C1=CNC=C1C#N MUJOIMFVNIBMKC-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法、特に絶縁性基
板上に絶縁分離された複数の半導体素子領域を有
する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a plurality of semiconductor element regions isolated from each other on an insulating substrate.
(2) 従来技術と問題点
本発明者等は、上記の形成の半導体装置の製造
方法を特願昭55−98397号にて既に提案した。こ
れを説明すると、第１図に見られるように、台１
上の絶縁性基板２を選択的にエツチングして複数
の凹所を形成し、その上に非単結晶材料層３（好
ましくは、生成する単結晶が各凹所に絶縁分離さ
れた複数の半導体領域と成るように計算した量の
それ）を形成し、好ましくは例えばPSGなどで
キヤツプ層４を設ける。その上からレーザー光を
照射してアニールを行なうと、非単結晶材料層３
が溶融、固化して凹所内に絶縁分離された複数の
単結晶領域が形成される。(2) Prior Art and Problems The present inventors have already proposed a method for manufacturing a semiconductor device having the above structure in Japanese Patent Application No. 55-98397. To explain this, as shown in Figure 1,
The upper insulating substrate 2 is selectively etched to form a plurality of recesses, and a non-single crystal material layer 3 (preferably, a plurality of semiconductors in which the single crystal to be produced is insulated and separated in each recess) is formed on the non-single crystal material layer 3. A cap layer 4, preferably made of PSG or the like, is provided. When annealing is performed by irradiating laser light from above, the non-single crystal material layer 3
is melted and solidified to form a plurality of isolated single crystal regions within the recess.
この従来技術に依れば、非単結晶材料を単結晶
化する工程が簡単であり、また複数の単結晶半導
体領域の電気的絶縁分離は完全である。更に、絶
縁分離領域の幅は絶縁性基板に凹部を形成する際
のエツチングで定めるものであるから充分に小さ
くすることができ、装置の高密度化、高集積化に
有効であるなどの利点がある。 According to this conventional technique, the process of converting a non-single-crystal material into a single crystal is simple, and the electrical isolation of a plurality of single-crystal semiconductor regions is perfect. Furthermore, since the width of the insulating isolation region is determined by etching when forming the recess in the insulating substrate, it can be made sufficiently small, which has the advantage of being effective in increasing the density and integration of devices. be.
ところで、上記の方法において、PSG膜など
でキヤツピングする理由は、主として保温のため
と、凹所内で固化する半導体の表面を平坦化させ
るためである。そして、この方法でアニールを行
なつた場合、例えは絶縁性基板２がSiO2より成
り、キヤツプ層４がPSGより成るとすれば、レ
ーザー光の高い出力のために発生する高温度にお
いてはPSG中の燐原子が結晶中に拡散し、また
PSG又はSiO2中の酸素原子も結晶中に拡散する
おそれがある。燐原子その他の不純物の混入は一
般的に好ましくないと言うことができる。また例
えばシリコン中の酸素は結晶欠陥の核となり、あ
るいはドナーともなるので好ましくない。また、
キヤツプ層なしでアニールを行なつても、通常の
例えば空気中などの雰囲気では、酸素原子などが
結晶中に拡散するおそれがある。 Incidentally, in the above method, the reason for capping with a PSG film or the like is mainly for heat retention and for flattening the surface of the semiconductor solidified within the recess. When annealing is performed using this method, for example, if the insulating substrate 2 is made of SiO 2 and the cap layer 4 is made of PSG, the PSG will be removed at the high temperature caused by the high output of the laser beam. The phosphorus atoms inside diffuse into the crystal, and
Oxygen atoms in PSG or SiO 2 may also diffuse into the crystal. It can be said that the inclusion of phosphorus atoms and other impurities is generally undesirable. Further, for example, oxygen in silicon is not preferable because it becomes a nucleus of crystal defects or also serves as a donor. Also,
Even if annealing is performed without a cap layer, oxygen atoms and the like may diffuse into the crystal in a normal atmosphere such as air.
(3) 発明の目的
本発明は上記の従来技術における欠点を除去す
ることを目的とする。即ち、凹所内に形成される
単結晶中への不純物の混入を除去することが本発
明の目的である。(3) Object of the invention The object of the present invention is to eliminate the above-mentioned drawbacks in the prior art. That is, an object of the present invention is to remove impurities from entering the single crystal formed in the recess.
(4) 発明の構成
上記目的を達成するためになされた本発明の要
旨は、絶縁性基板に選択的に複数の凹所を形成
し、そ上の全面に非単結晶材料膜を形成し、該非
単結晶材料膜を加熱エネルギー線を用いて単結晶
化し、前期凹所内に絶縁分離された複数の単結晶
半導体領域を形成することを含んで成る半導体装
置の製造方法に於いて、前記単結晶化工程を、前
記非単結晶材料膜を不活性絶縁膜で完全に包囲し
た状態で遂行することを特徴とする方法にある。(4) Structure of the invention The gist of the present invention, which has been made to achieve the above object, is to selectively form a plurality of recesses in an insulating substrate, form a non-single crystal material film on the entire surface thereof, A method for manufacturing a semiconductor device comprising: monocrystalizing the non-single crystal material film using heating energy rays to form a plurality of insulated and isolated single crystal semiconductor regions in the recess. The method is characterized in that the converting step is performed in a state where the non-single crystal material film is completely surrounded by an inert insulating film.
以下、本発明を実施例を用いて詳細に説明す
る。 Hereinafter, the present invention will be explained in detail using examples.
(5) 発明の実施例
第２図は本発明の一実施例を説明するための断
面図である。(5) Embodiment of the invention FIG. 2 is a sectional view for explaining an embodiment of the invention.
金属、アルミナ、高純度石英等から適宜選択し
た材料よりなる台板１１に絶縁性基板１２を形成
する。この絶縁性基板１２は、例えば、台板１１
としてのシリコンウエーハの表面を酸化して二酸
化シリコン層を形成してもよく、台板１１が金属
である場合に化学気相成長法（CVD）で非晶質
シリコン酸化膜を形成してもよい。絶縁性基板２
の厚さは例えば1μｍとする。 An insulating substrate 12 is formed on a base plate 11 made of a material appropriately selected from metal, alumina, high-purity quartz, etc. This insulating substrate 12 is, for example, a base plate 11
A silicon dioxide layer may be formed by oxidizing the surface of a silicon wafer, or an amorphous silicon oxide film may be formed by chemical vapor deposition (CVD) when the base plate 11 is made of metal. . Insulating substrate 2
The thickness is, for example, 1 μm.
次に、幅例えば5μｍの格子状の凸所を残して
例えば30μｍ×15μｍの凹所を多数形成するよう
に前記絶縁性基板を選択的にエツチングする。凹
所の底に少なくとも例えば0.05〜0.5μｍ程度の絶
縁性基板１２を残して1μｍ程度の深さにエツチ
ングしてもよいが、そのコントロールは通常容易
でないので、例えば、1μｍの二酸化シリコン膜
の凹所部分を完全にエツチングしてから露出した
シリコンウエーハ部分を酸化して0.05〜0.5μｍ程
度の酸化膜を形成してもよい。 Next, the insulating substrate is selectively etched so as to leave a lattice-shaped convex portion with a width of, for example, 5 μm, and to form a large number of recesses of, for example, 30 μm×15 μm. Etching may be performed to a depth of about 1 μm, leaving at least about 0.05 to 0.5 μm of the insulating substrate 12 at the bottom of the recess, but since it is usually not easy to control this, After completely etching a certain portion, the exposed silicon wafer portion may be oxidized to form an oxide film of about 0.05 to 0.5 μm.
それから、本発明の特徴の一つであるが、例え
ばSi3N4などの不活性絶縁膜２１をCVD法等によ
り例えば500〜2000Åの厚さに形成する。これに
よつて後のアニール処理の際、単結晶（半導体領
域）に不純物が下側から侵入することを阻止する
ことができる。この不活性絶縁膜材料は好ましく
は酸素原子を含まない高温生成材料であるが、ア
ルミナ類（例、サフアイヤ）などは酸素原子を含
んでいても高温生成材料である故にアニールの条
件に依つては十分に不活性といえる場合もあろ
う。 Then, which is one of the features of the present invention, an inert insulating film 21 made of, for example, Si 3 N 4 is formed to a thickness of, for example, 500 to 2000 Å by CVD or the like. This can prevent impurities from entering the single crystal (semiconductor region) from below during the subsequent annealing process. This inert insulating film material is preferably a high-temperature material that does not contain oxygen atoms, but aluminas (e.g., saphire) are high-temperature materials even if they contain oxygen atoms, so depending on the annealing conditions, In some cases, it can be said to be sufficiently inert.
次に、非単結晶（半導体）材料層１３、例えば
シリコン層をCVD法等により例えば0.5〜1μｍの
厚さに成長させる。非単結晶材料は多結晶体又は
非結晶体のいずれでもよい。また、好ましくはこ
の後パターニングして、シリコン等の量を調節す
ることができる。それによつて生成単結晶が各凹
所により完全に分離されることを保証することが
できる。 Next, a non-single crystal (semiconductor) material layer 13, for example, a silicon layer, is grown to a thickness of, for example, 0.5 to 1 μm by CVD or the like. The non-single crystal material may be polycrystalline or amorphous. Further, preferably, the amount of silicon etc. can be adjusted by patterning after this. This makes it possible to ensure that the produced single crystal is completely separated by each recess.
それから、本発明のもう一つの特徴であるが、
非単結晶材料層１３の上側及び側方を不活性絶縁
膜２２で覆い、前記不活性絶縁膜２１と一体とな
つて、非単結晶材料層１３が不活性絶縁膜で完全
に包囲されるようにする。即ち、これによつてア
ニールの際に単結晶に不純物が混入することを完
全に阻止することができる。このために例えば、
厚さ1000Å程度のSi3N4をCVD法で形成する。こ
の場合、特に、層１３の側方（周囲部）を完全に
包囲することが重要であり、そのために層１３の
形成の際にパターニングを行なつておくことが好
ましい。 Another feature of the present invention is that
The top and sides of the non-single-crystal material layer 13 are covered with an inert insulating film 22 so that the non-single-crystal material layer 13 is completely surrounded by the inert insulating film so as to be integrated with the inert insulating film 21. Make it. That is, this makes it possible to completely prevent impurities from being mixed into the single crystal during annealing. For this, for example,
Si 3 N 4 with a thickness of about 1000 Å is formed using the CVD method. In this case, it is particularly important to completely surround the sides (periphery) of the layer 13, and for this purpose it is preferable to perform patterning when forming the layer 13.
不活性絶縁膜２２は1μｍ程度であることが好
ましいが、Si3N4は1μｍの厚さに形成することは
困難であるので、前記のSi3N4膜上に、例えば、
1μｍ程度のPSG膜１４を形成する。これによつ
てレーザー光の反射防止の効果が得られる。 The inert insulating film 22 is preferably about 1 μm thick, but since it is difficult to form Si 3 N 4 to a thickness of 1 μm, for example, on the Si 3 N 4 film,
A PSG film 14 of about 1 μm is formed. This provides the effect of preventing reflection of laser light.
それから、例えば、CWアルゴンレーザーを、
エネルギー17W、走査速度10cm／秒、スポツトサ
イズ50μｍφの条件で照射することによつて、ア
リールを行なう。その際、全体を500℃程度に加
熱しておく。 Then, for example, a CW argon laser,
Aryl is carried out by irradiation under the conditions of energy 17 W, scanning speed 10 cm/sec, and spot size 50 μmφ. At that time, heat the whole thing to about 500℃.
このアニールにより、層１３の材料、例えば非
単結晶シリコンが溶融、固化し、凹所内に単結晶
１７（第３図参照）として成長する。この単結晶
１７は、前述のように、アニールの際その周囲が
完全に不活性絶縁物で包囲されているので、不純
物の混入は完全に除去されている。例えば、燐原
子含有量５％のPSG膜のみよりなるキヤツプで
同様なアニールを行つた場合、約1017個／cm3程度
の燐原子の拡散がみられ、またシリコン単結晶に
おいてｐタイプからｎタイプへの変化がみられた
が、本発明の方法に依れば、こうしたことは完全
に除去されている。 This annealing melts and solidifies the material of layer 13, for example non-monocrystalline silicon, and grows as a single crystal 17 (see FIG. 3) within the recess. As described above, since the single crystal 17 is completely surrounded by an inert insulator during annealing, impurities are completely removed. For example, when similar annealing is performed on a cap consisting only of a PSG film with a phosphorus atom content of 5%, approximately 10 17 atoms/cm 3 of phosphorus atoms are diffused, and silicon single crystals change from p-type to n-type. However, according to the method of the present invention, such changes have been completely eliminated.
また、本方法に依れば、アニールの際の周囲の
雰囲気は一般的には酸素雰囲気中、空気中等のい
ずれでもよい。 Further, according to the present method, the surrounding atmosphere during annealing may generally be either an oxygen atmosphere or air.
なお、上記の例では、アニールのエネルギー線
としてレーザー光を用いたが、その他キセノンラ
ンプやハロゲンランプなどの光を集光して使用す
ることもできる。 Note that in the above example, laser light was used as the energy beam for annealing, but it is also possible to use focused light from a xenon lamp, a halogen lamp, or the like.
(6) 発明の効果
以上の説明から明らかなように、本発明に依つ
て、絶縁性基板に選択的に複数の凹所を形成し、
その上の全面に非単結晶材料膜を形成し、該非単
結晶材料膜を加熱エネルギー線を用いて単結晶化
し、前記凹所内に絶縁分離された複数の単結晶半
導体領域を形成することを含んで成る半導体装置
の製造方法に於いて、形成される単結晶中への不
所望は不純物の混入を完全に除去することが可能
となる。このことによつて、上記のタイプの半導
体装置の実際的意義が高くなることは明らかであ
ろう。(6) Effects of the invention As is clear from the above description, the present invention allows selectively forming a plurality of recesses in an insulating substrate,
forming a non-single-crystalline material film on the entire surface thereof, monocrystallizing the non-single-crystalline material film using heating energy rays, and forming a plurality of isolated single-crystalline semiconductor regions in the recess. In the method for manufacturing a semiconductor device comprising the above method, it is possible to completely eliminate undesired impurities from being mixed into the formed single crystal. It will be clear that this increases the practical significance of semiconductor devices of the type described above.
第１図は従来技術の半導体装置の製造方法を説
明するための断面図、第２図は本発明の半導体装
置の製造方法を説明するための断面図、第２図は
本発明の製造した半導体装置を示す断面図であ
る。
１，１１……台板、２，１２……絶縁性基板、
３，１３……半導体材料層、４，１４……キヤツ
プ層、１７Ａ，１７Ｂ……半導体材料単結晶、２
１，２２……不活性絶縁膜。
FIG. 1 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device, FIG. 2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view showing the device. 1, 11... base plate, 2, 12... insulating substrate,
3, 13... Semiconductor material layer, 4, 14... Cap layer, 17A, 17B... Semiconductor material single crystal, 2
1, 22...Inactive insulating film.
Claims (1)
数の分離された半導体素子領域用の凹所を形成す
る工程と、 該凹所の側壁及び底面を含む該絶縁性基板の全
面に不活性絶縁膜を形成する工程と、 該凹所内に非単結晶半導体層を成長する工程
と、 該非単結晶半導体層の周辺の側面を含む表面全
面に不活性絶縁膜を形成する工程とを有し、 該非単結晶半導体層が該不活性絶縁膜で完全に
包囲された状態で加熱エネルギー線を用いて該凹
所内の該非単結晶半導体層を溶融し、単結晶化す
る工程を含むことを特徴とする半導体装置の製造
方法。[Claims] 1. A step of selectively etching an insulating substrate to form recesses for a plurality of separated semiconductor device regions; a step of forming an inert insulating film over the entire surface; a step of growing a non-single crystal semiconductor layer in the recess; a step of forming an inert insulating film over the entire surface including the peripheral side surfaces of the non-single crystal semiconductor layer. and a step of melting the non-single-crystalline semiconductor layer in the recess using a heating energy beam in a state where the non-single-crystalline semiconductor layer is completely surrounded by the inert insulating film to single-crystallize the non-single-crystalline semiconductor layer. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20954881A JPS58112333A (en) | 1981-12-26 | 1981-12-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20954881A JPS58112333A (en) | 1981-12-26 | 1981-12-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58112333A JPS58112333A (en) | 1983-07-04 |
| JPH0337732B2 true JPH0337732B2 (en) | 1991-06-06 |
Family
ID=16574629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20954881A Granted JPS58112333A (en) | 1981-12-26 | 1981-12-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58112333A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4558140B2 (en) * | 2000-05-02 | 2010-10-06 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247673A (en) * | 1975-10-15 | 1977-04-15 | Hitachi Ltd | Process for production of silicon crystal film |
| JPS5659694A (en) * | 1979-10-18 | 1981-05-23 | Agency Of Ind Science & Technol | Manufacture of thin film |
-
1981
- 1981-12-26 JP JP20954881A patent/JPS58112333A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247673A (en) * | 1975-10-15 | 1977-04-15 | Hitachi Ltd | Process for production of silicon crystal film |
| JPS5659694A (en) * | 1979-10-18 | 1981-05-23 | Agency Of Ind Science & Technol | Manufacture of thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58112333A (en) | 1983-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0036137B1 (en) | Method for production of semiconductor devices | |
| US4448632A (en) | Method of fabricating semiconductor devices | |
| US4404735A (en) | Method for manufacturing a field isolation structure for a semiconductor device | |
| JPH0343769B2 (en) | ||
| JPH0337732B2 (en) | ||
| JP2718074B2 (en) | Method of forming thin film semiconductor layer | |
| JPS5856457A (en) | Manufacture of semiconductor device | |
| JPS6342417B2 (en) | ||
| JPS6159820A (en) | Manufacture of semiconductor device | |
| JPS61166074A (en) | Insulated gate type transistor and manufacture thereof | |
| JPS59158515A (en) | Manufacture of semiconductor device | |
| JPS58175844A (en) | Manufacture of semiconductor device | |
| JPH0257337B2 (en) | ||
| JPS6347255B2 (en) | ||
| JP2526380B2 (en) | Method for manufacturing multilayer semiconductor substrate | |
| JPH0223027B2 (en) | ||
| TW379383B (en) | Method of forming large or selective area of silicon on insulation layer | |
| JPH0153509B2 (en) | ||
| JPS5919312A (en) | Manufacture of semiconductor device | |
| JPS5948532B2 (en) | Manufacturing method of semiconductor device | |
| JPS5961117A (en) | Manufacture of semiconductor device | |
| JPH0339038B2 (en) | ||
| JPS6038809A (en) | Manufacture of semiconductor device | |
| JPH0221137B2 (en) | ||
| JPS60257122A (en) | Semiconductor device |