JPH0336317B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] This invention relates to a method for forming high-density lines in thin film integrated circuits.

[Technical background of the invention and its problems] Conventionally, lead wire formation for thin film integrated circuits has been carried out by, for example,
In MIC (Micro Wave Integrated Circuits), a resistive film is attached to an insulating substrate such as a glass or glazed alumina substrate by sputtering, and then Gr (500 to 1000 Å) and Au (0.5 to 2 μ) are attached.
A resistor and a conductive circuit pattern as shown in FIG. 1A are obtained by laminating and depositing them by vapor deposition and by photoetching or the like. In some cases, the Au layer is further thickened by Au plating (10 μm) only on the extraction electrode part.

Another conventional example is that MIC is basically used in the initial lead formation of thermal heads.
Similarly, a conductive circuit pattern as shown in FIG. 1b was obtained, and the lead-out electrodes were plated with Au (10μ).

In either case, the part to be plated with Au has a large gap between the lines, a pattern with a coarse line density, and a shape in which the lead wires are laminated and plated completely in the width direction, as shown in Figure 1c. It's summery.

The drawbacks of the conventional method arise when high wiring density and low lead resistance are required. For example, recent thermal heads have a high density of 12 to 16 leads/mm, and have a structure in which the drive circuit and control circuit are mounted as ICs on the same chip, resulting in high density and many types of leads. It is necessary to form wiring. In the conventional method of forming a thick lead layer with the same thickness over the entire surface of the substrate and then photo-etching it, it is difficult to photo-etch fine patterns. There was a drawback that lead resistance wiring was difficult. To give a specific example, when Au is used as the lead material, the specific resistance of Au is 2.2×
Some IC drive wiring requires low lead resistance, such as 10 ^-6 Ωcm, and when wiring with a lead resistance of 0.6Ω or less, the lead length is
If the lead width is 32mm and the lead width is 50μ, an Au lead layer with a thickness of 23μ must be used. This is approximately the same as the line gap, or 1.5 depending on the location.
Since the value is twice that, it can be said that normal photoetching is impossible. Even in the method of depositing a thin lead layer of about 2 μm thick over the entire surface and forming a fine pattern by photo-etching, and then depositing Au by plating, etc., the plating grows only in the vertical direction in the conventional method where it is deposited as shown in Figure 1. Not,
Since it also grows in the lateral direction, shorts occur between the lines, making it impractical.

[Purpose of the invention]

An object of the present invention is to provide a method for overcoming the conventional drawbacks regarding such high-density wiring and meeting the requirements for high-density, low-lead resistance wiring.

[Summary of the invention]

This invention deposits a sufficiently thin lead layer on the entire surface to form fine patterns of high-density wiring, forms most of the lead wires that do not require particularly low lead resistance, and only applies to lead wires that require low lead resistance. The lead wire is plated, and at both ends in the width direction of the lead wire, an area where no plating is formed is created with a dimension larger than the plating thickness.

[Embodiments of the invention]

Next, examples of the present invention will be described.

A resistive film is attached to a glazed alumina substrate 1, and then a Cr/Au film 3 is formed with a Cr film of about 1000Å and an Au film of 2μ.
It is deposited in layers (Fig. 2a). This thickness is sufficient for 12 to 16 high-density wirings. On this entire film, a mask process is performed to expose only the parts where low lead resistance wiring is required and cover the rest with resist 4, and Au plating 6 is applied on the exposed Au film (see Figure 2b). Figure 2 c). The Au plating 6 is formed to have a thickness of about 10 to 25 μm. At this time, it is important to plate only the area recessed from the end, at least the plating thickness. (Make a Metsuki mask like that.)

Next, the plating resist mask is removed, and a new resist pattern 5 is formed using the main mask for high-density wiring (FIG. 2d). Each is etched using an Au etchant, then a Cr etchant, and finally a resistive film etchant. Finally, when the resist 5 is removed, the desired object is formed.

Next, a reference example will be explained.

A resistive film is attached to the glazed alumina substrate 1, and then a Cr film of about 1000 Å and an Au film of about 2 μm are stacked.
A Cr/Au film 3 is formed (FIG. 3a).

Next, a resist pattern 4 is formed using a main mask for high-density wiring (FIG. 3b). Each is etched using an Au etchant, then a Cr etchant, and finally a resistive film etchant (FIG. 3c). This resist 4 is removed, and then a new resist mask is used to coat the resist 5 so that the resist mask remains at least as much as the plating thickness, which is less than the line direction edge of the lead line width that requires low lead resistance wiring. (Figure 3d).

Next, Au plating 6 is applied to the exposed vapor-deposited Au. The thickness of the Au plating 6 is approximately 10 to 25μ. After that, by removing the plating resist 5, the desired object is formed. In this process, unlike the former, there is a high-density PEP first and then a plating of several tens of microns is attached, so it has the advantage of easily obtaining high resolution. It is necessary to pay attention to lead formation, and in some cases Al evaporation and its PEP may be necessary to achieve uniform plating.
Additional steps may be required. An extreme example is the case where it is necessary to plate an island-shaped lead pattern. Even in such a case, after Au plating 6, if the plating resist is removed and the Al electrode is removed, the desired object like f will remain.

Although the embodiment has been described using an example of Cr/Au metallization, it is of course possible to substitute other metal systems.

When a Ti/Au evaporated film is plated with Au When a Ti/Au evaporated film is plated with Ni/Cu When a Ti/Cu evaporated film is plated with Cu/Ni/Au When an Al/Ti/Cu evaporated film is plated with Cu/Ni/Au The following cases can be considered as practical metal systems.

In the explanation of the above examples, when the vapor deposition film is mentioned, sputtering, ion plating,
Other thin film forming means such as CVD may also be used.

〔Effect of the invention〕

(1) High-density wiring and low lead resistance wiring are formed on the same substrate in order to form high-density wiring from a lead layer consisting of only a vapor-deposited film, and to form low-lead resistance wiring from a lead layer in which a plating film is laminated on a vapor-deposited film. It becomes possible to form

(2) Plating low lead resistance wiring is not done over the full width of the line, but only in the center, and at both ends of the lead line in the width direction, an area larger than the plating thickness is created without plating. The gap between the two lines can be made smaller.
This makes it compact.

(3) Because of the same as above, line-to-line shoots due to matte growth do not occur.

Regarding the application of the present invention, it is of course possible to use it as a single-layer high-density wiring, but it is also possible to form a two-layer or multilayer high-density wiring by applying an insulating film thereon and further forming lead wiring. Furthermore, it can be used as a hybrid IC by mounting passive elements or active elements.

As an example, when adapting to a thermal head as shown in Figure 4, over 2000 lead wires are formed on a large A4 size board at a rate of 12 wires/mm with a line gap of 15μ.
Lead wires that require low lead resistance are plated with 23μ to reduce the lead resistance of a lead wire with a total length of 32 mm.
We were able to keep the resistance to 0.6Ω or less, making it possible to drive approximately 100 active chips uniformly.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional example, Fig. 2 is a sectional view of each step showing an embodiment of the present invention, Fig. 3 is a sectional view of each step showing a reference example of the present invention, and Fig. 4 is a sectional view of the present invention. FIG. 1 is a plan view of an embodiment of the invention. 1... Insulating substrate, 2... Adhesive layer, 3... Lead layer,
4, 5...Resist.

Claims (1)

[Claims] 1. A first step of forming a thin film metal layer on an insulating substrate, and a first step of forming a first resist layer on the thin film metal layer so as to expose a first predetermined opening. a third step of forming a plating layer around the first predetermined opening and a distance of at least the plating thickness from the first predetermined opening; and the first resist. a fourth step of removing the layer; a fifth step of forming a second resist layer on at least the thin film metal layer so as to form a second predetermined opening in the thin film metal layer; A high-density thin film circuit comprising at least a sixth step of forming an opening in the thin film metal layer using a second predetermined opening, and a seventh step of removing the second resist layer. A method of manufacturing a wiring board.