CN214014637U - Buried resistance metal foil - Google Patents

Abstract

The utility model relates to a printed board technical field discloses a bury and hinder metal foil, wherein, bury and hinder metal foil including the resistance layer, the conducting layer, tie coat and a plurality of electrically conductive arch, set up tie coat and electrically conductive arch between resistance layer and conducting layer, a plurality of electrically conductive protruding tie coats, it is inhomogeneous to have avoided leading to the resistance layer because the inhomogeneous copper foil of roughness is direct to contact with the resistance layer among the prior art, cause the different problem of resistance layer each direction's unit area's resistance, the difference of the resistance value of the unit area of each direction with the resistance layer reduces, and then be convenient for design high accuracy buries the resistance, in addition, the tie coat can also increase the adhesive force and the protective resistance layer of conducting layer.

Description

Buried resistance metal foil

Technical Field

The utility model relates to a printing board technical field especially relates to a bury and hinder metal forming.

Background

At present, with the development trend of miniaturization of electronic products, higher requirements are put on the packaging density and the volume of the electronic products, and embedding passive devices such as resistors into a printed board is an effective means for reducing the size of the electronic products.

As shown in fig. 1, it is a partial structural diagram of a conventional printed board with a buried resistor, in the conventional printed board with a buried resistor, a copper foil layer 10 covers a resistive layer 20, and the copper foil layer 10 is closely attached to the resistive layer 20, wherein the copper foil layer 10 is used for making a circuit pattern. In order to ensure tight connection between the copper foil layer 10 and the resistance layer 20, the surface of the copper foil layer 10 connected to the resistance layer 20 is generally set to have a certain roughness, but the roughness of the copper foil layer 10 is not uniform under microscopic conditions, so that the surface roughness of the resistance layer 20 close to the copper foil layer 10 is not uniform, and the resistance value of the resistance layer 20 has non-uniformity, which seriously affects the design accuracy of the buried resistor.

SUMMERY OF THE UTILITY MODEL

An object of the embodiment of the utility model is to provide a bury and hinder metal forming, printed board and bury preparation method who hinders metal forming, it can reduce the difference of the resistance value in each region of resistance layer, and then is convenient for design the buried resistance of high accuracy to the roughness of protective resistance layer, regulation conducting layer.

In order to solve the above technical problem, an embodiment of the present invention provides a buried resistance metal foil, including a resistance layer, a conductive layer, a bonding layer, and a plurality of conductive bumps;

the tie coat is located the resistive layer with between the conducting layer, it is a plurality of electrically conductive protruding interval distribution is in and protrusion on the one side of resistive layer the tie coat, and it is a plurality of electrically conductive protruding quilt the conducting layer covers, or it is a plurality of electrically conductive protruding interval distribution is in on the one side of conducting layer, and is a plurality of electrically conductive protruding quilt the resistive layer covers, or electrically conductive protruding interval distribution is in on the tie coat.

Preferably, the plurality of conductive protrusions are uniformly distributed on the resistive layer or the conductive layer.

Preferably, the plurality of conductive protrusions are first metal particles and/or particle clusters composed of a plurality of second metal particles.

Preferably, the height of the conductive bump is 0.5 to 20 micrometers.

Preferably, the thickness of the conductive layer is 2 to 20 micrometers.

Preferably, the conductive layer comprises any one or more of aluminum, silver, copper and gold.

Preferably, the conductivity of the conductive layer is 2 to 1000 times that of the resistive layer.

Preferably, the resistive layer includes any one metal of nickel, chromium, platinum, palladium and titanium, or an alloy including at least two combinations of nickel, chromium, platinum, palladium, titanium, silicon and phosphorus.

Preferably, the buried resistance metal foil further includes a dielectric layer, and the dielectric layer is disposed on a surface of the resistance layer away from the conductive layer.

Implement the embodiment of the utility model provides a, following beneficial effect has:

the embodiment of the utility model provides a bury and hinder metal foil, wherein, bury and hinder metal foil including the resistance layer, the conducting layer, tie coat and a plurality of electrically conductive arch, set up tie coat and electrically conductive arch between resistance layer and conducting layer, and a plurality of electrically conductive protruding salient tie coats, through set up the tie coat between conducting layer and resistance layer, so that the conducting layer covers on tie coat and electrically conductive arch, it is inhomogeneous to have avoided leading to the resistance layer because the inhomogeneous copper foil of roughness is direct to contact with the resistance layer among the prior art, cause the inhomogeneous problem of resistance layer, with the difference of the resistance value of the different regions of reduction resistance layer, and then be convenient for design the buried resistor of high accuracy, in addition, the tie coat can also increase the adhesive force and the protective resistance layer of conducting layer, still can play the effect of adjusting the conducting layer roughness.

Drawings

Fig. 1 is a partial structural schematic diagram of a conventional printed board with a buried resistor;

fig. 2 is a schematic structural diagram of a buried resistance metal foil according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of a buried barrier metal foil including a dielectric layer according to a first embodiment of the present invention;

fig. 4 is a schematic structural diagram of a buried barrier metal foil including a peelable carrier layer and a dielectric layer according to a first embodiment of the present invention;

fig. 5 is a flow chart of a method for manufacturing a buried resistance metal foil according to a first embodiment of the present invention;

fig. 6 is a schematic structural diagram of a buried resistance metal foil according to a second embodiment of the present invention.

10, a copper foil layer; 20. a resistive layer; 1. a conductive layer; 2. a resistive layer; 3. a dielectric layer; 4. a conductive bump; 5. a peelable carrier layer; 6. a bonding layer; 7. a dielectric layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Example one

Referring to fig. 2, the buried resistance metal foil according to the embodiment of the present invention includes a resistance layer 2, a conductive layer 1, an adhesive layer 6, and a plurality of conductive bumps 4;

the adhesive layer 6 is disposed between the resistive layer 2 and the conductive layer 1, the conductive protrusions 4 are distributed on one surface of the resistive layer 2 at intervals and protrude out of the adhesive layer 6, and the conductive protrusions 4 are covered by the conductive layer 1.

The embodiment of the utility model provides an in, set up tie coat 6 and electrically conductive protruding 4 between resistance layer and conducting layer 1, and a plurality of 4 interval distribution of electrically conductive protruding are in the one side of resistance layer 2 and protrusion tie coat 6, set up conducting layer 1 in the one side of keeping away from resistance layer 2 through 6 at tie coat, so that conducting layer 1 covers on tie coat 6 and electrically conductive protruding 4, it leads to the resistance layer inhomogeneous to have avoided leading to because the inhomogeneous copper foil of roughness is direct to contact with the resistance layer among the prior art, cause the inhomogeneous problem of resistance layer, with the difference of the resistance value of reducing the different regions of resistance layer, and then be convenient for design the buried resistor of high accuracy, in addition, tie coat 6 can also increase the adhesive force and the protective resistance layer 2 of conducting layer 1. At the same time, the adhesive layer 6 can also adjust the roughness of the conductive layer 1.

It should be noted that, the embodiment of the present invention provides the adhesive layer 6 and the conductive protrusion 4 between the resistive layer 2 and the conductive layer 1, thereby avoiding the direct contact between the conductive layer 1 and the resistive layer 2, and increasing the adhesion between the conductive layer 1 and the resistive layer 2. The conductive bumps 4 are distributed at intervals, so that the situation that the resistivity of the conductive bumps 4 is lower than that of the resistive layer 2 is avoided, and when the conductive bumps 4 are mutually adhered, current flows to a passage formed by the adhesion of the conductive bumps 4 after passing through a conductive end formed by the conductive layer 1, so that the resistive layer 2 loses effect and the use of the resistive layer 2 is influenced. In this embodiment, the conductive bumps 4 are distributed on one surface of the resistive layer 2 at intervals, that is, the conductive bumps 4 are not adhered to each other, so that the conductive bumps 4 are not conducted to each other to form a resistor. In addition, in the middle of concrete implementation, because factors such as process error, it is adjacent probably to lead to a plurality of electrically conductive 4 adhesion, but the influence can not be very big, consequently the utility model discloses easily realize form interval distribution's electrically conductive 4 on the resistance layer 2, its technological requirement need not too harsh, is favorable to reduction in production cost.

Specifically, each of the conductive bumps 4 is a first metal particle or a particle cluster composed of a plurality of second metal particles; or a part of the conductive protrusions 4 are first metal particles, another part of the conductive protrusions 4 are particle clusters composed of a plurality of second metal particles, and the number of the particle clusters and the number of the first metal particles may be equal or different. The materials of the first metal particles and the second metal particles may be the same or different. The first metal particles are individually granular, the first metal particles are distributed at intervals, and the particle clusters formed by a plurality of second metal particles are also distributed at intervals.

When the conductive protrusions 4 are particle clusters composed of a plurality of second metal particles, the surface roughness thereof is increased relative to that of a single first metal particle, thereby advantageously increasing the adhesion of the conductive layer 1, so that the conductive layer 1 can be reliably connected to the resistive layer 2.

As an alternative embodiment, the first metal particles are of a different material than the conductive layer 1. The first metal particles and the conductive layer 1 are made of different materials and have different resistivities, and when the resistivity of the first metal particles is lower than that of the conductive layer 1, the resistance circuit is formed by the embedded resistance metal foil, and then the influence of the first metal particles on the resistance circuit is smaller. Correspondingly, the second metal particles can also be chosen to be of a different material than the conductive layer 1. The material of both the first metal particles and the second metal particles may be the same or different.

Specifically, the height H of the conductive bump 4 in the present embodiment is 0.5 to 20 micrometers. The height H of the conductive bump 4 is the distance between the highest point and the lowest point of the conductive bump 4 in the vertical direction. In a specific application, if the height of the conductive bump 4 is too small, a good adhesion force cannot be added to the conductive layer 1 and the resistive layer 2, and if the height of the conductive bump 4 is too large, a pinhole may be generated in the conductive layer 1, thereby affecting the performance of the conductive layer 1. In this embodiment, the height of the conductive bump 4 is set to 0.5 to 2.0 micrometers, so that the conductive bump 4 has a good effect of increasing the adhesion between the conductive layer 1 and the resistive layer 2. Of course, the height of the conductive bump 4 may also be set to other values according to the actual use requirement, and further details are not described herein.

It should be noted that the conductive bumps 4 may be randomly distributed on the resistive layer 2, and in order to further ensure the connection stability between the conductive layer 1 and the resistive layer 2, the conductive bumps 4 in this embodiment are uniformly distributed on the resistive layer 2. The conductive protrusions 4 are uniformly distributed on the resistive layer 2, so that the peel strength of each connection part of the conductive layer 1 and the resistive layer 2 is relatively close, and the connection stability between the conductive layer 1 and the resistive layer 2 is further ensured. In a specific implementation, a plurality of conductive bumps 4 may be formed on the resistive layer 2 by a conventional process such as an electroplating process, and the conductive bumps 4 are not adhered to each other. Furthermore, the height of the conductive bumps 4 is set to be consistent, so that the direct adhesive force between the conductive layer 1 and the resistance layer 2 is further improved, and the whole embedded resistance metal foil is smoother. When the conductive bumps 4 are uniformly distributed and the height is set to be uniform, the effect is better when the two aspects are combined.

In specific application, the thickness of the bonding layer 6 needs to be set according to actual requirements, if the thickness of the bonding layer 6 is too small, the adhesion of the conductive layer 1 cannot be effectively improved, and if the thickness of the bonding layer 6 is too large, the internal stress in the bonding layer 6 is too large, so that the buried-resistance metal foil is prone to cracking in a subsequent punching process. Moreover, the thickness of the adhesive layer 6 is too large, which causes the thickness of the buried barrier metal foil to be too large, and thus the electronic product is not light and thin.

It should be noted that, the embedded resistive metal foil disclosed in this embodiment is used for manufacturing a resistive circuit, where the conductive layer 1 is manufactured through a process to form a conductive end, and the resistive layer 2 is manufactured through a process to form a resistor, when the embedded resistive metal foil is applied, the embedded resistive metal foil may be firstly laminated on a circuit board, and the embedded resistive metal foil is manufactured through a process to form a resistive circuit, or the embedded resistive metal foil is firstly laminated on a resistive circuit, and then the resistive circuit is laminated on the circuit board, so that the conductive end is conducted with an electrical device or a circuit on the circuit board, and the conductive end is conducted with the resistor, so that a conducted circuit is formed. The conductivity of the conductive layer 1 is greater than that of the resistive layer 2, and the conductivity of the conductive layer 1 is 2 to 1000 times that of the resistive layer 2. Of course, the conductivity of the conductive layer 1 and the conductivity of the resistive layer 2 may be set according to actual use requirements, and will not be further described herein.

Specifically, the resistance layer 2 in this embodiment includes any one metal of nickel, chromium, platinum, palladium and titanium, or an alloy including at least two combinations of nickel, chromium, platinum, palladium, titanium, silicon and phosphorus, for example, the resistance layer 2 may include an alloy such as a nickel-phosphorus alloy, or a metal such as nickel, or a combination of different metals such as nickel metal and chromium metal, or a combination of a nickel-phosphorus alloy and nickel metal, or a combination of nickel metal and silicon. Of course, the resistive layer 2 may also be made of other materials, which will not be described herein.

Specifically, the conductive layer 1 in this embodiment includes any one or more of aluminum, silver, copper, and gold. When the conductive layer 1 is made of copper, the buried resistance metal foil is a buried resistance copper foil product, and of course, the conductive layer 1 may also be made of other materials with good conductivity, which is not described herein. The thickness of the conductive layer 1 in this embodiment is 2 to 20 micrometers. The thickness of the conducting layer 1 is set to be 2-20 micrometers so as to meet the requirement of manufacturing a printed board fine circuit, and certainly, the thickness of the conducting layer 1 can be set to be other values according to the actual use requirement, which is not described herein.

In an optional embodiment, the buried barrier metal foil further includes a dielectric layer, and the dielectric layer is disposed on a surface of the resistive layer 2 away from the conductive layer 1. Specifically, the dielectric layer plays a role in carrying, and in a specific implementation, referring to fig. 3, the resistive layer 2 may be formed on the dielectric layer 7, and the dielectric layer 7 may protect the resistive layer 2. The dielectric layer 7 may be, but is not limited to, Polyimide (PI), in which case the dielectric layer 7 serves as a carrier, and the resistive layer 2 is formed on the dielectric layer 7, and the dielectric layer 7 does not need to be torn off when applied to a circuit board.

In another aspect, as shown in fig. 4, the dielectric layer may be a peelable carrier layer 5, which may be, but is not limited to, polyethylene terephthalate (PET), and where the peelable carrier layer 5 needs to be torn off when used in a circuit board. It will be readily appreciated that the peelable carrier layer 5 is also coated with the glue layer 3 to facilitate peeling, i.e. in the version shown in figure 4 the dielectric layer comprises the peelable carrier layer 5 and the glue layer 3. The thickness of the glue layer 3 can be set to be 10-100 angstroms, and the glue layer 3 is a peeling layer or a peeling agent, so that the peelable carrier layer 5 and the resistive layer 2 have good peeling strength, that is, the peelable carrier layer 5 is not easy to fall off, and the peelable carrier layer 5 can be well peeled off from the resistive layer 2 when the buried resistance metal foil is used subsequently. In addition, the glue layer 3 may also function to adjust the roughness of the resistive layer 2.

Correspondingly, the embodiment of the utility model provides a still provide a printing board, the printing board include bury hinder the metal forming. For example, when the resistive circuit is fabricated, the conductive layer 1 and the resistive layer 2 of the buried metal foil are etched according to a predetermined resistive circuit pattern, so as to obtain the desired resistive circuit. Illustratively, when a buried resistor needs to be designed in a certain area of the printed circuit board, the conductive layer 1 of the preset area may be etched to expose the resistive layer 2 of the preset area, and the corresponding conductive bump 4 on the preset area may be etched without etching or with etching.

Accordingly, referring to fig. 5, an embodiment of the present invention further provides a method for manufacturing a buried resistance metal foil, including:

step S101, forming the resistive layer 2;

step S102, forming a plurality of conductive bumps 4 distributed at intervals on one surface of the resistance layer 2;

step S103, forming an adhesive layer 6 on one surface of the resistance layer 2 on which the conductive bumps 4 are formed, and making a plurality of conductive bumps 4 protrude from the adhesive layer 6;

step S104, forming a conductive layer 1 on the adhesive layer 6, so that the conductive layer 1 covers the adhesive layer 6 and the conductive bump 4; wherein the conductive bump 4 is made of a different material than the conductive layer 1.

In an alternative embodiment, the step S101 "forming the resistive layer 2" specifically includes:

providing a medium layer 7;

forming a resistance layer 2 on one surface of the dielectric layer 7; in particular implementations, the resistive layer 2 may be formed by a conventional process such as a coating or plating process.

In the present embodiment, a plurality of conductive bumps 4 may be formed on the resistive layer 2 by a conventional process such as a plating process. Since the conductive bumps 4 are distributed on one surface of the resistive layer 2 at intervals, the conductive bumps 4 are not adhered to each other. In the middle of concrete implementation, because factors such as process error, probably lead to the 4 adhesions of the adjacent electrically conductive arch of a plurality of, nevertheless the influence can not be very big, consequently the utility model discloses easily realize form interval distribution's electrically conductive arch 4 on the resistance layer 2, its technological requirement need not too harsh, is favorable to reduction in production cost.

In an alternative embodiment, in the step S104 "forming the conductive layer 1 on the adhesive layer 6 so that the conductive layer 1 covers the adhesive layer 6 and the conductive bumps 4", the conductive layer 1 may be formed on the adhesive layer 6 by a conventional process such as one or more of electroplating, coating, or vacuum sputtering. In a specific implementation, the conductive layer 1 may be formed by combining a plurality of processes, for example, a vacuum sputtering process is used to sputter a metal layer on the adhesive layer 6, and then an electroplating process is used to form another metal layer on the sputtered metal layer, where the two metal layers together form the conductive layer 1. Of course, the process of forming the conductive layer 1 on the adhesive layer 6 is more, and will not be further described herein.

In summary, the buried resistance metal foil of the embodiment of the present invention includes a resistance layer 2, a conductive layer 1, an adhesive layer 6 and a plurality of conductive bumps 4, an adhesive layer 6 and conductive protrusions 4 are provided between the resistive layer 2 and the conductive layer 1, and a plurality of conductive protrusions 4 are spaced apart on one side of the resistive layer 2 and protrude from the adhesive layer 6, the conductive layer 1 is arranged on the surface of the bonding layer 6 far away from the resistance layer 2, so that the conductive layer 1 covers the bonding layer 6 and the conductive protrusion 4, the problem that the resistance value of each direction of the resistance layer is different due to the fact that the copper foil with uneven surface roughness is directly contacted with the resistance layer in the prior art is solved, the difference of the resistance value of each direction of the resistance layer in each direction is reduced, and then be convenient for design high accuracy buried resistor, in addition, tie coat 6 can also increase the adhesion of conducting layer 1 and protect resistance layer 2.

Example two

As shown in fig. 6, the present embodiment is different from the first embodiment only in that a plurality of conductive bumps 4 of the present embodiment are distributed on one surface of the conductive layer 1 at intervals, and a plurality of conductive bumps 4 are covered by the resistive layer 2. The technical effect of this embodiment is the same as that of the first embodiment, but the embodiment is different in the preparation method. In one embodiment of the present invention, a conductive bump 4 is formed on a conductive layer 1, an adhesive layer 6 is formed on one surface of the conductive bump 4, and a resistive layer 2 is additionally formed, and then the surface of the conductive layer 1 provided with the conductive bump 4 is attached to the resistive layer 2.

EXAMPLE III

The present embodiment is different from the first embodiment only in that the plurality of conductive protrusions of the present embodiment are spaced apart on the adhesive layer, so that the conductive protrusions and the adhesive layer are both between the conductive layer and the resistive layer.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and replacements can be made without departing from the technical principle of the present invention, and these modifications and replacements should also be regarded as the protection scope of the present invention.

Claims (8)

1. The buried resistance metal foil is characterized by comprising a resistance layer, a conductive layer, an adhesive layer and a plurality of conductive bulges;

the tie coat is located the resistive layer with between the conducting layer, a plurality of electrically conductive protruding interval distribution is in and the protrusion on the one side of resistive layer the tie coat, and a plurality of electrically conductive protruding quilt the conducting layer covers, or a plurality of electrically conductive protruding interval distribution is in on the one side of conducting layer, and is a plurality of electrically conductive protruding quilt the resistive layer covers, or a plurality of electrically conductive protruding interval distribution is on the tie coat.

2. The buried resistive metal foil of claim 1, wherein a plurality of the conductive bumps are uniformly distributed on the resistive layer or the conductive layer.

3. The buried resistive metal foil of claim 1, wherein the plurality of conductive bumps are a first metal particle and/or a particle cluster consisting of a plurality of second metal particles.

4. The buried resistive metal foil of claim 1, wherein the conductive bump has a height of 0.5 to 20 microns.

5. The buried resistive metal foil of claim 1, wherein the conductive layer has a thickness of 2 to 20 microns.

6. The buried resistive metal foil of claim 1, wherein the conductive layer is any one of aluminum, silver, copper, and gold.

7. The buried resistive metal foil of claim 1, wherein the conductive layer has an electrical conductivity 2 to 1000 times that of the resistive layer.

8. The buried resistive metal foil of any one of claims 1 to 7, further comprising a dielectric layer disposed on a surface of the resistive layer remote from the conductive layer.

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