CN214014636U - Buried resistance metal foil and printed board - Google Patents
Buried resistance metal foil and printed board Download PDFInfo
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- CN214014636U CN214014636U CN202022694293.1U CN202022694293U CN214014636U CN 214014636 U CN214014636 U CN 214014636U CN 202022694293 U CN202022694293 U CN 202022694293U CN 214014636 U CN214014636 U CN 214014636U
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Abstract
The utility model relates to a printing board technical field discloses bury and hinder metal forming and printing board, buries and hinders metal forming and include the adjustment layer and bury and hinder the metal forming body, it includes resistance layer and conducting layer to bury and hinder the metal forming body, the adjustment layer is located the one side of resistance layer, and the another side of resistance layer is located to the conducting layer, the resistance tolerance in the unit area of predetermineeing of arbitrary department on the resistance layer is at-10% ~ 10% within range. The utility model discloses a set up the regulating layer, can effectively adjust the roughness of resistance layer, make resistance layer roughness everywhere even to the resistance of resistance layer is even, and then is convenient for design the buried resistor of high accuracy.
Description
Technical Field
The utility model relates to a printing board technical field especially relates to a bury and hinder metal forming and printing board.
Background
With the development trend of miniaturization of electronic products, higher requirements are put on the packaging density and the volume of the electronic products, and embedding passive devices such as resistors into a printed board is an effective means for reducing the size of the electronic products.
At present, the existing printed board with the buried resistor generally comprises a resistor layer and a copper foil layer; the copper foil layer is directly made of finished copper foil, and the copper foil is usually pressed with the resistance layer, so that the printed board with the buried resistance is manufactured. In recent years, in order to ensure tight connection between the copper foil layer and the resistance layer, the surface of the copper foil layer connected with the resistance layer is generally set to have a certain roughness, but the roughness of the copper foil layer is not uniform under microscopic conditions, so that the surface roughness of the resistance layer 20 close to the copper foil layer 10 is not uniform, the resistance value of the resistance layer 20 has directionality, that is, the resistance value per unit area in one direction is larger, the resistance value per unit area in the other direction is smaller, and the design precision of the buried resistor is seriously affected.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a metal forming and printing board, its each roughness that can the adjusting resistance layer makes the resistance of resistance layer more even, and then is convenient for design the buried resistor of high accuracy.
In order to solve the technical problem, the utility model provides a bury and hinder metal forming, include the regulating layer and bury and hinder the metal forming body, it includes resistance layer and conducting layer to bury and hinder the metal forming body, the regulating layer is located the one side of resistance layer, the conducting layer is located the another side of resistance layer, the resistance tolerance in the unit area is predetermine to arbitrary department on the resistance layer is at-10% ~ 10% within range.
Preferably, the buried resistance metal foil further comprises a plurality of conductive bumps;
the conductive protrusions are distributed between the resistance layer and the conductive layer at intervals, the conductive layer is plated on one surface, close to the conductive protrusions, of the resistance layer, and the conductive protrusions are covered by the conductive layer.
Preferably, each of the plurality of conductive protrusions is a particle cluster composed of first metal particles and/or a plurality of second metal particles.
Preferably, the buried resistance metal foil further comprises a carrier layer, and the carrier layer is arranged on one surface of the adjusting layer far away from the resistance layer.
Preferably, the peel strength between the carrier layer and the adjustment layer is greater than the peel strength between the adjustment layer and the resistive layer.
Preferably, the thickness of the conductive layer is 2 to 20 micrometers.
Preferably, the conductive layer comprises any one or more of aluminum, silver, copper and gold.
Preferably, the conductivity of the conductive layer is 2 to 1000 times that of the resistive layer.
Preferably, the resistive layer includes any one metal of nickel, chromium, platinum, palladium and titanium, or an alloy including at least two combinations of nickel, chromium, platinum, palladium, titanium, silicon and phosphorus.
In order to solve the same technical problem, the embodiment of the utility model provides a still provide a printing board, including foretell bury hinder the metal forming body that buries among the metal forming.
Compared with the prior art, the utility model provides a bury and hinder metal forming and printed board, bury and hinder the metal forming and include the regulating layer and bury and hinder the metal forming body, the one side on resistance layer is located to the regulating layer, and the another side on resistance layer is located to the conducting layer. Through setting up the regulation layer, can effectively adjust the roughness of resistance layer, make the roughness everywhere of resistance layer even to the resistance of resistance layer is even, and then is convenient for design the buried resistor of high accuracy.
Drawings
Fig. 1 is a schematic structural diagram of a buried resistance metal foil according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a buried resistance metal foil with a carrier layer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a buried resistance metal foil including conductive bumps according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for manufacturing a buried resistance metal foil according to a third embodiment of the present invention.
Wherein, 1, a carrier layer; 2. a conditioning layer; 3. a buried resistance metal foil body; 31. a resistive layer; 32. a conductive layer; 4. and a conductive bump.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Example one
Referring to fig. 1, a schematic structural diagram of a buried resistance metal foil according to an embodiment of the present invention is shown.
In the embodiment of the present invention, the buried metal foil includes the adjusting layer 2 and the buried metal foil body 3, the buried metal foil body 3 includes the resistance layer 31 and the conducting layer 32, the adjusting layer 2 is located one side of the resistance layer 31, the conducting layer 32 is located another side of the resistance layer 31, the resistance tolerance in the preset unit area of any one place on the resistance layer 31 is in the range of-10%.
In the embodiment of the utility model provides an in, bury and hinder the foil and include adjustment layer 2 and bury and hinder foil body 3, bury and hinder foil body 3 and include resistive layer 31 and conducting layer 32, adjustment layer 2 is located resistive layer 31's one side, conducting layer 31 is located resistive layer 32's another side. Through setting up adjusting layer 2, can effectively adjust the roughness of resistive layer 31, make resistive layer 31 roughness everywhere even to resistive layer 31's resistance is even, and then is convenient for design the buried resistor of high accuracy.
In the embodiment of the present invention, the resistance tolerance of any one position on the resistance layer 31 in the preset unit area is in the range of-10% to 10%. The preset unit area may be, for example, 1cm by 1cm, and of course, other unit areas may be selected according to actual requirements. The resistance tolerance calculation formula includes obtaining resistance values (R1, R2, R3, … … Rn) of preset unit areas at a plurality of different positions, calculating an average value Rv of the plurality of resistance values, where Rv is (R1+ R2+ R3+ … … + Rn)/n, calculating a difference between each resistance value and the average value, dividing the difference by the average value, and performing percentage calculation to obtain the resistance tolerance, that is, D1 { (R1-Rv)/Rv }%, D2 { (R2-Rv)/Rv }%, … …, D1, and D2 respectively represent resistance tolerances corresponding to the resistance values at the different positions, and D1 and D2 both fall within a range of-10% to + 10%. The range of the resistance tolerance indicates that the resistance tolerance of the resistance value in each preset unit area falls within the range. Preferably, the resistance tolerance in a preset unit area at any position on the resistance layer 31 is in the range of-7% to + 7%, and more preferably, the resistance tolerance is in the range of-5% to + 5%, so as to design a buried resistor with high precision.
Referring to fig. 2, in an alternative embodiment, the buried-resistance metal foil further includes a carrier layer 1, and the carrier layer 1 is disposed on a side of the adjusting layer 2 away from the resistive layer 31.
In the embodiment of the present invention, the carrier layer 1 is preferably, but not limited to, made of Polyimide (PI) or polyethylene terephthalate (PET). In addition, the thickness of the carrier layer 1 of this embodiment can be set according to the actual use requirement, and will not be further described herein. Specifically, the dielectric layer 4 is a peeling layer or a peeling agent, and the thickness of the dielectric layer 4 is 10 angstroms to 100 angstroms, but of course, the thickness of the dielectric layer 4 may also be set to other values according to actual use requirements, which is not described herein. By arranging the dielectric layer 4 between the carrier layer 1 and the resistive layer 31, the carrier layer 1 and the resistive layer 31 have good peel strength, i.e. the carrier layer 1 is not easy to fall off, and the carrier layer 1 can be well peeled off from the resistive layer 31 when the buried resistance metal foil is used later. In addition, the dielectric layer 4 may also function to adjust the roughness of the resistive layer 31.
Referring to fig. 3, in an alternative embodiment, the buried barrier metal foil further includes a plurality of conductive bumps 4; the conductive protrusions 4 are distributed between the resistor layer 31 and the conductive layer 32 at intervals, the conductive protrusions 4 can be formed on the resistor layer 31 and also on the conductive layer 32, the conductive layer 32 is plated on the surface, close to the conductive protrusions 4, of the resistor layer 31, and the conductive protrusions 4 are covered by the conductive layer 32, so that the problem that resistance values of unit areas of the resistor layer in all directions are different due to the fact that copper foils with uneven surface roughness directly contact with the resistor layer in the prior art to cause unevenness is solved, the difference of the resistance values of the resistor layer in all directions in unit areas is reduced, and high-precision buried resistors are designed conveniently.
It should be noted that, in the embodiment of the present invention, the conductive protrusion 4 is disposed between the resistive layer 31 and the conductive layer 32, so as to avoid the conductive layer 32 directly contacting the resistive layer 31, and increase the adhesion between the conductive layer 32 and the resistive layer 31. The conductive bumps 4 are distributed at intervals, so that when the conductive bumps 4 are adhered to each other, current flows to a path formed by the adhesion of the conductive bumps 4 through the conductive end formed by the conductive layer 32, so that the resistive layer 31 loses effect and the use of the resistive layer 31 is prevented from being influenced. In this embodiment, the conductive bumps 4 are distributed on one surface of the resistive layer 31 at intervals, that is, the conductive bumps 4 are not adhered to each other, so that the conductive bumps 4 are not conducted to each other to form a resistor. In addition, in the middle of concrete implementation, because factors such as process error, it is adjacent probably to lead to a plurality of electrically conductive 4 adhesion, but the influence can not be very big, consequently the utility model discloses easily realize form interval distribution's electrically conductive 4 on the resistance layer 31, its technological requirement need not too harsh, is favorable to reduction in production cost.
Specifically, each of the conductive bumps 4 is a first metal particle or a particle cluster composed of a plurality of second metal particles, or a part of the conductive bumps 4 among the plurality of conductive bumps are first metal particles, and another part of the conductive bumps 4 among the plurality of conductive bumps are particle clusters composed of a plurality of second metal particles. The materials of the first metal particles and the second metal particles may be the same or different. The first metal particles are individually granular, the first metal particles are distributed at intervals, and the particle clusters formed by a plurality of second metal particles are also distributed at intervals. When the conductive protrusions 4 are particle clusters composed of a plurality of second metal particles, the surface roughness thereof is increased relative to that of a single first metal particle, thereby advantageously increasing the adhesion of the conductive layer 32, so that the conductive layer 32 can be reliably connected to the resistive layer 31.
As an alternative embodiment, the first metal particles are of a different material than the conductive layer 32. The first metal particles and the conductive layer 32 are made of different materials and have different resistivities, and when the resistivity of the first metal particles is lower than that of the conductive layer 32, the first metal particles have less influence on the resistive circuit after the resistive circuit is formed by the buried metal foil. Accordingly, the second metal particles may also be selected to be different from the material of the conductive layer 32. The material of both the first metal particles and the second metal particles may be the same or different.
Specifically, the height H of the conductive bump 4 in the present embodiment is 0.5 to 20 micrometers. In a specific application, if the height of the conductive bump 4 is too small, a good adhesion force cannot be added to the conductive layer 32 and the resistive layer 31, and if the height of the conductive bump 4 is too large, a pinhole may be generated in the conductive layer 32, thereby affecting the performance of the conductive layer 32. In the present embodiment, the height of the conductive bump 4 is set to 0.5 to 20 micrometers, so that the conductive bump 4 has a good effect of increasing the adhesion between the conductive layer 32 and the resistive layer 31. Of course, the height of the conductive bump 4 may also be set to other values according to the actual use requirement, and further details are not described herein.
It should be noted that the conductive bumps 4 may be randomly distributed on the resistive layer 31, and in order to further ensure the connection stability between the conductive layer 32 and the resistive layer 31, the conductive bumps 4 in this embodiment are uniformly distributed on the resistive layer 31. The plurality of conductive protrusions 4 are uniformly distributed on the resistive layer 31, so that the peel strength of each connection between the conductive layer 32 and the resistive layer 31 is relatively close, and the connection stability between the conductive layer 32 and the resistive layer 31 is further ensured. In a specific implementation, a plurality of conductive bumps 4 may be formed on the resistive layer 31 by a conventional process such as an electroplating process, and the conductive bumps 4 are not adhered to each other. Furthermore, the height of the conductive bump 4 is set to be consistent, so that the direct adhesive force between the conductive layer 32 and the resistor layer 31 is further improved, and the whole embedded metal foil is more flat. When the conductive bumps 4 are uniformly distributed and the height is set to be uniform, the effect is better when the two aspects are combined.
In the embodiment of the present invention, in order to facilitate the conductive layer 32 to be plated on the resistance layer 31, preferably, the conductive layer 32 of the embodiment is formed on the resistance layer 31 by using any one or more processes of chemical plating, physical vapor deposition, chemical vapor deposition, evaporation plating, sputter plating, electroplating, and hybrid plating.
It should be noted that, here is only one specific implementation manner of plating the conductive layer 32 on the resistance layer 31, the embodiment of the present invention is not limited to the specific manner of plating the conductive layer 32 on the resistance layer 31, and those skilled in the art can also plate the conductive layer 32 on the resistance layer 31 in other manners according to the specific conditions in practical applications.
In the embodiment of the utility model provides an in, the disclosed metallic foil that buries of this embodiment is used for making resistive circuit, wherein conducting layer 32 forms the electrically conductive end through the technology preparation, resistive layer 31 forms resistance through the technology preparation, during the application, can bury earlier and hinder the metallic foil pressfitting on the circuit board, will bury through the technology preparation and hinder the metallic foil and form resistive circuit, perhaps bury earlier and hinder the metallic foil and form resistive circuit, again with resistive circuit pressfitting on the circuit board, the electrically conductive end switches on with electrical part or circuit on the circuit board, electrically conductive end switches on with resistance, make to form the circuit that switches on. The conductivity of the conductive layer 32 is greater than that of the resistive layer 31. Illustratively, the conductivity of the conductive layer 32 is 2 to 1000 times the conductivity of the resistive layer 31. Of course, the conductivity of the conductive layer 32 and the conductivity of the resistive layer 31 can be set according to actual use requirements, and will not be described herein.
In the embodiment of the present invention, the conductive layer 32 in the present embodiment includes any one or more of aluminum, silver, copper, and gold. When the conductive layer 32 is made of copper, the buried resistance metal foil is a buried resistance copper foil product; of course, the conductive layer 32 can also be made of other materials with good conductivity, which will not be described herein.
In addition, the thickness of the conductive layer 32 in the present embodiment is 2 to 20 micrometers. The thickness of the conductive layer 32 is set to be 2 micrometers to 20 micrometers so as to meet the requirement of manufacturing a printed board fine circuit, and of course, the thickness of the conductive layer 32 may be set to be other values according to the actual use requirement, which is not described herein.
In the embodiment of the present invention, the resistance layer 31 in this embodiment includes any one of nickel, chromium, platinum, palladium and titanium, or an alloy including at least two combinations of nickel, chromium, platinum, palladium, titanium, silicon and phosphorus, for example, the resistance layer 31 may include an alloy such as nickel-phosphorus alloy, or a metal such as nickel, or a combination of different metals such as nickel metal and chromium metal, or a combination of nickel-phosphorus alloy and nickel metal, or a combination of nickel metal and silicon. Of course, the resistive layer 31 may also be made of other materials, which will not be described herein.
In addition, the thickness of the resistive layer 31 of this embodiment may be set according to actual use requirements, and will not be further described herein.
Correspondingly, the embodiment of the utility model provides a still provide a printing board, including foretell bury hinder among the metal forming bury hinder metal forming body 3. For example, when the resistive circuit is fabricated, the conductive layer 32 and the resistive layer 31 of the buried metal foil body 3 are etched according to a predetermined resistive circuit pattern, so as to obtain the desired resistive circuit. When it is necessary to design a buried resistor in a certain area of the printed board, the conductive layer 32 in a predetermined area may be etched to expose the resistive layer 31 in the predetermined area.
Example two
The buried resistance metal foil in this embodiment is different from that in the first embodiment in that the peel strength between the carrier layer 1 and the adjustment layer 2 is greater than the peel strength between the adjustment layer 2 and the resistance layer 31. By making the peel strength between the carrier layer 1 and the adjustment layer 2 greater than the peel strength between the adjustment layer 2 and the resistance layer 31, peeling between the carrier layer 1 and the adjustment layer 2 is made less likely to occur, thereby enabling the adjustment layer 2 to be peeled off along with the carrier layer 1.
In the embodiment of the present invention, other structures and working principles of the buried resistance metal foil of the present embodiment are the same as those of the first embodiment, and are not described herein.
EXAMPLE III
Referring to fig. 4, a schematic flow chart of a method for manufacturing a buried resistance metal foil according to a third embodiment of the present invention is shown.
The embodiment of the utility model provides a preparation method of bury and hinder metal foil is applicable to preparation embodiment one bury and hinder metal foil, bury and hinder metal foil' S preparation method includes following step S11-S14:
s11, forming a regulating layer; in particular implementations, it may be formed on a carrier layer.
S12, forming a resistance layer on one surface of the adjusting layer; in particular, the adjusting layer can be formed on the side of the adjusting layer away from the carrier layer;
and S13, plating a conductive layer on one surface of the resistance layer far away from the adjusting layer.
Specifically, in step S12, the forming a resistive layer on the adjustment layer specifically includes:
a resistive layer is formed on the adjustment layer using a conventional process such as a coating or plating process.
In step S13, the plating a conductive layer on the surface of the resistive layer away from the adjustment layer specifically includes:
and plating the surface of the resistance layer, which is far away from the regulating layer, by adopting any one or more processes of chemical plating, physical vapor deposition, chemical vapor deposition, evaporation plating, sputtering plating, electroplating and mixed plating to form the conducting layer.
Of course, here is only a specific implementation manner of plating the conductive layer on the side of the resistance layer away from the adjustment layer, and the embodiment of the present invention is not limited to the specific implementation manner of plating the conductive layer on the side of the resistance layer away from the adjustment layer, and those skilled in the art can also plate the conductive layer on the side of the resistance layer away from the adjustment layer by other manners according to the specific conditions in practical application.
In addition, it should be noted that the method for preparing the buried barrier metal foil provided in this embodiment is only one example for preparing the buried barrier metal foil described in the first embodiment, and the buried barrier metal foil described in the first embodiment may also be prepared by other preparation methods. In addition, the method for preparing the buried barrier metal foil in the second embodiment may specifically refer to the method for preparing the buried barrier metal foil provided in this embodiment, and will not be further described herein.
To sum up, the utility model provides a bury and hinder metal forming and printed board buries and hinders metal forming and include the adjustment layer and bury and hinder metal forming body 3, bury and hinder metal forming body 3 including resistance layer 31 and conducting layer 32, the adjustment layer is located the one side of resistance layer, the conducting layer is located the another side of resistance layer. Through setting up the regulation layer, can effectively adjust the roughness of resistance layer, make the roughness everywhere of resistance layer even to the resistance of resistance layer is even, and then is convenient for design the buried resistor of high accuracy.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and replacements can be made without departing from the technical principle of the present invention, and these modifications and replacements should also be regarded as the protection scope of the present invention.
Claims (9)
1. The embedded resistance metal foil is characterized by comprising an adjusting layer and an embedded resistance metal foil body, wherein the embedded resistance metal foil body comprises a resistance layer and a conducting layer, the adjusting layer is arranged on one surface of the resistance layer, the conducting layer is arranged on the other surface of the resistance layer, and the resistance tolerance in a preset unit area at any position on the resistance layer is in the range of-10%.
2. The buried barrier metal foil of claim 1, further comprising a plurality of conductive bumps;
the conductive protrusions are distributed between the resistance layer and the conductive layer at intervals, the conductive layer is plated on one surface, close to the conductive protrusions, of the resistance layer, and the conductive protrusions are covered by the conductive layer.
3. The buried resistive metal foil of claim 2, wherein the plurality of conductive bumps are a first metal particle and/or a particle cluster consisting of a plurality of second metal particles.
4. The embedded resistive metal foil of claim 1, further comprising a carrier layer disposed on a side of the adjustment layer remote from the resistive layer.
5. The buried resistive metal foil of claim 4, wherein a peel strength between the carrier layer and the adjustment layer is greater than a peel strength between the adjustment layer and the resistive layer.
6. The buried resistive metal foil of any of claims 1-5, wherein the conductive layer has a thickness of 2 microns to 20 microns.
7. The buried resistive metal foil of any one of claims 1-5, wherein the conductive layer is any one of aluminum, silver, copper, gold.
8. The buried resistive metal foil of any of claims 1-5, wherein the conductivity of the conductive layer is 2-1000 times the conductivity of the resistive layer.
9. A printed board characterized by being made of the buried resistance metal foil according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022694293.1U CN214014636U (en) | 2020-11-19 | 2020-11-19 | Buried resistance metal foil and printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022694293.1U CN214014636U (en) | 2020-11-19 | 2020-11-19 | Buried resistance metal foil and printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214014636U true CN214014636U (en) | 2021-08-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022694293.1U Active CN214014636U (en) | 2020-11-19 | 2020-11-19 | Buried resistance metal foil and printed board |
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|---|---|
| CN (1) | CN214014636U (en) |
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2020
- 2020-11-19 CN CN202022694293.1U patent/CN214014636U/en active Active
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| TR01 | Transfer of patent right |
Effective date of registration: 20211227 Address after: 510530 6th floor, building A5, No. 11, Kaiyuan Avenue, Guangzhou hi tech Industrial Development Zone, Guangzhou, Guangdong Province Patentee after: GUANGZHOU FANG BANG ELECTRONICS Co.,Ltd. Patentee after: Zhuhai Dachuang Electronics Co., Ltd Address before: 510530 6th floor, building A5, No. 11, Kaiyuan Avenue, Guangzhou hi tech Industrial Development Zone, Guangzhou, Guangdong Province Patentee before: GUANGZHOU FANG BANG ELECTRONICS Co.,Ltd. |
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