JPH0334532A - Semiconductor substrate - Google Patents

Abstract

PURPOSE:To obtain a high-quality semiconductor substrate which is free from defects such as a dislocation and the like by a method wherein an insulating film whose softening point is at a temperature lower than a growth temperature of a III-V compound semiconductor single-crystal layer or a III-V mixed-crystal semiconductor layer is laminated on a substrate, an Si substrate is laminated on the insulating film and a III-V compound semiconductor single-crystal layer or a III-V mixed-crystal semiconductor layer is grown on the Si substrate. CONSTITUTION:A BPSG glass (of a softening temperature at about 350 deg.C) is laminated as an insulating film 2 on an Si substrate (of a coefficient of thermal expansion at 2.5X10<-6> deg.C<-1>) 1 by a plasma CVD method; after that, an Si substrate whose plane orientation is (100) plane is piled up on it; the Si substrate is etched so as to be a thin layer of about 1mum in thickness; an Si layer 3 is manufactured. This Si substrate is set inside an MOCVD apparatus) a GaAs film 4 about 5mm is grown as a III-V compound semiconductor single-crystal layer by a two-stage growth method.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a method for forming a monocrystalline layer of m-v group compound semiconductor such as InP, cap, GaAS, etc. on a silicon substrate, or a layer of m-v compound semiconductor such as GaAs,
AlGaAs, Gaxl, which is a mixed crystal of GaP, InP, etc.
n+-, p, GaP, As1-.

Regarding a semiconductor substrate characterized by a structure including an m-v group compound semiconductor single crystal layer for obtaining an m-v group mixed crystal semiconductor layer, or an m-v group mixed crystal semiconductor layer and an insulating layer such as a glass layer. .

[Conventional technology]

Compound semiconductor single crystal such as GaAs, GaP, InP, etc. or AlGaA which is a mixed crystal such as QaAs, GaP, InP, etc.
s, QaX In+-, P, GaP.

Compound mixed crystal semiconductors such as A s l-x are being utilized for high performance and highly functional devices by taking advantage of their excellent characteristics. However, compound semiconductors are generally expensive and have problems such as difficulty in obtaining large-area, high-quality substrate crystals. In an attempt to overcome these problems, we used cheap, high-quality, lightweight, and large-area silicon as a substrate, and layered compound semiconductors such as a compound semiconductor single crystal layer or a compound mixed crystal semiconductor layer on this silicon substrate. However, attempts have been made to manufacture devices using this compound semiconductor layer.

Although several structures for manufacturing compound semiconductor substrates using such silicon substrates have been proposed in the past, they are still inferior to bulk crystals in terms of crystal quality.

The reason for this is that the thermal expansion coefficient and lattice constant of the m-v group raw conductor are different from those of silicon. In particular, the thermal stress based on the difference in coefficient of thermal expansion is 10"dyn/cm" or more, which is the main cause of defects and cracks. That is, for example, as a compound semiconductor layer on a Si substrate at a growth temperature Tg,
For example, when cooling begins after growing a GaAs layer, the thermal expansion coefficient α1 of the Si substrate and the thermal expansion coefficient α of GaAs0
. A stress σ7 is generated based on the difference from aAi. Here σ
i is expressed by the following formula. That is, σ7=(αGaAl−αst)・(Tg−T)
・Ecaas/(1+l')...(1) Here, σ is the stress acting between the Si substrate and the GaAs layer,
α6. A3 is the thermal expansion coefficient of GaAs, α3 is the thermal expansion coefficient of the Si substrate, Tg is the growth temperature, T is the temperature after cooling, ν
is the product of the ratio of the thicknesses of GaAS and St and the ratio of the elastic constants, and E GIIAI is the elastic constant of GaAs.

This stress σ7 is unavoidable as long as Si and GaAs are in close contact with each other, and is alleviated by introducing cracks and defects into the GaAs layer, which is thinner than the Si substrate.

Conventionally, in order to solve this problem, a structure has been proposed in which a layer for reducing the difference in thermal expansion coefficient is inserted between the m-V group raw conductor layer and the substrate.

For example, there is a structure in which a low melting point material layer is interposed between a ■-V group semiconductor and a substrate such as Si or glass. According to ``Batteries and Methods for Producing the Same'', Sn, Ga, I
A structure in which n or the like is interposed, or a structure in which a Ge single crystal is used instead of a solar cell and an m-v crystal is grown on it are shown. However, in this method, since the solar cell layer is produced and then attached to the substrate, its area is limited to the size of the ■-■ group substrate (eg, 4 inches or less in diameter). In addition, with the method of pasting a Ge layer, it is generally difficult to obtain crystals with a large area compared to Si.
There are problems similar to those mentioned above.

Another structure is one in which a plurality of semiconductor substrates of different types are laminated and integrated. Japanese Patent Publication No. 61-18221
According to Publication No. 5, titled "Method for manufacturing semiconductor substrate," InP is formed on a Si substrate.

Furthermore, a structure is shown in which GaAs is placed next to each other, the mirror surfaces are brought into close contact with each other, and the mirror surfaces are heat-treated and integrated. In this method, the difference in thermal expansion coefficient between adjacent materials is 2X10-'°C, and the bonding temperature is at most 200°C.
Thermal strain is significantly reduced. However, the size of the resulting semiconductor substrate is limited to the size of the ■-v group semiconductor, and there are economical problems because InP, which is more expensive than GaAS, is used in the intermediate layer.

In addition, Japanese Patent Application Laid-Open No. 61-219182, the title of the invention “
The manufacturing method for compound semiconductor devices involves creating a highly concentrated impurity layer on a silicon substrate, forming a thin layer of Si on top of it, and
Furthermore, a structure is shown in which a large-area, lightweight compound semiconductor can be obtained by growing an m-v group bioconductor crystal, then chemically etching the Si substrate and stopping the etching with a highly concentrated impurity layer. However, with this method, compound semiconductors are grown on a thick silicon substrate, so
It has the obvious disadvantage that it does not have the effect of reducing thermal strain and does not work to improve the quality of compound semiconductors.

[Problem to be solved by the invention]

An object of the present invention is to provide a semiconductor substrate in which a high-quality m-v group compound semiconductor single crystal layer or a high-quality m-v group compound semiconductor mixed crystal semiconductor layer without cracks or defects is grown on an St substrate. There is a particular thing.

[Means to solve the problem]

While the conventional technology has a structure in which an m-v group compound semiconductor single crystal layer or a III-V group compound semiconductor crystal layer is grown on a thick Si substrate, the present invention has a structure in which a low softening material layer is grown on a thick Si substrate. The structure of the semiconductor substrate is characterized by a structure in which a desired m-v group compound semiconductor single crystal layer or m-v group mixed crystal semiconductor crystal layer is grown on a thin Si layer.

[For production]

The constituent requirements of the present invention are (A) that the substrate has a thermal expansion coefficient comparable to that of the upper III-V compound semiconductor layer (including mixed crystals); (B) that an intervening insulating film (glass layer) is the top m
- It has a softening point below the growth temperature Tg of the V group compound semiconductor, and the thickness of the (C) Si layer is 1/m or n (μm) of the upper m-V group compound semiconductor layer, No. 3
It is a point. Here, the numerical values of m and n are determined for the following reasons. That is, the substrate, the adhesive insulating film, and the S
To prepare a desired semiconductor substrate consisting of an i-layer and an m-v group compound semiconductor layer, for example, considering the thermal stress generated in the upper m-v group compound semiconductor layer when the temperature is lowered to room temperature (growth temperature: 600°C), For example, by decreasing the temperature, Ga
Thermal stress σ generated in As. 1. is Asum Esum+ AGIIAIEcansEiiaA*
(α, i-αGmAm) ΔT34 h (2). Here, A 3i+ AGaAs is St and Ga
Thickness of As layer, α, 1. α. □ is the thermal expansion coefficient of Si and GaAs, E Si layer EGmAs is Si and GaA
The elastic constant of s and ΔT are the temperature difference between the growth temperature Tg and the room temperature T.

AGaAs=5μm, σG, A3-5×1O1l
With a stress of dyn/cm'', if defects do not occur in GaAs, the thickness of Asi'' should be 0.8 μm. In this calculation, Ga As / Si
It is assumed that there is no warping because it is bonded to the substrate. In reality, it is not clear to what extent a stress of 5X10"dyn/cm" can suppress the occurrence of defects, but for normal G and aAs/Si, it is 1 to 2X109 dyn/cm"
stress has been measured.

Further, at around room temperature, even if stress is applied, defects will not occur. For the above reasons, the value of A and si is 2 μm.
It is desirable to set the following.

In the case of InP, a similar calculation yields 3.7 μm. This difference is due to the thermal expansion coefficient of InP S compared to GaAs.
This is because it is close to i. Therefore, SiN
The thickness of the film may be thicker.

If the m-v crystal such as GaAs is thicker than the above (5 .mu.m), the thickness of the Si may also be thicker according to equation (2), but in practice this is not preferable because cracks will occur in the Si. Therefore, it is desirable to set the thickness Asi of the Si layer to 175 or less of the thickness of the upper ■-V group compound semiconductor layer (including mixed crystal), or 2 μm or less. . Similarly, especially in the case of InP, these numbers are less than 1/2 thick or 3 μm thick.
It is desirable to set the thickness as follows.

Constituent elements (A), (B), (C) of the present invention described above
) or a combination thereof, a desired semiconductor substrate can be constructed, and a high quality m-v group compound semiconductor layer with reduced thermal stress can be obtained.

〔Example〕

FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor substrate as an embodiment of the present invention. 1 is Si, quartz.

The substrate 2, such as sapphire, is an insulating film, and may be an insulating layer made of BPSG glass, low melting point glass, or other materials such as SiN. 3 is an adhesive S having a (100) plane orientation.
This is a Si layer made by thinning the S substrate, and 4 is the desired GaAs layer.
, GaP, InP, or other m-v group compound semiconductor single crystal layer.

Examples according to the present invention will be described in detail as Examples 1 to 7 with reference to FIG.

(Example 1) For example, as a substrate, a Si substrate (4 inches, thermal expansion coefficient 2
．． 5X10-'℃-') Insulating film 2 on 1 and Te3 i
o2. After laminating BPSG glass (softening temperature approximately 350°C) consisting of Bz Oa + pg 03 by plasma CVD method, S having a (100) plane orientation is layered on top of this by the plasma CVD method.
The i-substrates were stacked and heated to about 700'C to bond the Si substrate 1 and the 81-substrate having the (100) plane via BPSG glass. Then, S having the (100) plane
The i-substrate was etched to a thickness of about 1 μm,
A Si layer 3 was produced. The Si substrate produced in this way is set in an MOCVD apparatus, and a so-called two-step growth method (consisting of low-temperature growth at about 400°C and high-temperature growth at about 700'C) is used to grow, for example, an m-v group compound semiconductor monolayer. A GaAs film 4 was grown to a thickness of about 5 μm as a crystal layer. FIG. 1 shows a schematic cross-sectional structural diagram of a semiconductor substrate manufactured in this manner.

The stress in the GaAs film 4 obtained in this way is estimated to be a tensile stress of 8 x 10" d y n70 m" based on the amount of shift of the peak wavelength of the photonsense, and compared to the conventional GaAs/Si ( Tensile stress approximately 2X1
0"dyn/cm"). In conventional GaAs/Si, the stress resulting from the difference in thermal expansion coefficients between GaAs and Si is due to the temperature difference between the growth temperature and room temperature. On the other hand, in the case of Example 1 according to the present invention, it is thought that this is because the BPSG glass relaxes the thermal stress up to the softening temperature of the BPSG glass, and only the thermal stress below the softening temperature is present in the GaAs film 4.

Etch pit density (EPD) was estimated to be about 1.times.10'cm-'' from etching with molten KOH, and the film quality was significantly improved compared to GaAs films on Si substrates that have been obtained so far.

In Example 1, an example of CaAs was described as the m-v group compound semiconductor single crystal layer, but a similar formation method can be used when growing a GaP film as another compound semiconductor, and the resulting semiconductor Similarly, excellent values were obtained for the quality characteristics of the substrate.

(Example 2) For example, as a substrate, a quartz substrate (thickness: 300 μm) is used.

After laminating BPSG glass 2 on a thermal expansion coefficient of 0.6×10−”℃−′)1 by plasma CVD method, a Si substrate having a (100) plane orientation is layered on top of the BPSG glass 2.
The quartz substrate 1 and the Si substrate having the (100) plane were bonded together by heating to 0°C. Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to form a Si layer 3. The Si layer 3 on the quartz substrate 1 prepared in this way is set in an MOCVD apparatus,
The so-called two-step growth method (low-temperature growth at about 400℃ and growth at about 70℃)
For example, a GaAs film 4 was grown to a thickness of about 5 μm as an m-v group compound semiconductor single crystal layer by high-temperature growth at 0° C.).

The stress in the GaAs film 4 thus obtained as an example was estimated to be a tensile stress of 2×10'dyn/am" from the shift amount of the peak wavelength of photoluminescence.・Pit density (EPD) is approximately I x 10'Cm-"
It is estimated that the Ga on Si substrate obtained so far is
A marked improvement in film quality was observed compared to the As film. Example 2
The thermal stress in GaAs in is caused by the difference in thermal expansion coefficient between the quartz substrate l, which accounts for the thickness of most substrates, and the GaAs film 4. The substrate is Si (thermal expansion coefficient approximately 2
．． Compared to Example 1, which uses GaAs (thermal expansion coefficient of about 6°C-1), in Example 2 GaAs (thermal expansion coefficient of about 6°C-1) is used.
The substrate uses quartz (thermal expansion coefficient approximately 0.6 x 10-6℃-I), which has a large difference in thermal expansion coefficient from that of BPSG glass (approximately 350℃). It is thought that the thermal stress increases due to the temperature difference between room temperatures.However, the GaAs layer
In the following, stress-induced dislocations are not introduced below this stress, so the dislocation density in GaAs is small as in Example 1.

In Example 2, an example of GaAs was described as the m-v group compound semiconductor single crystal layer, but a similar formation method can be used when growing a GaP film as another compound semiconductor, and the resulting semiconductor Similarly, excellent values were obtained for the quality characteristics of the substrate.

(Example 3) For example, as a substrate, a sapphire substrate (thermal expansion coefficient 6.5
After laminating the BPSG glass 2 on the X10-''°C-I)l by plasma CVD method, a Si substrate having a (100) plane orientation is placed on top of the BPSG glass 2, and heated to about 700°C to form the sapphire substrate. 1 and Si having the (100) plane
The board was glued.

Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to produce SiN3. S on the sapphire substrate 1 produced in this way
The i-layer 3 was set in an MBE apparatus, and a GaAs film 4 of about 5 μm was grown by a so-called two-step growth method (consisting of low-temperature growth at about 400° C. and high-temperature growth at about 650° C.). As for the stress in the GaAs film 4 obtained in this way, no shift amount of the peak wavelength of photoluminescence was detected, and the stress was 107
It was estimated to be less than dyn/cm".

The stress in the conventional GaAs film 4 is GaAs/S
It can be seen that it has decreased slightly compared to i. Melting KO
From etching with H, the etch bit density (E
PD) was estimated to be approximately 1×10'Cm-''. BP
GaAs film 4 by using SG film as adhesive layer
The reduction in dislocation density in the sample is about the same as in Examples 1 and 2. Furthermore, in Example 3 in which the substrate was sapphire, which has a coefficient of thermal expansion almost equal to that of GaAs, stress in the GaAs film was also reduced.

In this Example 3, an example of GaAs was described as the m-v group compound semiconductor single crystal layer, but the same forming force method can be used when growing a GaP film as other compound semiconductors, and the obtained Similarly, excellent values were obtained for the quality characteristics of the semiconductor substrate.

(Example 4) As a substrate, a Si substrate (4 inches, thermal expansion coefficient 2.5X
10-'C-') S i O2 on 1, B20. , P
After laminating a low melting point glass 2 (softening temperature 350'c) made of BO (softening temperature 350'c) by plasma CVD method,
) Si substrates having a plane orientation of the (100) plane were stacked and heated to about 700° C. to bond the Si substrate 1 and the Si substrate having the (100) plane. Then, the Si having the (100) plane
The substrate was etched to a thickness of approximately 1 μm, and S
An i-layer 3 was formed. The SiiN3 on the Si substrate 1 prepared in this way was set in an MOCVD apparatus, and a Ga, As film was grown by the so-called two-step growth method (consisting of low-temperature growth at about 400°C and high-temperature growth at about 7°0°C). 4 was grown to about 5 μm.

The stress in the GaAs film 4 obtained in this way is 8X10@d based on the shift amount of the peak wavelength of photoluminescence.
Etch pit density (E P
D) was estimated to be about 1×10'cm-'', and the same improvement in film quality as in Example 1 was observed.

In Example 4, an example of GaAs was described as the m-v group compound semiconductor single crystal layer, but a similar formation method can be used when growing a GaP film as other compound semiconductors, and the resulting semiconductor Similarly, excellent values were obtained for the quality characteristics of the substrate.

(Example 5) For example, as a substrate, a Si substrate (4 inches, thermal expansion coefficient 2
．． 5X10"C-1) SiO,,B on 1).

BPSG glass consisting of Os, PzOs (softening temperature 35
0℃) by the plasma CVD method, and then a Si substrate with a (100) plane orientation is placed on top of this, and a
The Si substrate 1 and the Si substrate having the (100) plane were bonded to each other via BPSG glass by heating to 0°C. Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to form a Si layer 3. The Si substrate produced in this way was set in an MOCVD apparatus, and InPn was grown using the so-called two-step growth method (consisting of low-temperature growth at about 400't and high-temperature growth at about 700°C).
A layer film of about 5 μm was grown. FIG. 1 shows the structure of a semiconductor substrate manufactured in this manner.

The stress in the InP film 4 obtained in this way is 2X10" d from the shift amount of the peak wavelength of photoluminescence.
The tensile stress is estimated to be yn/cm”, and the conventional InP
/St (tensile stress approximately 1×10'dyn/cm")
It can be seen that it has decreased compared to . Conventional InP/Si
In this case, the stress resulting from the difference in expansion coefficients between InP and SiOi is due to the temperature difference between the growth temperature and room temperature. On the other hand, in the case of Example 5 according to the present invention, BPSG relaxes the thermal stress up to the softening temperature of BPSG, and it is thought that this is because only the thermal stress below the softening temperature exists in the InP film 4. From processing with O4+HBr, the etch pit density (EPD) is approximately I
It was estimated to be 10'cm-'', and the film quality was significantly improved compared to the InP films on Si-based substrates obtained so far.

(Example 6) As a substrate, an alumina single crystal substrate (thermal expansion coefficient 4.6X
10-'℃-1) Plasma CV of BPSG glass on 1
After laminating by the D method, a Si substrate with a (100) plane orientation is placed on top of this and heated to about 700°C to form an aluminum ξ
The single crystal substrate 1 and the Si substrate having the (100) plane were bonded together. Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching, and the
Layer 3 was created. 5iii3 on the alumina single crystal substrate l prepared in this way was set in the MOMBE equipment, and an InP film was grown using the so-called two-step growth method (consisting of low-temperature growth at about 350"C and high-temperature growth at about 550"C). Approximately 5μ
mtc lengthened. The stress in the InP film 4 obtained in this manner was estimated to be less than 10'dyn/cm'', with no shift in the peak wavelength of either the photons or the neissances detected. In comparison, it can be seen that the stress in the InP film 4 is greatly reduced.Hz P Oa
From + HBr etching, the etch pit density (EPD) was estimated to be approximately 1 x 10'cm-''.

The reduction in the dislocation density of the InP film through BPSG is about the same as in Example 5. Furthermore, in Example 6 according to the present invention in which the substrate was a single crystal of aluminum having a coefficient of thermal expansion almost equal to that of InP, stress in the InP film was also reduced.

(Example 7) For example, as a substrate, a quartz substrate (4 inches, thermal expansion coefficient 2
．． 5xlO-'°C-1) on 5i02. B2o:+,
After laminating a low melting point glass made of PBO (softening temperature 350°C) by plasma CVD method, (100)
The Si substrates having the plane orientation were stacked and heated to about 700° C. to bond the quartz substrate 1 and the Si substrate having the (100) plane. Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching, and the Si substrate was etched to a thickness of about 1 μm.
Layer 3 was formed. The Si layer 3 on the quartz substrate l prepared in this manner is set in an MOCVD apparatus, and an InP film 4 is grown by a so-called two-step growth method (consisting of low-temperature growth at about 350°C and high-temperature growth at about 600°C). It grew to about 5 μm.

FIG. 1 shows the structure of a semiconductor substrate manufactured in this manner.

The stress in the InP film 4 obtained in this way is 4X10" d from the shift amount of the peak wavelength of photoluminescence.
The tensile stress is estimated to be yn/cm”, Hs P O
Etch pit density (EPD) was estimated to be about 1 x 105 cm-'' from etching with s+HBr, and the same improvement in film quality as in Example 5 was observed.

In addition to Examples 1 to 7, ceramic vine substrates, metal substrates, glass substrates, and semiconductor substrates other than Si such as Ge were used, and similar excellent results were obtained.

Furthermore, in Examples 1 to 7 of the present invention, B was used as an insulating film for adhesion.
Although PSG glass or low melting point glass has been described as an example, other general insulating films may be used, such as a silicon nitride film.

FIG. 2 is a schematic cross-sectional structural diagram of a semiconductor substrate according to another embodiment of the present invention. That is, 1 is a substrate made of 3i, quartz, sapphire, etc., and 2 is an insulating film, which may be an insulating layer made of BPSG glass, low melting point glass, or another SiN film. 3 is an St layer formed by thinning an adhesive Si substrate with a (100) plane orientation, and 5 is a desired GaAs, GaP, InP layer.
AlGaAs, Ga, I nl-Xp as a mixed crystal such as
, GaPxAs+-x, or the like.

Still other embodiments of the present invention will be described as Examples 8 to 11 with reference to FIG.

(Example 8) For example, as a substrate, a Si substrate (4 inches, thermal expansion coefficient 2
．． 5xlO-'℃-') 3i0z, Bi12, P on 1
BPSG glass 2 consisting of tO (softening temperature approximately 350°C
) was laminated by plasma CVD method, and then (1
00) plane orientation and heated to approximately 700°C.
The Si substrate 1 and the Si having the (100) plane are heated to
The substrate was bonded via BPSG glass 2. after that,
The Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to form the St layer 3.

The Si substrate produced in this way was set in an MOCVD apparatus, and QaxI
An nk-XP (X=0.5) film 5 was grown to a thickness of about 5 μm.

FIG. 2 shows a schematic cross-sectional structural diagram of a semiconductor substrate manufactured in this manner.

The stress in the Ga, In, -XP film 5 obtained in this way is calculated by 8 from the shift amount of the peak wavelength of photoluminescence.
The tensile stress of the conventional GaX ln, -8P/Si (tensile stress of about 2
It can be seen that this decreases compared to X10"dyn/cm"). In conventional Ga, In+-xP/Si, the stress generated from the difference in thermal expansion coefficient between Qa, t I n+-x P and StO is due to the temperature difference between the growth temperature and room temperature. On the other hand, in the case of Example 8 according to the present invention, BPSG2 relaxes the thermal stress up to the softening temperature of BPSG, and only the thermal stress below the softening temperature is QaX r
This is considered to be because it is in the nl-, P film 5. molten KOH
Etch bit density (EP)
D) was estimated to be approximately 1×10'cm-'', and a marked improvement in film quality was observed compared to the QaX I nl-XP film on the Si substrate that had been obtained up to this point.

In Example 8, QaX is used as the m-v group mixed crystal semiconductor.
Although the example of I n+-x P has been described, a similar formation method can be used to grow AJGaAs, GaP, and ASI-31 films as other mixed crystal systems, and the quality characteristics of the obtained semiconductor substrate Similarly, excellent values were obtained.

(Example 9) For example, as a substrate, a quartz substrate (thickness: 300 μm) is used.

After laminating BPSG glass 2 on a thermal expansion coefficient of 0.6
The quartz substrate I and the Si substrate having the (100) plane were bonded together by heating to 00°C.

Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to form a Si layer 3. The 5i substrate on the quartz substrate 1 prepared in this way is
It is set in the OCVD equipment and used in the so-called two-step growth method (
GaX1n r-XP (X = 0-5
) Film 5 was grown to a thickness of about 5 um.

Gax I nI-x P film 5 obtained in this way
The stress inside was estimated to be a tensile stress of 2xlQ'dyn/cm'' from the amount of shift in the peak wavelength of photoluminescence. From dislocation observation using a cross-sectional electron microscope (TEM), the dislocation density was approximately I x 10' cm- ”, and the GaxIn, X
A remarkable improvement in film quality was observed compared to the p-film. Example 9
The thermal stress in QaXln+-xP at quartz substrate l and QaXInI-x
This is caused by a difference in thermal expansion coefficient from the P film 5. Compared to Example 8, in which Si (thermal expansion coefficient of approximately 2.5×10-'°C-') was used as the substrate, in this Example 9, Ga substrate was used.
n1-+1P (thermal expansion coefficient approximately 6.4X10-'℃-1)
Substrate quartz with a large difference in thermal expansion coefficient (thermal expansion coefficient of about 0.
6XIO-'°C-1) is used. Therefore, BPS
It is thought that the thermal stress due to the temperature difference between the softening point of the G film (approximately 350° C.) and room temperature is increased.

However, the temperature of about 400°C for GaX I J-, P film is
In the following, since stress-induced dislocations are not introduced below this stress, GaXI n
The dislocation density in l-XP is small.

In this Example 9, Ga is used as the m-v group mixed crystal semiconductor.
Although the example of Inl-xP has been described, a similar formation method can be used to grow AllGaAs, GaP, and A31-X films as other mixed crystal systems, and the quality characteristics of the obtained semiconductor substrate Similarly, excellent values were obtained.

(Example 10) For example, as a substrate, a sapphire substrate (thermal expansion coefficient 6.5
After laminating a BPSG glass 2 on X10-'°C-1) 1 by plasma CVD, a Si substrate having a (100) plane orientation is placed thereon and heated to about 700°C to form the sapphire substrate l. and the Si substrate having the (100) plane were bonded together.

Thereafter, the 31 substrate having the (100) plane was thinned to a thickness of about 1 μm by etching to form the Si layer 3. The St layer 3 on the sapphire substrate 1 prepared in this way was set in an MBE apparatus, and GaX1n1-, p Film 5 was grown to a thickness of about 5 μm. caz 1 nl-X Pli obtained in this way
No shift in the peak wavelength of photoluminescence was detected, and the stress in 5 was estimated to be less than 10'dyn/cm''. , 1 nl-x It can be seen that the stress in the P film 5 is slightly reduced. From the results of observing the dislocation density by TEM, the dislocation 1-position density was estimated to be about I x 10'cm-''. The reduction in dislocation density of this G az I n I-MP film is about the same as in Examples 8 and 9. Furthermore, in Example 10, in which the substrate was sapphire, which has a coefficient of thermal expansion almost equal to that of Ga, l I nl-, P, the stress in the Ga-In, P film was also reduced.

In Example 10, Ga is used as the m-v group mixed crystal semiconductor.
, lnl-, and P, but a similar formation method can be used to grow films of other mixed crystal systems such as AjlGaAs and GaPgASt-, and the quality of the obtained semiconductor substrate can be improved. The characteristics are also excellent (direction has been obtained).

(Example 11) As a substrate, a Si substrate (4 inches, thermal expansion coefficient 2.5
10-'℃-1) S i O2,B, O,,p on 1
After laminating low melting point glass 2 made of bO (softening temperature 350'C) by plasma CVD method, (100)
The Si substrates having the plane orientation were stacked and heated to about 700° C. to bond the Si substrate having the (100) plane onto the Si base substrate. Thereafter, the Si substrate having the (100) plane was thinned to a thickness of about 1 μm by etching, and St.
Layer 3 was formed. The Si substrate prepared in this way was set in an MOCVD apparatus, and the so-called two-step growth method (consisting of low/MLrli and long growth of about 400°C and high temperature growth of about 700°C) was performed. GaX I nl
-Xp film 5 was grown to a thickness of about 5 μm.

The stress in the Ga-In,-XP film obtained in this way is estimated to be a tensile stress of 8 x 10"dyn/cm" from the shift amount of the peak wavelength of photoluminescence, and from the dislocation density observation by TEM. , the dislocation density is about I
X 10'cm-'', and the same improvement in film quality as in Example 8 was observed.

In Example 11, Ga is used as the m-v group mixed crystal semiconductor.
Although the example of XIn1-xP has been described, a similar formation method can be used to grow an AlGaAs layer as another mixed crystal system, and the quality characteristics of the obtained semiconductor substrate are also excellent. value is obtained.

In addition to Examples 8 to 11, ceramic substrates, metal substrates,
Similar results were obtained using a glass substrate or a semiconductor substrate other than Si such as Ge.

In addition, different compositions of GaX In, -xP (x = 0°0
Similar results were obtained for other ternary mixed crystals such as AlG
Similar results were obtained for the composition of the aAs layer, such as Ga1nPAs.

The embodiments according to the present invention are described below. That is, the present invention provides an m-v group compound semiconductor single crystal layer or an m-v group mixed crystal semiconductor layer grown on Si.
An insulating film having a softening point at a temperature below the growth temperature of the V group semiconductor single crystal layer or the V group mixed crystal semiconductor layer is laminated, a Si substrate is further laminated on the insulating film, and a Si substrate is laminated on the Si substrate. A semiconductor substrate characterized by a structure in which an m-v group compound semiconductor single crystal layer or an m-v group mixed crystal semiconductor layer is grown, or characterized in that the softening point of the insulating film is 400°C or less or a semiconductor substrate having a thickness of 115 or less than the thickness of the ■-■ group compound semiconductor single crystal layer or m-v group mixed crystal semiconductor layer to be laminated, or a thickness of 2 μm or less as the Si substrate. The semiconductor substrate may be characterized by using a Si substrate, and more specifically, the m-v group compound semiconductor single crystal layer may be any one of GaAs1i, GaP layer, and InP layer. Alternatively, the m-v group compound semiconductor single crystal layer may be GaA.
The semiconductor substrate may be either an S layer or a GaP layer, and more specifically, the m-v
A semiconductor substrate characterized in that the group compound semiconductor single crystal is an InP layer, and the Si substrate has a thickness of 1/2 or less of the thickness of the InP layer or 3 μm or less. Alternatively, the m-v group mixed crystal semiconductor layer may be any one of an AlGaAs layer, a GalnP layer, a ternary mixed crystal of a GaPAs layer, or a quaternary mixed crystal of Ga1nPAsli.
The present invention relates to a semiconductor substrate characterized in that it is formed by:

〔Effect of the invention〕

According to the present invention, the stress caused by the difference in thermal expansion coefficient is absorbed by the glass having a low softening temperature, so that heat is absorbed in the m-v group compound semiconductor single crystal layer or the m-v group mixed crystal semiconductor crystal layer. A high quality m-v group compound semiconductor single crystal layer or m-v group mixed crystal compound semiconductor layer free of defects such as dislocations caused by stress can be obtained.

In addition, since glass, metal, ceramics, single crystal substrates, etc. can be used as the substrate, it is possible to use an inexpensive, large-area semiconductor substrate containing an m-v group compound semiconductor single crystal layer or an m-v group mixed crystal semiconductor substrate. Its effects are significant, such as the ability to obtain

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional structural diagram of a semiconductor substrate as an embodiment of the present invention. FIG. 2 is a schematic cross-sectional structural diagram of another semiconductor substrate as an example according to the present invention. 1... Substrate (St, sapphire, quartz, etc.) 2... Insulating film/glass layer/BPSG film 3... St layer ←... m-v group compound semiconductor single crystal layer 5... m-v group mixed crystal compound semiconductor layer

Claims (7)

[Claims] (1) In a III-V group compound semiconductor single crystal layer or a III-V group mixed crystal semiconductor layer grown on Si, on the substrate,
An insulating film having a softening point at a temperature lower than the growth temperature of the III-V group compound semiconductor single crystal layer or the III-V group mixed crystal semiconductor layer is laminated, a Si substrate is laminated on the insulating film, and the Si substrate is laminated on the insulating film. A semiconductor substrate characterized by a structure in which a III-V group compound semiconductor single crystal layer or a III-V group mixed crystal semiconductor layer is grown on the substrate. (2) The semiconductor substrate according to claim 1, wherein the insulating film has a softening point of 400° C. or lower. (3) The Si substrate has a thickness of 1/5 or less of the thickness of the III-V group compound semiconductor single crystal layer or the III-V group mixed crystal semiconductor layer to be laminated, or a thickness of 2 μm or less. The semiconductor substrate according to any one of claims 1 and 2, characterized in that: (4) The III-V compound semiconductor single crystal layer is made of GaAs.
3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is one of a layer, a GaP layer, and an InP layer. (5) The III-V compound semiconductor single crystal layer is made of GaAs.
4. The semiconductor substrate according to claim 3, wherein the semiconductor substrate is either a GaP layer or a GaP layer. (6) The III-V compound semiconductor single crystal layer is an InP layer, and the Si substrate is a Si substrate having a thickness of 1/2 or less of the thickness of the InP layer or 3 μm or less. The semiconductor substrate according to claim 1 or claim 2, characterized in that: (7) The III-V group mixed crystal semiconductor layer is formed of an AlGaAs layer, a GaInP layer, a ternary mixed crystal of a GaPAs layer, or a quaternary mixed crystal of a GaInPAs layer. Claims 1 to 3 are characterized in that:
The semiconductor substrate according to any one of the following.