JPH01230255A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH01230255A
JPH01230255A JP5700588A JP5700588A JPH01230255A JP H01230255 A JPH01230255 A JP H01230255A JP 5700588 A JP5700588 A JP 5700588A JP 5700588 A JP5700588 A JP 5700588A JP H01230255 A JPH01230255 A JP H01230255A
Authority
JP
Japan
Prior art keywords
layer
substrates
semiconductor
layers
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5700588A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP5700588A priority Critical patent/JPH01230255A/en
Publication of JPH01230255A publication Critical patent/JPH01230255A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make bubbles hard to remain in bonding surfaces and to reduce stress, by using a semiconductor layer in a fused state to bond two semiconductor substrates. CONSTITUTION:Two sheets of Si substrates 11 and 12 are prepared. The substrates 11 and 12 have SiO2/Si structures having SiO2 layers on the surfaces. A polycrystalline Si layer 15 having a thickness of about 10-50Angstrom are formed on the layer 13 of the substrate 11. Then, the sides of the layers 13 and 14 are made to face each other, and the substrates 11 and 12 are brought into contact together. The layers 13 and 14 are selectively heated. Since the layer 15 is very thin, only the layer 15 is fused when the layers 13 and 14 are selectively heated. Thereafter the heating is stopped. Then, the layer 15 is solidified, and the substrates 11 and 12 are bonded together. Since the layer 15 is fused, remaining bubbles in the bonding surfaces of the substrates 11 and 12 are very few, and stress is also less.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、内部にwA縁層を宵する半導体基板の製造方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor substrate having a WA edge layer therein.

〔発明の概要〕[Summary of the invention]

本発明は、上記の様な半導体基板の製造方法において、
夫々の表面に絶縁層を有する第1及び第2の半導体基板
を溶融状態の半導体層を用いて接着することによって、
高品質の半導体基板を製造することができる様にしたも
のである。
The present invention provides a method for manufacturing a semiconductor substrate as described above.
By bonding first and second semiconductor substrates having insulating layers on their respective surfaces using a molten semiconductor layer,
This makes it possible to manufacture high quality semiconductor substrates.

〔従来の技術〕[Conventional technology]

SOI基板は、LSI作成時に大きな利点を有するのみ
ならず、電気的性質においても優れていることがよく知
られている。
It is well known that SOI substrates not only have great advantages when producing LSIs, but also have excellent electrical properties.

そして、この様なSOI基板を実現するものとして、結
晶性が良い等の理由から、張り合わせ基板が現在のとこ
ろ有望視されている。
At present, a bonded substrate is considered to be a promising material for realizing such an SOI substrate due to its good crystallinity.

即ち、特開昭60−121776号公報や^ppl。That is, JP-A-60-121776 and ^ppl.

Phys−Lett、+Vo1.4B+N11+6 J
anuary 1986 PP78〜80等に記載され
ている様に、Sing/Si構造の2枚の基板の5iO
1面同士を接触させ、熱圧着や静電圧着等を行えば、2
枚の基板は完全に1枚の基板となる。
Phys-Lett, +Vo1.4B+N11+6 J
5iO of two substrates with Sing/Si structure, as described in 1986 PP78-80 etc.
If one side is brought into contact with another and thermocompression bonding or electrostatic bonding is performed, two
The two substrates become one complete substrate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしこの様な方法では、微細な気泡が接着面に残存す
るのを防止できず、応力も比較的大きい。
However, with this method, it is not possible to prevent fine air bubbles from remaining on the adhesive surface, and the stress is relatively large.

従って、この様な方法で製造されたSol基板の品質は
、必ずしも高くない。
Therefore, the quality of the Sol substrate manufactured by such a method is not necessarily high.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体基板の製造方法は、夫々の表面に絶
縁層13.14を有する第1及び第2の半導体基板11
.12を準備する工程と、溶融状態の半導体層15を介
して前記絶縁層13.14同士を対向させる工程と、前
記熔融状態の半導体N15を固化させて前記第1及び第
2の半導体基板11.12同士を接着させる工程とを夫
々具備している。
The method for manufacturing a semiconductor substrate according to the present invention includes first and second semiconductor substrates 11 having insulating layers 13 and 14 on their respective surfaces.
.. 12, a step of making the insulating layers 13 and 14 face each other via the molten semiconductor layer 15, and solidifying the molten semiconductor N15 to form the first and second semiconductor substrates 11. 12 to each other.

(作用) 本発明による半導体基板の製造方法では、溶融状態の半
導体層15を用いて第1及び第2の半導体基板11.1
2同士を接着させているので、接着面に気泡が残存しに
くく且つ応力も少ない。
(Function) In the method for manufacturing a semiconductor substrate according to the present invention, the semiconductor layer 15 in a molten state is used to form the first and second semiconductor substrates 11.1.
Since the two are bonded together, air bubbles are unlikely to remain on the bonded surface and stress is also low.

〔実施例〕〔Example〕

以下、本発明の第1及び第2実施例を、第1図を参照し
ながら説明する。
Hereinafter, first and second embodiments of the present invention will be described with reference to FIG.

第1実施例では、第1A図に示す様な2枚のSi基板1
1.12をまず準備する。これらのSi基板11.12
は、表面にSiO□N13.14を有する5iOt/S
t構造であり、更にSi基板11のSin、層13上に
は、10〜50人程度の熱酸の多結晶Si層15を形成
しておく。
In the first embodiment, two Si substrates 1 as shown in FIG. 1A are used.
1. Prepare 12 first. These Si substrates 11.12
is 5iOt/S with SiO□N13.14 on the surface
Further, on the Si layer 13 of the Si substrate 11, a polycrystalline Si layer 15 of about 10 to 50 layers of thermal acid is formed.

次に、第1B図に示す様に5L(h層13.14側を対
向させてSi基板11.12同士を接触させ、ラピッド
サーマルアニール処理やCO□レーザ等で5int層1
3.14を選択的に加熱する。
Next, as shown in FIG. 1B, the Si substrates 11 and 12 are brought into contact with each other with the 5L (h layers 13 and 14 sides facing each other), and the 5int layer 1 is
3.Selectively heat 14.

ところで多結晶Si層15は、上述の様に非常に薄いの
で、CVDで成長させても粒径が小さく、且つ熱の放散
率も低い、また、SingよりもSiの方が融点が低い
。これらのために、SiO□層13.14を選択的に加
熱すると、sto、Jl 13.14に挾持されている
多結晶Si層15のみが溶融する。
By the way, since the polycrystalline Si layer 15 is very thin as described above, the grain size is small even when grown by CVD, and the heat dissipation rate is also low. Also, Si has a lower melting point than Sing. For these reasons, when the SiO□ layer 13.14 is selectively heated, only the polycrystalline Si layer 15 sandwiched between the sto and Jl 13.14 is melted.

その後、加熱を停止すると、多結晶Si層15が固化し
て、Si基板11.12同士が接着する。
Thereafter, when the heating is stopped, the polycrystalline Si layer 15 is solidified and the Si substrates 11 and 12 are bonded to each other.

従って、この状態からSi基板12を研削したりして薄
膜状のSi層を形成すれば、第1B図の様なSOI基板
が得られる。
Therefore, by grinding the Si substrate 12 from this state to form a thin Si layer, an SOI substrate as shown in FIG. 1B can be obtained.

この様な第1実施例では、多結晶Si層15は粒径が小
さいために元々表面が平坦であり、しかもこの多結晶S
i層15は溶融するので、多結晶Si層15の固化後に
Si基板11.12同士の接着面に残存している気泡は
非常に少なく、且つ応力も少ない。
In the first embodiment, the polycrystalline Si layer 15 originally has a flat surface because of its small grain size.
Since the i-layer 15 is melted, there are very few bubbles remaining on the bonding surfaces of the Si substrates 11 and 12 after solidification of the polycrystalline Si layer 15, and there is also little stress.

また、多結晶5ill 15が非常に薄いので、隣接素
子へ電位が伝わりにクク、多結晶Si層15の存在を実
質的には無視することができる。なお、隣接素子への電
位の伝わりを更に少なくするには、sto、m 13よ
りもSin、層14を厚くすればよい。
Furthermore, since the polycrystalline Si layer 15 is very thin, the potential is transmitted to adjacent elements, and the presence of the polycrystalline Si layer 15 can be virtually ignored. Note that in order to further reduce the transmission of potential to adjacent elements, it is sufficient to make the Sin layer 14 thicker than the sto, m 13.

次に、第2実施例を説明する。この第2実施例は、第1
実施例における多結晶5ijii15の代りに非晶質s
tJ!iを用いることを除いて、第1実施例と実質的に
同様の工程を有している。
Next, a second embodiment will be explained. This second embodiment is based on the first
Amorphous s instead of polycrystalline 5ijii15 in the example
tJ! This embodiment has substantially the same steps as the first embodiment except that i is used.

非晶¥isi層は、SiH*を分解するプラズマCVD
や、580℃以下の温度でSiH*を分解するLP−C
VDや、LP−CVDで多結晶Si層を成長させた後に
イオン注入で非晶質化する方法や、非晶質Siを蒸着さ
せる蒸着法等によって形成することができる。
The amorphous isi layer is formed by plasma CVD that decomposes SiH*.
LP-C that decomposes SiH* at temperatures below 580℃
It can be formed by a method in which a polycrystalline Si layer is grown by VD or LP-CVD and then made amorphous by ion implantation, or by a vapor deposition method in which amorphous Si is vapor-deposited.

非晶質Siは、熱を急激に加えると、エネルギ量自体が
少なくても、つまり低融点で、溶融する。
Amorphous Si melts when heat is rapidly applied, even if the amount of energy itself is small, that is, at a low melting point.

従って、Si基板11.12同士の接着に好都合である
Therefore, it is convenient for bonding the Si substrates 11 and 12 together.

〔発明の効果〕〔Effect of the invention〕

本発明による半導体基板の製造方法では、第1及び第2
の半導体基板同士の接着面に気泡が残存しにくく且つ応
力も少ないので、高品質の半導体基板を製造することが
できる。
In the method for manufacturing a semiconductor substrate according to the present invention, the first and second
Since air bubbles are less likely to remain on the bonding surfaces of the semiconductor substrates and there is less stress, high quality semiconductor substrates can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例の工程を順次に示す側断面
図である。 なお図面に用いた符号において、 11.12・−−−−−・−−−−5i基板13、14
−−−−−−−−−−−5 io t J!115−・
・・−・−・−−−−−一−・−多結晶St層である。
FIG. 1 is a side sectional view sequentially showing the steps of a first embodiment of the present invention. In addition, in the symbols used in the drawings, 11.12・------・---5i substrates 13, 14
−−−−−−−−−−5 io t J! 115-・
...-----------Polycrystalline St layer.

Claims (1)

【特許請求の範囲】  内部に絶縁層を有する半導体基板の製造方法において
、 夫々の表面に絶縁層を有する第1及び第2の半導体基板
を準備する工程と、 溶融状態の半導体層を介して前記絶縁層同士を対向させ
る工程と、 前記溶融状態の半導体層を固化させて前記第1及び第2
の半導体基板同士を接着させる工程とを夫々具備するこ
とを特徴とする半導体基板の製造方法。
[Claims] A method for manufacturing a semiconductor substrate having an insulating layer therein, comprising the steps of: preparing first and second semiconductor substrates having insulating layers on their respective surfaces; a step of making the insulating layers face each other; and solidifying the molten semiconductor layer to form the first and second semiconductor layers.
A method for manufacturing a semiconductor substrate, comprising the steps of: adhering semiconductor substrates to each other.
JP5700588A 1988-03-10 1988-03-10 Manufacture of semiconductor substrate Pending JPH01230255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5700588A JPH01230255A (en) 1988-03-10 1988-03-10 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5700588A JPH01230255A (en) 1988-03-10 1988-03-10 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH01230255A true JPH01230255A (en) 1989-09-13

Family

ID=13043346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5700588A Pending JPH01230255A (en) 1988-03-10 1988-03-10 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH01230255A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5755914A (en) * 1992-08-25 1998-05-26 Canon Kabushiki Kaisha Method for bonding semiconductor substrates
JP2006066928A (en) * 1994-09-09 2006-03-09 Renesas Technology Corp Method of manufacturing semiconductor device
WO2022176701A1 (en) * 2021-02-19 2022-08-25 信越化学工業株式会社 Composite wafer and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5755914A (en) * 1992-08-25 1998-05-26 Canon Kabushiki Kaisha Method for bonding semiconductor substrates
JP2006066928A (en) * 1994-09-09 2006-03-09 Renesas Technology Corp Method of manufacturing semiconductor device
WO2022176701A1 (en) * 2021-02-19 2022-08-25 信越化学工業株式会社 Composite wafer and manufacturing method therefor

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