JPH0352250A - Manufacture of dielectric isolating substrate - Google Patents

Manufacture of dielectric isolating substrate

Info

Publication number
JPH0352250A
JPH0352250A JP18587589A JP18587589A JPH0352250A JP H0352250 A JPH0352250 A JP H0352250A JP 18587589 A JP18587589 A JP 18587589A JP 18587589 A JP18587589 A JP 18587589A JP H0352250 A JPH0352250 A JP H0352250A
Authority
JP
Japan
Prior art keywords
alloy
silicon
substrate
silicon substrate
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18587589A
Other languages
Japanese (ja)
Inventor
Hideji Ito
伊藤 秀二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP18587589A priority Critical patent/JPH0352250A/en
Publication of JPH0352250A publication Critical patent/JPH0352250A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to reduce the cost of a dielectric isolating substrate by filling recess parts in the surface of a first silicon substrate by the diffusion and solidification of alloy of silicon base material having a melting point lower than that of silicon, and bonding both silicon substrates. CONSTITUTION:As a material for bonding both silicon substrates 11 and 17, alloy 16 of silicon base material having a melting point lower than that of silicon is used. The insides of recess parts 13 in the surface of the substrate 11 are filled with the fusion and solidification of the alloy 16, and both substrates 11 and 17 are bonded. The fused liquid of the alloy 16 has a low viscosity coefficient. Therefore, the complete filling of the alloy 16 into the recess parts 13 in the surface of the substrate 11 by the fusing heat treatment of the alloy 16 can be performed even if the alloy shape before fusion is in the state of particles whose diameters are several mum or more or in the state of a thin plate. In this way, depositing steps of bonding junction layers are simplified to a large extent, and the cost of the dielectric isolating substrate can be reduced.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、半導体集積装置に用いられる誘電体分離基
板の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a dielectric isolation substrate used in a semiconductor integrated device.

(従来の技術) 従来の誘電体分離基板の製造方法における、重大な短所
である基板製造コスト高を解決する方法として、基板接
合技術を用いた誘電体分離基板の製造方法が近年提案さ
れて来ている.以下、そのような製造方法の1つである
特開昭61 − 242033号公報に開示される方法
を第4図(a)〜(2)に従い説明する. まず、第4図(a)に示すように、単結晶シリコン基板
1の表面に異方性エッチングにより凹部2を形戒後、単
結晶シリコン基板1を酸化し、四部2を含む基板表面に
、絶縁分離のための酸化膜3を形或する. 次に、第4図ら)に示すように、前記酸化膜3上にシリ
コン,硼素,酸素からなるSi−B=O超微粒子のガラ
ス質堆積層4を形威し、その上に別のシリコン基板5を
置く. 次に、第4図(c)に示すように、これに1300℃程
度の温度で熱処理を行い、前記堆積層4を焼結するとと
もに単結晶シリコン基板1とシリコン基板5を接合させ
る。
(Prior Art) In recent years, a method for manufacturing a dielectrically isolated substrate using substrate bonding technology has been proposed as a method to solve the high cost of manufacturing a substrate, which is a serious disadvantage of the conventional method for manufacturing a dielectrically isolated substrate. ing. Hereinafter, one such manufacturing method, which is disclosed in Japanese Patent Application Laid-Open No. 61-242033, will be explained with reference to FIGS. 4(a) to (2). First, as shown in FIG. 4(a), after forming a recess 2 on the surface of a single crystal silicon substrate 1 by anisotropic etching, the single crystal silicon substrate 1 is oxidized, and the substrate surface including the four parts 2 is formed. An oxide film 3 is formed for insulation isolation. Next, as shown in FIG. 4, a glassy deposited layer 4 of Si-B=O ultrafine particles made of silicon, boron, and oxygen is formed on the oxide film 3, and another silicon substrate is placed on top of it. Place 5. Next, as shown in FIG. 4(c), this is subjected to heat treatment at a temperature of about 1300° C. to sinter the deposited layer 4 and bond the single crystal silicon substrate 1 and the silicon substrate 5 together.

次に、第4図(2)に示すように、単結晶シリコン基板
1の裏面側を、凹部2の先端が露出するまで研削・研磨
によって除去することにより、誘電体分離基板が得られ
る。
Next, as shown in FIG. 4(2), the back side of the single crystal silicon substrate 1 is removed by grinding and polishing until the tips of the recesses 2 are exposed, thereby obtaining a dielectric isolation substrate.

(発明が解決しようとする課題) しかし、以上述べた方法では、両シリコン基板lと5を
接合する物質として、焼結時の粘性率が10”l)oj
se以上のガラスを用いているので、焼結により、基板
1表面の凹部2内を空隙無く堆積層4で完全に充填する
為には、粒径0.05〜0.2nのガラスの超微粒子を
基仮I上に隙間無く均一に堆積せねばならないので、堆
積工程の制御が難かしく又、堆積時間もかかると云う問
題点があった.この為、誘電体分離基板の製造コストを
下げる目的が十分には達或出来なかった。
(Problem to be Solved by the Invention) However, in the method described above, the material that joins both silicon substrates 1 and 5 has a viscosity of 10"l) oj during sintering.
Since glass of se or higher is used, in order to completely fill the concave portion 2 on the surface of the substrate 1 with the deposited layer 4 without any voids by sintering, it is necessary to use ultrafine glass particles with a particle size of 0.05 to 0.2 nm. must be deposited uniformly on the substrate I without any gaps, so there were problems in that it was difficult to control the deposition process and the deposition took a long time. For this reason, the objective of lowering the manufacturing cost of the dielectric isolation substrate could not be fully achieved.

この発明は、以上述べた超微粒子の堆積のために誘電体
分離基板の製造コストが高くなると云う問題点を除去し
、経済性の優れた誘電体分離基板の製造方法を提供する
ことを目的とする。
The purpose of the present invention is to eliminate the above-mentioned problem that the production cost of dielectric isolation substrates increases due to the deposition of ultrafine particles, and to provide an economical method for producing dielectric isolation substrates. do.

(課題を解決するための手段) この発明は、基板接合技術による誘電体分離基板の製造
方法において、両シリコン基板を接合する物質として、
シリコンよりも低い融点を有する、シリコン母材の合金
を用い、この合金の溶融・凝固により第1のシリコン基
板表面の凹部内を充填すると共に両シリコン基板を接合
するようにしたものである、, (作 用) 前記合金の融液は10t〜10−’poise程度の低
い粘性率を有する.したがって、前記合金の溶融熱処理
による、第1のシリコン基板表面の凹部内への前記合金
の完全な充填は、溶融前の合金形状が、数一以上の粒径
の粒子状又は薄板状であっても可能となる.そして、こ
のような大粒子状または薄板状のものを使用できれば、
合金層(接合層)の堆積工程が大幅に簡略化される。
(Means for Solving the Problems) The present invention provides a method for manufacturing a dielectric separation substrate using substrate bonding technology, in which a substance for bonding both silicon substrates is used.
An alloy of silicon base material having a lower melting point than silicon is used, and by melting and solidifying this alloy, it fills the recess on the surface of the first silicon substrate and joins both silicon substrates. (Function) The melt of the alloy has a low viscosity of about 10t to 10-'poise. Therefore, the complete filling of the alloy into the recesses on the surface of the first silicon substrate by the melting heat treatment of the alloy is difficult because the shape of the alloy before melting is particle-like or thin-plate-like with a grain size of several tens or more. It also becomes possible. And if we can use such large particles or thin plates,
The process of depositing the alloy layer (bonding layer) is greatly simplified.

(実施例) 以下第1図(a)〜(e)に従い、この発明の実施例に
ついて説明する. まず第1図(a)に示すように、単結晶シリコン基板1
1の表面に、酸化膜】2をマスクにして異方性エノチン
グを行うことにより、深さ50一程度の凹部13を形戒
する. 次に第1図中〉に示すように、酸化膜12を除去後、単
結晶シリコン基板1lを酸化し、凹部13を含む基板表
面に膜厚2一程度の絶縁分離のための酸化膜14を形威
し、その後、該酸化膜14上に膜厚063一程度の多結
晶シリコン膜15を形或する。
(Example) Examples of the present invention will be described below with reference to FIGS. 1(a) to (e). First, as shown in FIG. 1(a), a single crystal silicon substrate 1
By performing anisotropic etching using the oxide film 2 as a mask, a recess 13 with a depth of about 50 mm is formed on the surface of 1. Next, as shown in FIG. 1, after removing the oxide film 12, the single-crystal silicon substrate 1l is oxidized, and an oxide film 14 for insulation isolation with a thickness of about 21 is formed on the substrate surface including the recesses 13. After that, a polycrystalline silicon film 15 having a thickness of about 0.6 mm is formed on the oxide film 14.

次に第1図(c)に示すように、単結晶シリコン基板I
l上に、シリコンよりも融点の低いシリコンーゲルマニ
ウム合金からなる厚さ100一程度の基板l6を置く.
又は、第2図に示すように、前記合金からなる粒径1〇
一程度の粒子16′を100一程度の厚さまで堆積させ
る.その後、その上に、支持体となる厚み500一程度
のシリコン基板17を置き、これに1350〜1400
℃の熱処理を加える。
Next, as shown in FIG. 1(c), a single crystal silicon substrate I
A substrate l6 having a thickness of about 100 mm and made of a silicon-germanium alloy having a melting point lower than that of silicon is placed on the substrate l.
Alternatively, as shown in FIG. 2, particles 16' made of the alloy and having a grain size of about 101 are deposited to a thickness of about 1001. Thereafter, a silicon substrate 17 with a thickness of about 500 mm is placed on top of it, and a silicon substrate 17 with a thickness of about 1350 to 1400 mm
Add heat treatment at ℃.

これにより、第1図(2)に示すように、シリコンーゲ
ルマニウム合金基板16又は合金粒子16′は溶融し、
凹部13を完全に充填し、その後冷却することにより凝
固し、単結晶シリコン基板11とシリコン基板l7はシ
リコンーゲルマニウム合金層18を介して接合される. ここで、シリコンーゲルマニウム合金[18は、後の素
子形威の為の1200゜C程度の熱処理温度でも、接合
層として溶融しない必要がある。このシリコンーゲルマ
ニウム合金(Si−Ge合金)の融点の組或比に対する
依存性を第3図に示す.この図より、前記溶融を防止す
る上で、シリコンーゲルマニウム合金中のゲルマニウム
組或比は20〜40at%が適当である。
As a result, as shown in FIG. 1(2), the silicon-germanium alloy substrate 16 or the alloy particles 16' are melted.
The recess 13 is completely filled and then cooled to solidify, and the single crystal silicon substrate 11 and the silicon substrate 17 are bonded via the silicon-germanium alloy layer 18. Here, the silicon-germanium alloy [18] must not melt as a bonding layer even at a heat treatment temperature of about 1200° C. for later device shaping. Figure 3 shows the dependence of the melting point of this silicon-germanium alloy (Si-Ge alloy) on the composition ratio. From this figure, in order to prevent the above-mentioned melting, it is appropriate that the germanium composition ratio in the silicon-germanium alloy is 20 to 40 at%.

又前記多結晶シリコンlil5は、溶融したシリコンー
ゲルマニウム合金が凹部13内に浸入し完全に充填する
のを助ける働きを持つが、溶融の熱処理を減圧中で行な
えば省く事が出来る。
The polycrystalline silicon lil5 has a function of helping the molten silicon-germanium alloy to penetrate into the recess 13 and completely fill it, but it can be omitted if the melting heat treatment is performed under reduced pressure.

次に、単結晶シリコン基板1lの裏面側を、凹部13の
先端が露出するまで研削・研磨により除去することによ
り、第1図(e)に示すように、凹部13間の単結晶シ
リコン基板11部分が各単結晶シリコン島19として酸
化MI4により絶縁分離され且つシリコンーゲルマニウ
ム合金層l8を介してシリコン基板I7で保持された誘
電体分H基板が得られる. 尚前記実施例では、シリコンーゲルマニウム合金を用い
て説明したが、この発明では、同様にシリコンを母材と
し、合金化によりシリコンの融点より低い融点が得られ
るシリコンーコバルト合金あるいはシリコンー鉄合金等
を使用することも出来る。
Next, by removing the back side of the single crystal silicon substrate 1l by grinding and polishing until the tips of the recesses 13 are exposed, the single crystal silicon substrate 1l between the recesses 13 is removed, as shown in FIG. 1(e). A dielectric H substrate is obtained in which each monocrystalline silicon island 19 is insulated and isolated by oxidized MI4 and held by a silicon substrate I7 via a silicon-germanium alloy layer l8. In the above embodiments, a silicon-germanium alloy was used, but in the present invention, silicon-cobalt alloys, silicon-iron alloys, etc., which similarly have silicon as a base material and which have a melting point lower than that of silicon by alloying, are used. You can also use

(発明の効果) 以上詳細に説明したようにこの発明によれば、両シリコ
ン基板を接合する物質として、シリコンーゲルマニウム
合金のように、シリコンよりも低い融点を有する、シリ
コン母材の合金を用い、該合金の溶融・凝固により基板
表面の凹部内を充填すると共に両基板を接合する.この
合金によれば、融液は101〜10−’poise程度
の低い粘性率を有するので、該合金の溶融熱処理による
、基板表面の凹部内への該合金の完全な充填は、溶融前
の合金形状が数一以上の粒径の粒子状又は薄板状であっ
ても可能となる.そして、このような大粒子状または薄
板状のものを使用できるので、この発明によれば接合層
(合金層)の堆積工程が大幅に簡略化され、誘電体分離
基板の製造コストを低減出来る.
(Effects of the Invention) As explained in detail above, according to the present invention, an alloy of a silicon base material having a lower melting point than silicon, such as a silicon-germanium alloy, is used as a material for bonding both silicon substrates. , by melting and solidifying the alloy, it fills the recesses on the substrate surface and joins both substrates together. According to this alloy, since the melt has a low viscosity of about 101 to 10-'poise, it is difficult to completely fill the recesses of the substrate surface with the alloy by melt heat treatment of the alloy. This is possible even if the shape is particle-like or thin plate-like with a particle size of several tens or more. Since such large particles or thin plates can be used, the present invention greatly simplifies the process of depositing the bonding layer (alloy layer) and reduces the manufacturing cost of the dielectric isolation substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の誘電体分離基板の製造方法の実施例
を示す工程断面図、第2図は上記実施例における一部変
形例を示す断面図、第3図はシリコンーゲルマニウム合
金の融点の&l1威比に対する依存性を示す特性図、第
4図は従来の誘電体基板の製造方法を示す工程断面図で
ある。 11・・・単結晶シリコン基板、13・・・凹部、l4
・・・酸化膜、l6・・・シリコンーゲルマニウム合金
基板、1 6’・・・シリコンーゲルマニウム合金粒子
、17・・・シリコン基1、18・・・シリコンーゲル
マニウム合金層、 1 9・・・単結晶シリ コン島. 本発明の実施例 第tyl 本発明実施例1こお17る一部変形例 合金粒子 第2 図 S+ at % Ge Si−Ge合金の融点の組成比{こ対する依存性第3図
Fig. 1 is a process cross-sectional view showing an embodiment of the method for manufacturing a dielectric isolation substrate of the present invention, Fig. 2 is a cross-sectional view showing a partial modification of the above embodiment, and Fig. 3 is a melting point of a silicon-germanium alloy. FIG. 4 is a process sectional view showing a conventional method for manufacturing a dielectric substrate. 11... Single crystal silicon substrate, 13... Concave portion, l4
...Oxide film, l6...Silicon-germanium alloy substrate, 1 6'...Silicon-germanium alloy particles, 17...Silicon base 1, 18...Silicon-germanium alloy layer, 1 9...・Single crystal silicon island. Embodiments of the present invention Example 1 of the present invention Partially modified examples of alloy particles 2 Figure 3 Dependence of melting point of S+ at % Ge Si-Ge alloy on composition ratio

Claims (1)

【特許請求の範囲】 (a)第1のシリコン基板の第1の主表面側に凹部を形
成し、その凹部を含む第1の主表面側に絶縁膜を形成す
る工程と、 (b)その第1のシリコン基板の前記第1の主表面側に
、シリコンを母材とする、シリコンよりも低い融点を有
する合金からなる薄板又は粒子の層を設け、その上に第
2のシリコン基板を載置する工程と、 (c)その後、熱処理により前記合金の薄板又は粒子層
のみを溶融・凝固させ、第1のシリコン基板の凹部を前
記合金で埋めると同時に、該合金で第1及び第2のシリ
コン基板を接合する工程と、(2)その後、第1のシリ
コン基板を第2の主表面側から前記凹部の先端が露出す
るまで除去する工程とを具備してなる誘電体分離基板の
製造方法。
[Claims] (a) A step of forming a recess on the first main surface side of a first silicon substrate and forming an insulating film on the first main surface side including the recess; A thin plate or layer of particles made of an alloy having silicon as a base material and having a melting point lower than that of silicon is provided on the first main surface side of the first silicon substrate, and a second silicon substrate is placed thereon. (c) Thereafter, only the thin plate or particle layer of the alloy is melted and solidified by heat treatment, and the concave portion of the first silicon substrate is filled with the alloy, and at the same time, the alloy is used to melt and solidify only the thin plate or particle layer of the alloy. A method for manufacturing a dielectrically isolated substrate, comprising: a step of bonding a silicon substrate; and (2) a step of thereafter removing the first silicon substrate from the second main surface side until the tip of the recess is exposed. .
JP18587589A 1989-07-20 1989-07-20 Manufacture of dielectric isolating substrate Pending JPH0352250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18587589A JPH0352250A (en) 1989-07-20 1989-07-20 Manufacture of dielectric isolating substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18587589A JPH0352250A (en) 1989-07-20 1989-07-20 Manufacture of dielectric isolating substrate

Publications (1)

Publication Number Publication Date
JPH0352250A true JPH0352250A (en) 1991-03-06

Family

ID=16178409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18587589A Pending JPH0352250A (en) 1989-07-20 1989-07-20 Manufacture of dielectric isolating substrate

Country Status (1)

Country Link
JP (1) JPH0352250A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6814476B2 (en) 1999-03-15 2004-11-09 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror having an attachment member including an approach light
US6848816B2 (en) 2000-02-11 2005-02-01 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror
US6976761B2 (en) 1999-10-19 2005-12-20 Schefenacker Vision Systems Australia Pty Ltd Exterior vehicle mirror with forward folding feature

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6814476B2 (en) 1999-03-15 2004-11-09 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror having an attachment member including an approach light
US6981789B2 (en) 1999-03-15 2006-01-03 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror having an attachment member including an approach light
US6976761B2 (en) 1999-10-19 2005-12-20 Schefenacker Vision Systems Australia Pty Ltd Exterior vehicle mirror with forward folding feature
US7040770B1 (en) 1999-10-19 2006-05-09 Schefenacker Vision Systems Australia Pty Ltd. Exterior mirror
US6848816B2 (en) 2000-02-11 2005-02-01 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror
US7165853B2 (en) 2000-02-11 2007-01-23 Schefenacker Vision Systems Australia Pty Ltd Exterior mirror

Similar Documents

Publication Publication Date Title
JP3975634B2 (en) Manufacturing method of semiconductor wafer
JP3395661B2 (en) Method for manufacturing SOI wafer
JPH0312775B2 (en)
JPH0832038A (en) Manufacture of stuck soi substrate and stuck soi substrate
JPH02228023A (en) Manufacture of soi device employing excellend sealed layer
JPH0352250A (en) Manufacture of dielectric isolating substrate
JP2699359B2 (en) Semiconductor substrate manufacturing method
JPH01259539A (en) Soi substrate and manufacture thereof
JP3287436B2 (en) Method for manufacturing semiconductor device
JP2721265B2 (en) Semiconductor substrate manufacturing method
JPH0563071A (en) Manufacture of dielectric isolation substrate
JPH0437020A (en) Preparation of thermocompression bonding wafer
JPH056883A (en) Manufacture of semiconductor substrate
JPH04148525A (en) Soi substrate and its manufacture
JPH01230255A (en) Manufacture of semiconductor substrate
JP3327977B2 (en) Semiconductor substrate manufacturing method
JPH03265153A (en) Dielectric isolation substrate, manufacture thereof and semiconductor integrated circuit device using same substrate
JP2002057309A (en) Method of forming soi substrate
JPH06318633A (en) Manufacture of semiconductor substrate
JPH02155227A (en) Manufacture of semiconductor substrate
JP2981673B2 (en) Semiconductor substrate manufacturing method
TWI267901B (en) Semiconductor substrate and process for producing it
RU2197768C2 (en) Semiconductor structure manufacturing method
JPS61240676A (en) Manufacture of semiconductor thin film crystal
JPS63108708A (en) Formation of silicon single crystal thin film