JPH03292734A - Formation of si single crystal thin film - Google Patents

Abstract

PURPOSE:To control idealy the setting of the orientation of a specified face of Si single crystal thin films and to form the Si single crystal thin films, which are dielectrically isolated from one another at an arbitrary portion or are continued, by a method wherein a complete signal crystal film having the oritentation of a specified face is grown on a substrate containing SiO2 as its component. CONSTITUTION:The surface of a 4-inch (100) Si wafer 11 is oxidized up to a depth of 0.5mum and an insulator layer 12 is formed. Then, a SEG crystal is provided in opening parts 13 on the wafer 11, is grown until the surface of the SEG crystal becomes the same surface as that of the layer 12 and the opening parts 13 are filled with the SEG crystal 14. Then, the surface, which becomes flat by the SEG crystal, of the wafer 11 is made to closely adhere to the flat surface of a 4-inch melted quartz wafer 10 to form an interface 15 and (after the wafer 10 is made to adhere to the wafer 11, the side of the wafer 11 to the adhering wafer 10 is polished.) Thereby, a multitude of Si single crystal thin films, which are respectively 0.5mum in thickness, 50mum in longitudinal and lateral lengths and is a SEG film 14 of the orientation of a face (100), are formed on the quartz substitute 10 in a state that they are dielectrically isolated from one another.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application]
This invention relates to a method for producing an l-crystalline thin film.

[Prior Art] Conventionally, a semiconductor element formed on an S single crystal has an S1
It is known that the performance is greatly influenced by the orientation of the crystal plane. In addition, when a 31 film is formed on a different material, depending on the material, the Si film may be subjected to tensile or compressive forces.
It is also known that forces act, and these stresses also cause changes in the performance of semiconductor devices.

B-Y of MIT (Massachusetts Family Canine).

The report by Tsaur et al. states that they have demonstrated through calculations and experiments that when tensile stress is applied to a 31 film with a (100) plane orientation, the electron mobility in the film becomes extremely high.
(B-Y, Tsaur, John C, CF
an, and M, W, Gels, ^pp1. Phys.
, Lett, 40 (4), 15Feb, 1982)
.

According to this, a Si film with a (200) plane orientation that is subjected to downward stress by a quartz (SiO2) substrate has an electron mobility of 1
．． It is expected to be more than five times as large. In other words, a semiconductor element formed on a film subjected to stress can more easily achieve higher performance than a semiconductor element formed on a Si wafer.

However, tensile stress has the opposite effect on hole mobility, and in this case, it is necessary to select an orientation other than the (100) plane.

On the other hand, Si on a bulk SiO2 such as a quartz substrate
Although various methods for manufacturing single-crystal films have been reported in the past, methods for manufacturing a St perfect crystal thin film oriented in the (100) plane have hardly been developed.

However, as shown in Figure 4, for example, the above-mentioned MIT B
-Y, Tsaur et al.
Polycrystalline or amorphous) 41 is deposited and once melted and recrystallized by a rod-shaped heater 43, thereby forming (
100) proposed the so-called melt recrystallization method (hereinafter referred to as ZMR method) to obtain the orientation @42. This method utilizes the phenomenon that when liquid-phase Si crystallizes on the SiO7 surface, it is easy to select the orientation of the (100) plane with stable interfacial energy.

Another method is the so-called bonding method as shown in FIG. In this method, a Si wafer 51 and another support having an insulating material surface, for example, a Si wafer 52 having an oxide layer 53 on the surface, are brought into close contact with each other and bonded by heat treatment in an H2 atmosphere. Polishing is performed from one side to remove the oxide film 53 and the Si thin film 51''.
(La5ky, J,, B
,,5tiffer.

S, R,, White, F, R, and Aberna
They, J. R., “5ili-con On In
5ulator(Sol) by Bonding
and Etch-Back'' IEEE Inter
national electron devices
Meeting (IEDM) Technical D
igest, pp 684-687Dec, 1985
．． In addition, there are several reported examples).

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has the following problems.

First, in the ZMR method, as mentioned above, 5i02
Since the orientation of the Si interface is controlled by how well the interfacial energy is stabilized, the crystal orientation is affected by minute fluctuations such as scratches and irregularities on the substrate surface.
It is difficult to fabricate a perfectly crystalline thin film with a uniform plane orientation. In addition, it is generally known that Si films produced by the ZMR method are polycrystalline with large grains on the order of millimeters, which means that grain boundaries exist and the film It can be said that it is not possible to produce a uniform single crystal film over the entire area.

Next, regarding the above-mentioned bonding method, although it is possible to produce a wafer-sized perfect single crystal on a 5in2 surface, the particular problem is that the polishing must be controlled so as to leave a uniform film. This is extremely difficult.

In other words, Si wafers currently on the market inherently have a warp of several μm to several tens of μm, so even if the wafers are polished in parallel after bonding, considerable unevenness in film thickness will occur. It is from. Therefore, semiconductor elements formed in regions with different film thicknesses will have large variations in element performance due to differences in stress applied to the films and the presence or absence of thin film effects.

In order to solve the problems of the prior art described above, the present invention provides 3102
An object of the present invention is to provide a method for manufacturing a 31 single crystal thin film on a substrate, which can ideally control the orientation of a specific plane, has a uniform film thickness, and has no variation in semiconductor device performance.

[Means for Solving the Problems] The present invention has been achieved through extensive research to achieve the above objects.

The present invention provides Si! having a specific plane orientation on a substrate containing 5102 as a component! In method 7 for producing a crystalline thin film, a first step of forming an insulating layer on the surface of the Si wafer that can be selectively polished with Si and can also be used as a mask for selective epitaxial growth; a second step of providing an opening in the layer to form a mask and selectively epitaxially growing Si of the Si wafer, which is viewed through the opening, up to the surface of the insulating layer; A third step of bringing the surface into contact with the surface of the substrate and performing heat treatment to bond the corresponding contact portion, and performing selective polishing from the Si wafer side of the bonded substrate using the mask as a stopper. The method is characterized by including a fourth step.

[Operation (I) In the first step, an insulating layer is formed on the surface of the Si wafer.

Since the insulating layer functions both as a mask described later and as a stopper for selective polishing, it is necessary to select a material that can perform both functions. For example, the material is 5
i02, Si3 N4.5iON, and the like. When SiO2 is used as the material for the insulating layer, the surface of the Si wafer may be thermally oxidized. When using other materials, they are deposited by CVD or the like.

The thickness of the insulating layer is preferably set to a value of 0.1 to 1.0 μm, more preferably a value of 0.2 to 0.5 μm, as a thickness that can sufficiently exhibit both of the functions. Make it. Note that the optimum film thickness varies depending on the material of the mask and the method of subsequent polishing.

(II) In the second step, etching is performed to form an opening in the insulating layer, and then selective epitaxial growth (hereinafter referred to as S) is performed on the Si surface exposed through the opening.
(referred to as EG).

Although the size of the opening is arbitrary, it is effective to make it equal to the area of the vehicle body of the semiconductor element to be formed later, when the elements are integrated.

The growth of the SEG crystal obtained by performing SEG on the Si plane exposed from the opening is terminated when the SEG crystal becomes flush with the surface of the insulating layer serving as a mask. The SEG conditions are as follows: 5t) (silane-based gas such as 4,5i2Ha, and 5iH2CA2.5iHCu3.S).
A chlorosilane type gas such as iCβ4 or others can be used, and as the additive gas, HCfl or the like having an etching effect can be used. Moreover, H2 is used as a carrier gas. The temperature largely depends on the gas used, etc., but is 800 to 1200°C, preferably 900 to 1100°C.
Set to a range of The pressure is set in the range of several tens to 200 Torr, preferably around 100 Torr.

(III) In the third step, the substrate 1o made of 5in2 is brought into contact with the surface of the substrate subjected to the SEG, and heat treatment is performed to sufficiently bond the contact portion.

As the 5i02 substrate, any material can be used as long as it has 5in2 as a main component and can withstand the heat treatment temperature, such as fused quartz, synthetic quartz, and high heat-resistant glass. The temperature of the heat treatment is preferably around the glass transition temperature of the 5iOz substrate, and the atmosphere of the heat treatment is preferably hydrogen (H2) or a forming gas containing hydrogen.

(rV) In the fourth step, the Si wafer is selectively polished, and the polishing ends when the surface of the insulating layer is exposed.

There are roughly two types of M selective polishing methods. One is mechanical chemical polishing method (mechanochemical etching), and the other is mechanical stone Wa? (mechanical nitching)
It is. The former is a selective polishing method in which when the insulating layer serving as a mask is 5i02 plus 1, a special chemical polishing liquid is mixed in to make the polishing rate of Si and 5in2 significantly different (Ida, continuous layer, application). Journal of the Physical Society of Japan, Vol. 56, No. 11, p. 1480, etc.).

Specifically, the above polishing is performed using, for example, ethylene diamine,
This is done using an alkaline solution called ``hyrocatechol'' on a borizing cloth. The above chemical polishing liquid
)6'-, but it does not react with 5in2, so the exposed SiO2 surface becomes the polishing end position, and the exposed surface acts as a stopper. Note that this chemical reaction is not suitable for polishing polycrystalline S1 because the etching rate differs depending on the orientation of the Si plane, but there is no problem in polishing single crystal Si as in the present invention.

On the other hand, when using a material such as Si3N4, which has a Mohs hardness sufficiently higher than that of Si, as an insulating layer serving as a mask,
Material - Rough polishing method can be used (Patent application No. 63-24)
7819), this polishing method has a hardness equal to or higher than that of St, and Si.

This method uses abrasive grains with lower hardness than N4, such as colloidal silica, as an abrasive, and performs mechanical polishing. The colloidal silica has a Mohs hardness slightly higher than that of Si, but lower than St and N4. Therefore, Si3
When the N4 surface is exposed, the polishing rate decreases significantly and the polishing can be completed. Since this mechanical polishing does not involve chemical reactions, it is suitable for polishing films containing various plane orientations, such as polycrystalline Si, and also has the advantage of being able to achieve a higher polishing rate than mechanochemical etching.

By going through these steps, on the 5i02 substrate,
A Si single-crystal thin film in which the orientation of a specific plane is ideally regulated and has a uniform thickness, which can be applied to high-performance semiconductor devices, can be produced.

[Example] Hereinafter, an example of a method for manufacturing a Si single crystal thin film will be specifically described with reference to FIG. 1 and the like.

(First Example) In this example, 5iR of (100) plane orientation was formed on a quartz substrate.
This is to form an L crystal thin film.

(a) First, as shown in Figure 1 (a), a 4-inch (
100) The surface of the Si wafer 11 was oxidized to a depth of 0.5 μm to form an insulating layer 12.

The oxidation conditions are N2:02=3:2
The temperature was set at 1000° C. and the oxidation time was set at 3 hours.

Next, as shown in FIG. 2, the oxide film 22, which is an insulating layer, is formed into a 50x50 film using ordinary photolithography technology.
A region of 2 .mu.m2 was patterned in a lattice pattern with intervals of 10 .mu.m vertically and horizontally, and etched using an HF solution to form openings 13 (see FIG. 1(a)) and expose the Si wafer surface 23.

(b) As shown in FIG. 1(b), the s1 wafer 1
SEG was performed on the opening 13 on the substrate 1 to grow it until it was flush with the surface of the insulating layer 12, and the opening 13 was buried with the SEG crystal 14.

The SEG conditions in this case are as follows.

Gas type -S i H2Cn 2 / HCj2 /
H2 gas flow rate ratio...0.53/1.6/100 [f
l/min Temperature: 030 ['C] Pressure: too [rorr] Growth time: 220 [seC] As shown in Figure 1 (C), the SEG flattened the The surface of the fused silica wafer 10 is brought into close contact with the flat surface of the 4-inch fused silica wafer 10 to form an interface 15.
A heat treatment was performed at 980'C for 30 minutes in a 7R-ming gas atmosphere of 20:80 (%) to bond the contact portion.

(d) As shown in FIG. 1(d), the (100) Si wafer side of the bonded wafer was polished. in this case,
Since the thickness of the S1 wafer 11 is approximately 520 μm, alumina (Aj2203) was used until the 50 μm rough stone polishing.
Using coarse abrasive grains such as the following, stone polishing was then carried out using the mechanochemical etching method described above, and the polishing was completed when the surface of the insulating layer 12 was exposed. Specifically, while sliding the 31 single crystal part on a commercially available polishing cloth, pH=9.
5. Ethylenecyamine birocatechol was injected into the sliding surface at a temperature of 45° C. before polishing.

As a result, on the quartz substrate 10, the above-mentioned S
EG film] A large number of 5ill crystal thin films (4) were formed insulated and isolated from each other. Note that the SEG film 14
When one NMOS transistor is formed in the 5iJL crystal thin film region, its electron mobility is 800 cm'/
It showed a value of v·seC.

(Second Example) In this example, a Si single-crystal thin film with (l○0) orientation is formed on a quartz substrate.

(a') i1 As shown in Figure (a), 4 inch (10
0) Si3 on the surface of the Si wafer 11 by LPCVD
An insulator layer 12 of N4 was deposited to a thickness of 0.2 μm.

This deposition condition is SiH2CJ22 /NH3=
Using a mixed gas of 20/80 (S CCm), the temperature was 800°C, the degree of vacuum was 0°3 orr, and the deposition time was 6.
The duration was 0 minutes.

Next, a third layer is formed using conventional photolithography techniques.
As shown in the figure, a region 32 of 5×5 μm 2 was patterned in a lattice shape with intervals of 50 μm in the vertical and horizontal directions, and the other portions were etched by RIE (reactive ion etching) to form openings 13.

(bo) Next, as shown in FIG. 1(b), SEG was performed under the following conditions.

Gas type...S i H2Cl12/HCj! /H
2 Gas flow rate...0.53/2.4/100 [fL/
m1nl Temperature: 050 [℃] Pressure: -80 [Torr] Growth time: 200 [sec (c') As shown in figure (c), the surface flattened by the above SEG and 4 inches The flat surfaces of the fused silica wafers 10 are brought into close contact to form an interface 15, and the
A heat treatment was performed for 0 minutes to bond the adhesive portion.

(do) As shown in FIG. 1(d), the (100) Si wafer side of the bonded wafer is polished.

This polishing is the mechanical polishing described above, using colloidal silica as abrasive grains, and
The polishing was finished when the surface of No. 2 was exposed. Specifically, the single bonded portion of the Si wheel was slid on a commercially available borising cloth, and polishing was performed while colloidal silica suspended in a neutral solution was injected into the sliding portion. Here, the solution contains methanol.
The colloidal silica used had a particle size of 100 mm.

In this way, a continuous (1
The SWG film 14, which is a Si single crystal film with the orientation of the S
It was formed in an island-like region of the insulator layer 12, which is an i3N4 film.

(Third Example) In this example, 5i of (111) 4° off was placed on a quartz substrate.
jl crystal thin film is formed.

(a”) Hz at 4 inches as shown in Figure 1 (a))
5i3N41i12 was deposited to a thickness of 0.4 μm on the surface of the Si wafer 11 with an offset angle of 4° by LPCVD.
It was deposited to a thickness of . These deposition conditions are such that the deposition time is 120
The trip was the same as the second actual trip example above, except that the travel time was 1 minute.

Next, a second layer is formed using normal photolithography technology.
It was buttered and etched as shown in the figure. The opening area formed by etching is 70x70μm.
These are two square areas separated by 10 μm in the vertical and horizontal directions.

(b'') Next, as shown in FIG. 1(b), SEG was performed under the following conditions.

Gas type S i H2Cfl 2 / HC11/
H2 gas flow rate 0.60/2.2/100 (ρ/m
1n) Temperature: 1030°C Pressure: 100 Torr During growth f 320 S e C (c”) i1As shown in Figure (C), quartz substrates were bonded together under the same conditions as in the second embodiment, and (d”) Figure 1. (d)
As shown in the figure, an S1 wafer having an offset angle of 4° to (111) was polished by mechanical polishing in the same manner as in the second example.

In this way, on a quartz substrate, a large number of Si single crystal thin films each having a thickness of 0.4 μm and an offset angle of 4° to (111) of 70 μm in the vertical and horizontal directions were formed with sufficient insulation and separation from each other. I was able to form it.

[Effects of the Invention] As described above, according to the present invention, by growing a perfect single crystal film having a specific plane orientation on a substrate containing 5102 as a component, 31 single crystal ili? It is possible to ideally control the orientation of a specific plane of This allows uniform formation over the entire wafer surface.

[Brief explanation of the drawing]

Figures 1 (a,) to (d) are process diagrams according to embodiments of the present invention, Figures 2 and 3 are perspective views showing an example of patterning an insulator layer, and Figure 4 is a conventional ZMR Fig. 5 is a side sectional view explaining the conventional bonding method. (Explanation of symbols) 10...Quartz substrate, 11...St wafer 12.
... Insulator layer, 13... Opening, 14... SEG crystal, 15... Interface. Figure ρ 〃 2 □33

Claims (1)

[Claims] (1) In a method for producing a Si single crystal thin film with a specific plane orientation on a substrate containing SiO_2, the Si wafer surface can be selectively polished with Si, and can also be used as a mask for selective epitaxial growth. a first step of forming a usable insulating layer, forming an opening in the insulating layer to form a mask, and transferring Si of the Si wafer exposed through the opening to the surface of the insulating layer; a second step of performing selective epitaxial growth until the surface of the substrate has been selectively grown; a third step of bringing the surface on which the selective epitaxial growth has been performed into contact with the surface of the substrate and heat-treating the contact portion to bond the bonded portion; a fourth step of selectively polishing the Si wafer side of the substrate using the mask as a stopper.